Merge a776ebf394 into e1ae367084

Detect AMD engineering samples in randomx_boost.sh

CMakeLists.txt

@@ -14,7 +14,9 @@ option(WITH_HTTP            "Enable HTTP protocol support (client/server)" ON)
 option(WITH_DEBUG_LOG       "Enable debug log output" OFF)
 option(WITH_TLS             "Enable OpenSSL support" ON)
 option(WITH_ASM             "Enable ASM PoW implementations" ON)
-option(WITH_MSR             "Enable MSR mod & 1st-gen Ryzen fix" ON)
+option(WITH_ASM_AMD         "Enable ASM for AMD processors" ON)
+option(WITH_MSR             "Enable MSR mod" ON)
+option(WITH_MSR_ZEN         "Enable MSR mod for AMD Zen-based processors" ON)
 option(WITH_ENV_VARS        "Enable environment variables support in config file" ON)
 option(WITH_EMBEDDED_CONFIG "Enable internal embedded JSON config" OFF)
 option(WITH_OPENCL          "Enable OpenCL backend" ON)

cmake/asm.cmake

@@ -44,9 +44,17 @@ if (WITH_ASM AND NOT XMRIG_ARM AND CMAKE_SIZEOF_VOID_P EQUAL 8)
     set_property(TARGET ${XMRIG_ASM_LIBRARY} PROPERTY LINKER_LANGUAGE C)
 
     add_definitions(/DXMRIG_FEATURE_ASM)
+    if (WITH_ASM_AMD)
+        add_definitions(/DXMRIG_FEATURE_ASM_AMD)
+        message("-- WITH_ASM=ON (+amd)")
+    else()
+        message("-- WITH_ASM=ON (-amd)")
+    endif()
 else()
     set(XMRIG_ASM_SOURCES "")
     set(XMRIG_ASM_LIBRARY "")
 
     remove_definitions(/DXMRIG_FEATURE_ASM)
+    remove_definitions(/DXMRIG_FEATURE_ASM_AMD)
+    message("-- WITH_ASM=OFF")
 endif()

cmake/randomx.cmake

@@ -104,8 +104,13 @@ if (WITH_RANDOMX)
 
     if (WITH_MSR AND NOT XMRIG_ARM AND CMAKE_SIZEOF_VOID_P EQUAL 8 AND (XMRIG_OS_WIN OR XMRIG_OS_LINUX))
         add_definitions(/DXMRIG_FEATURE_MSR)
-        add_definitions(/DXMRIG_FIX_RYZEN)
-        message("-- WITH_MSR=ON")
+        if (WITH_MSR_ZEN)
+            add_definitions(/DXMRIG_FIX_RYZEN)
+            message("-- WITH_MSR=ON (+zen)")
+        else()
+            remove_definitions(/DXMRIG_FIX_RYZEN)
+            message("-- WITH_MSR=ON (-zen)")
+        endif()
 
         if (XMRIG_OS_WIN)
             list(APPEND SOURCES_CRYPTO

scripts/randomx_boost.sh

@@ -8,7 +8,7 @@ else
 	modprobe msr allow_writes=on
 fi
 
-if grep -E 'AMD Ryzen|AMD EPYC' /proc/cpuinfo > /dev/null;
+if grep -E 'AMD Ryzen|AMD EPYC|AuthenticAMD' /proc/cpuinfo > /dev/null;
 	then
 	if grep "cpu family[[:space:]]\{1,\}:[[:space:]]25" /proc/cpuinfo > /dev/null;
 		then
@@ -28,6 +28,14 @@ if grep -E 'AMD Ryzen|AMD EPYC' /proc/cpuinfo > /dev/null;
 					wrmsr -a 0xc001102b 0x2000cc10
 					echo "MSR register values for Zen3 applied"
 				fi
+		elif grep "cpu family[[:space:]]\{1,\}:[[:space:]]26" /proc/cpuinfo > /dev/null;
+			then
+				echo "Detected Zen5 CPU"
+				wrmsr -a 0xc0011020 0x4400000000000
+				wrmsr -a 0xc0011021 0x4000000000040
+				wrmsr -a 0xc0011022 0x8680000401570000
+				wrmsr -a 0xc001102b 0x2040cc10
+				echo "MSR register values for Zen5 applied"
 		else
 			echo "Detected Zen1/Zen2 CPU"
 			wrmsr -a 0xc0011020 0

src/backend/cpu/CpuWorker.cpp

@@ -359,7 +359,9 @@ void xmrig::CpuWorker<N>::start()
             }
         }
 
-        consumeJob();
+        if (!Nonce::isPaused()) {
+            consumeJob();
+        }
     }
 }
 

src/backend/cpu/platform/HwlocCpuInfo.cpp

@@ -326,7 +326,8 @@ void xmrig::HwlocCpuInfo::processTopLevelCache(hwloc_obj_t cache, const Algorith
         }
     }
 
-    if (scratchpad == 2 * oneMiB) {
+    // This code is supposed to run only on Intel CPUs
+    if ((vendor() == VENDOR_INTEL) && (scratchpad == 2 * oneMiB)) {
         if (L2 && (cores.size() * oneMiB) == L2 && L2_associativity == 16 && L3 >= L2) {
             L3    = L2;
             extra = L2;

src/backend/cuda/CudaWorker.cpp

@@ -158,7 +158,7 @@ void xmrig::CudaWorker::start()
             std::this_thread::yield();
         }
 
-        if (!consumeJob()) {
+        if (isReady() && !consumeJob()) {
             return;
         }
     }

src/backend/opencl/OclWorker.cpp

@@ -190,7 +190,7 @@ void xmrig::OclWorker::start()
             std::this_thread::yield();
         }
 
-        if (!consumeJob()) {
+        if (isReady() && !consumeJob()) {
             return;
         }
     }

src/core/Miner.cpp

@@ -576,6 +576,11 @@ void xmrig::Miner::setJob(const Job &job, bool donate)
 
 #   ifdef XMRIG_ALGO_RANDOMX
     const bool ready = d_ptr->initRX();
+
+    // Always reset nonce on RandomX dataset change
+    if (!ready) {
+        d_ptr->reset = true;
+    }
 #   else
     constexpr const bool ready = true;
 #   endif

src/core/config/usage.h

@@ -94,7 +94,13 @@ static inline const std::string &usage()
 #   ifdef XMRIG_ALGO_RANDOMX
     u += "      --huge-pages-jit          enable huge pages support for RandomX JIT code\n";
 #   endif
+#   ifdef XMRIG_FEATURE_ASM
+#   ifdef XMRIG_FEATURE_ASM_AMD
     u += "      --asm=ASM                 ASM optimizations, possible values: auto, none, intel, ryzen, bulldozer\n";
+#   else
+    u += "      --asm=ASM                 ASM optimizations, possible values: auto, none, intel\n";
+#   endif
+#   endif
 
 #   if defined(__x86_64__) || defined(_M_AMD64)
     u += "      --argon2-impl=IMPL        argon2 implementation: x86_64, SSE2, SSSE3, XOP, AVX2, AVX-512F\n";

src/crypto/cn/CnHash.cpp

@@ -55,6 +55,7 @@ bool cn_vaes_enabled = false;
 
 
 #ifdef XMRIG_FEATURE_ASM
+#ifdef XMRIG_FEATURE_ASM_AMD
 #   define ADD_FN_ASM(algo) do {                                                                                    \
         m_map[algo]->data[AV_SINGLE][Assembly::INTEL]     = cryptonight_single_hash_asm<algo, Assembly::INTEL>;     \
         m_map[algo]->data[AV_SINGLE][Assembly::RYZEN]     = cryptonight_single_hash_asm<algo, Assembly::RYZEN>;     \
@@ -63,34 +64,50 @@ bool cn_vaes_enabled = false;
         m_map[algo]->data[AV_DOUBLE][Assembly::RYZEN]     = cryptonight_double_hash_asm<algo, Assembly::RYZEN>;     \
         m_map[algo]->data[AV_DOUBLE][Assembly::BULLDOZER] = cryptonight_double_hash_asm<algo, Assembly::BULLDOZER>; \
     } while (0)
+#else
+#   define ADD_FN_ASM(algo) do {                                                                                    \
+        m_map[algo]->data[AV_SINGLE][Assembly::INTEL]     = cryptonight_single_hash_asm<algo, Assembly::INTEL>;     \
+        m_map[algo]->data[AV_DOUBLE][Assembly::INTEL]     = cryptonight_double_hash_asm<algo, Assembly::INTEL>;     \
+    } while (0)
+#endif
 
 
 namespace xmrig {
 
 
 cn_mainloop_fun        cn_half_mainloop_ivybridge_asm             = nullptr;
+#ifdef XMRIG_FEATURE_ASM_AMD
 cn_mainloop_fun        cn_half_mainloop_ryzen_asm                 = nullptr;
 cn_mainloop_fun        cn_half_mainloop_bulldozer_asm             = nullptr;
+#endif
 cn_mainloop_fun        cn_half_double_mainloop_sandybridge_asm    = nullptr;
 
 cn_mainloop_fun        cn_trtl_mainloop_ivybridge_asm             = nullptr;
+#ifdef XMRIG_FEATURE_ASM_AMD
 cn_mainloop_fun        cn_trtl_mainloop_ryzen_asm                 = nullptr;
 cn_mainloop_fun        cn_trtl_mainloop_bulldozer_asm             = nullptr;
+#endif
 cn_mainloop_fun        cn_trtl_double_mainloop_sandybridge_asm    = nullptr;
 
 cn_mainloop_fun        cn_tlo_mainloop_ivybridge_asm              = nullptr;
+#ifdef XMRIG_FEATURE_ASM_AMD
 cn_mainloop_fun        cn_tlo_mainloop_ryzen_asm                  = nullptr;
 cn_mainloop_fun        cn_tlo_mainloop_bulldozer_asm              = nullptr;
+#endif
 cn_mainloop_fun        cn_tlo_double_mainloop_sandybridge_asm     = nullptr;
 
 cn_mainloop_fun        cn_zls_mainloop_ivybridge_asm              = nullptr;
+#ifdef XMRIG_FEATURE_ASM_AMD
 cn_mainloop_fun        cn_zls_mainloop_ryzen_asm                  = nullptr;
 cn_mainloop_fun        cn_zls_mainloop_bulldozer_asm              = nullptr;
+#endif
 cn_mainloop_fun        cn_zls_double_mainloop_sandybridge_asm     = nullptr;
 
 cn_mainloop_fun        cn_double_mainloop_ivybridge_asm           = nullptr;
+#ifdef XMRIG_FEATURE_ASM_AMD
 cn_mainloop_fun        cn_double_mainloop_ryzen_asm               = nullptr;
 cn_mainloop_fun        cn_double_mainloop_bulldozer_asm           = nullptr;
+#endif
 cn_mainloop_fun        cn_double_double_mainloop_sandybridge_asm  = nullptr;
 
 cn_mainloop_fun        cn_upx2_mainloop_asm                       = nullptr;
@@ -160,31 +177,41 @@ static void patchAsmVariants()
     auto base = static_cast<uint8_t *>(VirtualMemory::allocateExecutableMemory(allocation_size, false));
 
     cn_half_mainloop_ivybridge_asm              = reinterpret_cast<cn_mainloop_fun>         (base + 0x0000);
+#   ifdef XMRIG_FEATURE_ASM_AMD
     cn_half_mainloop_ryzen_asm                  = reinterpret_cast<cn_mainloop_fun>         (base + 0x1000);
     cn_half_mainloop_bulldozer_asm              = reinterpret_cast<cn_mainloop_fun>         (base + 0x2000);
+#   endif
     cn_half_double_mainloop_sandybridge_asm     = reinterpret_cast<cn_mainloop_fun>         (base + 0x3000);
 
 #   ifdef XMRIG_ALGO_CN_PICO
     cn_trtl_mainloop_ivybridge_asm              = reinterpret_cast<cn_mainloop_fun>         (base + 0x4000);
+#   ifdef XMRIG_FEATURE_ASM_AMD
     cn_trtl_mainloop_ryzen_asm                  = reinterpret_cast<cn_mainloop_fun>         (base + 0x5000);
     cn_trtl_mainloop_bulldozer_asm              = reinterpret_cast<cn_mainloop_fun>         (base + 0x6000);
+#   endif
     cn_trtl_double_mainloop_sandybridge_asm     = reinterpret_cast<cn_mainloop_fun>         (base + 0x7000);
 #   endif
 
     cn_zls_mainloop_ivybridge_asm               = reinterpret_cast<cn_mainloop_fun>         (base + 0x8000);
+#   ifdef XMRIG_FEATURE_ASM_AMD
     cn_zls_mainloop_ryzen_asm                   = reinterpret_cast<cn_mainloop_fun>         (base + 0x9000);
     cn_zls_mainloop_bulldozer_asm               = reinterpret_cast<cn_mainloop_fun>         (base + 0xA000);
+#   endif
     cn_zls_double_mainloop_sandybridge_asm      = reinterpret_cast<cn_mainloop_fun>         (base + 0xB000);
 
     cn_double_mainloop_ivybridge_asm            = reinterpret_cast<cn_mainloop_fun>         (base + 0xC000);
+#   ifdef XMRIG_FEATURE_ASM_AMD
     cn_double_mainloop_ryzen_asm                = reinterpret_cast<cn_mainloop_fun>         (base + 0xD000);
     cn_double_mainloop_bulldozer_asm            = reinterpret_cast<cn_mainloop_fun>         (base + 0xE000);
+#   endif
     cn_double_double_mainloop_sandybridge_asm   = reinterpret_cast<cn_mainloop_fun>         (base + 0xF000);
 
 #   ifdef XMRIG_ALGO_CN_PICO
     cn_tlo_mainloop_ivybridge_asm               = reinterpret_cast<cn_mainloop_fun>         (base + 0x10000);
+#   ifdef XMRIG_FEATURE_ASM_AMD
     cn_tlo_mainloop_ryzen_asm                   = reinterpret_cast<cn_mainloop_fun>         (base + 0x11000);
     cn_tlo_mainloop_bulldozer_asm               = reinterpret_cast<cn_mainloop_fun>         (base + 0x12000);
+#   endif
     cn_tlo_double_mainloop_sandybridge_asm      = reinterpret_cast<cn_mainloop_fun>         (base + 0x13000);
 #   endif
 
@@ -220,8 +247,10 @@ static void patchAsmVariants()
         constexpr uint32_t ITER = CnAlgo<Algorithm::CN_HALF>().iterations();
 
         patchCode(cn_half_mainloop_ivybridge_asm,            cnv2_mainloop_ivybridge_asm,           ITER);
+#       ifdef XMRIG_FEATURE_ASM_AMD
         patchCode(cn_half_mainloop_ryzen_asm,                cnv2_mainloop_ryzen_asm,               ITER);
         patchCode(cn_half_mainloop_bulldozer_asm,            cnv2_mainloop_bulldozer_asm,           ITER);
+#       endif
         patchCode(cn_half_double_mainloop_sandybridge_asm,   cnv2_double_mainloop_sandybridge_asm,  ITER);
     }
 
@@ -231,8 +260,10 @@ static void patchAsmVariants()
         constexpr uint32_t MASK = CnAlgo<Algorithm::CN_PICO_0>().mask();
 
         patchCode(cn_trtl_mainloop_ivybridge_asm,            cnv2_mainloop_ivybridge_asm,           ITER,   MASK);
+#       ifdef XMRIG_FEATURE_ASM_AMD
         patchCode(cn_trtl_mainloop_ryzen_asm,                cnv2_mainloop_ryzen_asm,               ITER,   MASK);
         patchCode(cn_trtl_mainloop_bulldozer_asm,            cnv2_mainloop_bulldozer_asm,           ITER,   MASK);
+#       endif
         patchCode(cn_trtl_double_mainloop_sandybridge_asm,   cnv2_double_mainloop_sandybridge_asm,  ITER,   MASK);
     }
 
@@ -241,8 +272,10 @@ static void patchAsmVariants()
         constexpr uint32_t MASK = CnAlgo<Algorithm::CN_PICO_TLO>().mask();
 
         patchCode(cn_tlo_mainloop_ivybridge_asm,             cnv2_mainloop_ivybridge_asm,           ITER,   MASK);
+#       ifdef XMRIG_FEATURE_ASM_AMD
         patchCode(cn_tlo_mainloop_ryzen_asm,                 cnv2_mainloop_ryzen_asm,               ITER,   MASK);
         patchCode(cn_tlo_mainloop_bulldozer_asm,             cnv2_mainloop_bulldozer_asm,           ITER,   MASK);
+#       endif
         patchCode(cn_tlo_double_mainloop_sandybridge_asm,    cnv2_double_mainloop_sandybridge_asm,  ITER,   MASK);
     }
 #   endif
@@ -251,8 +284,10 @@ static void patchAsmVariants()
         constexpr uint32_t ITER = CnAlgo<Algorithm::CN_ZLS>().iterations();
 
         patchCode(cn_zls_mainloop_ivybridge_asm,             cnv2_mainloop_ivybridge_asm,           ITER);
+#       ifdef XMRIG_FEATURE_ASM_AMD
         patchCode(cn_zls_mainloop_ryzen_asm,                 cnv2_mainloop_ryzen_asm,               ITER);
         patchCode(cn_zls_mainloop_bulldozer_asm,             cnv2_mainloop_bulldozer_asm,           ITER);
+#       endif
         patchCode(cn_zls_double_mainloop_sandybridge_asm,    cnv2_double_mainloop_sandybridge_asm,  ITER);
     }
 
@@ -260,8 +295,10 @@ static void patchAsmVariants()
         constexpr uint32_t ITER = CnAlgo<Algorithm::CN_DOUBLE>().iterations();
 
         patchCode(cn_double_mainloop_ivybridge_asm,          cnv2_mainloop_ivybridge_asm,           ITER);
+#       ifdef XMRIG_FEATURE_ASM_AMD
         patchCode(cn_double_mainloop_ryzen_asm,              cnv2_mainloop_ryzen_asm,               ITER);
         patchCode(cn_double_mainloop_bulldozer_asm,          cnv2_mainloop_bulldozer_asm,           ITER);
+#       endif
         patchCode(cn_double_double_mainloop_sandybridge_asm, cnv2_double_mainloop_sandybridge_asm,  ITER);
     }
 

src/crypto/cn/CryptoNight_x86.h

@@ -852,12 +852,16 @@ extern "C" void cnv1_single_mainloop_asm(cryptonight_ctx * *ctx);
 extern "C" void cnv1_double_mainloop_asm(cryptonight_ctx **ctx);
 extern "C" void cnv1_quad_mainloop_asm(cryptonight_ctx **ctx);
 extern "C" void cnv2_mainloop_ivybridge_asm(cryptonight_ctx **ctx);
+#ifdef XMRIG_FEATURE_ASM_AMD
 extern "C" void cnv2_mainloop_ryzen_asm(cryptonight_ctx **ctx);
 extern "C" void cnv2_mainloop_bulldozer_asm(cryptonight_ctx **ctx);
+#endif
 extern "C" void cnv2_double_mainloop_sandybridge_asm(cryptonight_ctx **ctx);
 extern "C" void cnv2_rwz_mainloop_asm(cryptonight_ctx **ctx);
 extern "C" void cnv2_rwz_double_mainloop_asm(cryptonight_ctx **ctx);
+#ifdef XMRIG_FEATURE_ASM_AMD
 extern "C" void cnv2_upx_double_mainloop_zen3_asm(cryptonight_ctx **ctx);
+#endif
 
 
 namespace xmrig {
@@ -867,28 +871,38 @@ typedef void (*cn_mainloop_fun)(cryptonight_ctx **ctx);
 
 
 extern cn_mainloop_fun cn_half_mainloop_ivybridge_asm;
+#ifdef XMRIG_FEATURE_ASM_AMD
 extern cn_mainloop_fun cn_half_mainloop_ryzen_asm;
 extern cn_mainloop_fun cn_half_mainloop_bulldozer_asm;
+#endif
 extern cn_mainloop_fun cn_half_double_mainloop_sandybridge_asm;
 
 extern cn_mainloop_fun cn_trtl_mainloop_ivybridge_asm;
+#ifdef XMRIG_FEATURE_ASM_AMD
 extern cn_mainloop_fun cn_trtl_mainloop_ryzen_asm;
 extern cn_mainloop_fun cn_trtl_mainloop_bulldozer_asm;
+#endif
 extern cn_mainloop_fun cn_trtl_double_mainloop_sandybridge_asm;
 
 extern cn_mainloop_fun cn_tlo_mainloop_ivybridge_asm;
+#ifdef XMRIG_FEATURE_ASM_AMD
 extern cn_mainloop_fun cn_tlo_mainloop_ryzen_asm;
 extern cn_mainloop_fun cn_tlo_mainloop_bulldozer_asm;
+#endif
 extern cn_mainloop_fun cn_tlo_double_mainloop_sandybridge_asm;
 
 extern cn_mainloop_fun cn_zls_mainloop_ivybridge_asm;
+#ifdef XMRIG_FEATURE_ASM_AMD
 extern cn_mainloop_fun cn_zls_mainloop_ryzen_asm;
 extern cn_mainloop_fun cn_zls_mainloop_bulldozer_asm;
+#endif
 extern cn_mainloop_fun cn_zls_double_mainloop_sandybridge_asm;
 
 extern cn_mainloop_fun cn_double_mainloop_ivybridge_asm;
+#ifdef XMRIG_FEATURE_ASM_AMD
 extern cn_mainloop_fun cn_double_mainloop_ryzen_asm;
 extern cn_mainloop_fun cn_double_mainloop_bulldozer_asm;
+#endif
 extern cn_mainloop_fun cn_double_double_mainloop_sandybridge_asm;
 
 extern cn_mainloop_fun cn_upx2_mainloop_asm;
@@ -964,46 +978,54 @@ inline void cryptonight_single_hash_asm(const uint8_t *__restrict__ input, size_
         if (ASM == Assembly::INTEL) {
             cnv2_mainloop_ivybridge_asm(ctx);
         }
+#       ifdef XMRIG_FEATURE_ASM_AMD
         else if (ASM == Assembly::RYZEN) {
             cnv2_mainloop_ryzen_asm(ctx);
         }
         else {
             cnv2_mainloop_bulldozer_asm(ctx);
         }
+#       endif
     }
     else if (ALGO == Algorithm::CN_HALF) {
         if (ASM == Assembly::INTEL) {
             cn_half_mainloop_ivybridge_asm(ctx);
         }
+#       ifdef XMRIG_FEATURE_ASM_AMD
         else if (ASM == Assembly::RYZEN) {
             cn_half_mainloop_ryzen_asm(ctx);
         }
         else {
             cn_half_mainloop_bulldozer_asm(ctx);
         }
+#       endif
     }
 #   ifdef XMRIG_ALGO_CN_PICO
     else if (ALGO == Algorithm::CN_PICO_0) {
         if (ASM == Assembly::INTEL) {
             cn_trtl_mainloop_ivybridge_asm(ctx);
         }
+#       ifdef XMRIG_FEATURE_ASM_AMD
         else if (ASM == Assembly::RYZEN) {
             cn_trtl_mainloop_ryzen_asm(ctx);
         }
         else {
             cn_trtl_mainloop_bulldozer_asm(ctx);
         }
+#       endif
     }
     else if (ALGO == Algorithm::CN_PICO_TLO) {
         if (ASM == Assembly::INTEL) {
             cn_tlo_mainloop_ivybridge_asm(ctx);
         }
+#       ifdef XMRIG_FEATURE_ASM_AMD
         else if (ASM == Assembly::RYZEN) {
             cn_tlo_mainloop_ryzen_asm(ctx);
         }
         else {
             cn_tlo_mainloop_bulldozer_asm(ctx);
         }
+#       endif
     }
 #   endif
     else if (ALGO == Algorithm::CN_RWZ) {
@@ -1013,23 +1035,27 @@ inline void cryptonight_single_hash_asm(const uint8_t *__restrict__ input, size_
         if (ASM == Assembly::INTEL) {
             cn_zls_mainloop_ivybridge_asm(ctx);
         }
+#       ifdef XMRIG_FEATURE_ASM_AMD
         else if (ASM == Assembly::RYZEN) {
             cn_zls_mainloop_ryzen_asm(ctx);
         }
         else {
             cn_zls_mainloop_bulldozer_asm(ctx);
         }
+#       endif
     }
     else if (ALGO == Algorithm::CN_DOUBLE) {
         if (ASM == Assembly::INTEL) {
             cn_double_mainloop_ivybridge_asm(ctx);
         }
+#       ifdef XMRIG_FEATURE_ASM_AMD
         else if (ASM == Assembly::RYZEN) {
             cn_double_mainloop_ryzen_asm(ctx);
         }
         else {
             cn_double_mainloop_bulldozer_asm(ctx);
         }
+#       endif
     }
 #   ifdef XMRIG_ALGO_CN_FEMTO
     else if (ALGO == Algorithm::CN_UPX2) {
@@ -1094,12 +1120,16 @@ inline void cryptonight_double_hash_asm(const uint8_t *__restrict__ input, size_
 #   endif
 #   ifdef XMRIG_ALGO_CN_FEMTO
     else if (ALGO == Algorithm::CN_UPX2) {
+#       ifdef XMRIG_FEATURE_ASM_AMD
         if (Cpu::info()->arch() == ICpuInfo::ARCH_ZEN3) {
             cnv2_upx_double_mainloop_zen3_asm(ctx);
         }
         else {
             cn_upx2_double_mainloop_asm(ctx);
         }
+#       else
+        cn_upx2_double_mainloop_asm(ctx);
+#       endif
     }
 #   endif
     else if (ALGO == Algorithm::CN_RWZ) {

src/crypto/cn/asm/cn_main_loop.S

@@ -15,12 +15,16 @@
 .global FN_PREFIX(cnv1_double_mainloop_asm)
 .global FN_PREFIX(cnv1_quad_mainloop_asm)
 .global FN_PREFIX(cnv2_mainloop_ivybridge_asm)
+#ifdef XMRIG_FEATURE_ASM_AMD
 .global FN_PREFIX(cnv2_mainloop_ryzen_asm)
 .global FN_PREFIX(cnv2_mainloop_bulldozer_asm)
+#endif
 .global FN_PREFIX(cnv2_double_mainloop_sandybridge_asm)
 .global FN_PREFIX(cnv2_rwz_mainloop_asm)
 .global FN_PREFIX(cnv2_rwz_double_mainloop_asm)
+#ifdef XMRIG_FEATURE_ASM_AMD
 .global FN_PREFIX(cnv2_upx_double_mainloop_zen3_asm)
+#endif
 
 ALIGN(64)
 FN_PREFIX(cnv1_single_mainloop_asm):
@@ -58,6 +62,7 @@ FN_PREFIX(cnv2_mainloop_ivybridge_asm):
 	ret 0
 	mov eax, 3735929054
 
+#ifdef XMRIG_FEATURE_ASM_AMD
 ALIGN(64)
 FN_PREFIX(cnv2_mainloop_ryzen_asm):
 	sub rsp, 48
@@ -75,6 +80,7 @@ FN_PREFIX(cnv2_mainloop_bulldozer_asm):
 	add rsp, 48
 	ret 0
 	mov eax, 3735929054
+#endif
 
 ALIGN(64)
 FN_PREFIX(cnv2_double_mainloop_sandybridge_asm):
@@ -103,6 +109,7 @@ FN_PREFIX(cnv2_rwz_double_mainloop_asm):
 	ret 0
 	mov eax, 3735929054
 
+#ifdef XMRIG_FEATURE_ASM_AMD
 ALIGN(64)
 FN_PREFIX(cnv2_upx_double_mainloop_zen3_asm):
 	sub rsp, 48
@@ -111,6 +118,7 @@ FN_PREFIX(cnv2_upx_double_mainloop_zen3_asm):
 	add rsp, 48
 	ret 0
 	mov eax, 3735929054
+#endif
 
 #if defined(__linux__) && defined(__ELF__)
 .section .note.GNU-stack,"",%progbits

src/crypto/cn/asm/win64/cn_main_loop.S

@@ -5,12 +5,16 @@
 .global cnv1_double_mainloop_asm
 .global cnv1_quad_mainloop_asm
 .global cnv2_mainloop_ivybridge_asm
+#ifdef XMRIG_FEATURE_ASM_AMD
 .global cnv2_mainloop_ryzen_asm
 .global cnv2_mainloop_bulldozer_asm
+#endif
 .global cnv2_double_mainloop_sandybridge_asm
 .global cnv2_rwz_mainloop_asm
 .global cnv2_rwz_double_mainloop_asm
+#ifdef XMRIG_FEATURE_ASM_AMD
 .global cnv2_upx_double_mainloop_zen3_asm
+#endif
 
 ALIGN(64)
 cnv1_single_mainloop_asm:
@@ -36,6 +40,7 @@ cnv2_mainloop_ivybridge_asm:
 	ret 0
 	mov eax, 3735929054
 
+#ifdef XMRIG_FEATURE_ASM_AMD
 ALIGN(64)
 cnv2_mainloop_ryzen_asm:
 	#include "../cn2/cnv2_main_loop_ryzen.inc"
@@ -47,6 +52,7 @@ cnv2_mainloop_bulldozer_asm:
 	#include "../cn2/cnv2_main_loop_bulldozer.inc"
 	ret 0
 	mov eax, 3735929054
+#endif
 
 ALIGN(64)
 cnv2_double_mainloop_sandybridge_asm:
@@ -66,8 +72,10 @@ cnv2_rwz_double_mainloop_asm:
 	ret 0
 	mov eax, 3735929054
 
+#ifdef XMRIG_FEATURE_ASM_AMD
 ALIGN(64)
 cnv2_upx_double_mainloop_zen3_asm:
 	#include "cn2/cnv2_upx_double_mainloop_zen3.inc"
 	ret 0
 	mov eax, 3735929054
+#endif

src/crypto/ghostrider/README.md

@@ -16,7 +16,7 @@ xmrig -a gr -o rtm.suprnova.cc:4273 --tls -u WALLET_ADDRESS -p x
 
 You can use **rtm_ghostrider_example.cmd** as a template and put pool URL and your wallet address there. The general XMRig documentation is available [here](https://xmrig.com/docs/miner).
 
-**Using `--threads` or `-t` option is NOT recommended because it turns off advanced built-in config.** If you want to tweak the nubmer of threads used for GhostRider, it's recommended to start using config.json instead of command line. The best suitable command line option for this is `--cpu-max-threads-hint=N` where N can be between 0 and 100.
+**Using `--threads` or `-t` option is NOT recommended because it turns off advanced built-in config.** If you want to tweak the number of threads used for GhostRider, it's recommended to start using config.json instead of command line. The best suitable command line option for this is `--cpu-max-threads-hint=N` where N can be between 0 and 100.
 
 ## Performance
 

src/crypto/randomx/jit_compiler_x86.cpp

@@ -267,8 +267,8 @@ namespace randomx {
 						initDatasetAVX2 = false;
 						break;
 					case xmrig::ICpuInfo::ARCH_ZEN5:
-						// TODO: test it
-						initDatasetAVX2 = false;
+						// AVX2 init is 49% faster on Zen5
+						initDatasetAVX2 = true;
 						break;
 					}
 				}

src/crypto/rx/RxConfig.cpp

@@ -60,8 +60,6 @@ static const std::array<MsrItems, kMsrArraySize> msrPresets = {
     MsrItems{{ 0xC0011020, 0ULL }, { 0xC0011021, 0x40ULL, ~0x20ULL }, { 0xC0011022, 0x1510000ULL }, { 0xC001102b, 0x2000cc16ULL }},
     MsrItems{{ 0xC0011020, 0x0004480000000000ULL }, { 0xC0011021, 0x001c000200000040ULL, ~0x20ULL }, { 0xC0011022, 0xc000000401570000ULL }, { 0xC001102b, 0x2000cc10ULL }},
     MsrItems{{ 0xC0011020, 0x0004400000000000ULL }, { 0xC0011021, 0x0004000000000040ULL, ~0x20ULL }, { 0xC0011022, 0x8680000401570000ULL }, { 0xC001102b, 0x2040cc10ULL }},
-
-    // TODO: Tune it for Zen5 when it's available
     MsrItems{{ 0xC0011020, 0x0004400000000000ULL }, { 0xC0011021, 0x0004000000000040ULL, ~0x20ULL }, { 0xC0011022, 0x8680000401570000ULL }, { 0xC001102b, 0x2040cc10ULL }},
 
     MsrItems{{ 0x1a4, 0xf }},

src/crypto/rx/RxVm.cpp

@@ -41,10 +41,12 @@ randomx_vm *xmrig::RxVm::create(RxDataset *dataset, uint8_t *scratchpad, bool so
         flags |= RANDOMX_FLAG_JIT;
     }
 
+#   ifdef XMRIG_FEATURE_ASM_AMD
     const auto asmId = assembly == Assembly::AUTO ? Cpu::info()->assembly() : assembly.id();
     if ((asmId == Assembly::RYZEN) || (asmId == Assembly::BULLDOZER)) {
         flags |= RANDOMX_FLAG_AMD;
     }
+#   endif
 
     return randomx_create_vm(static_cast<randomx_flags>(flags), !dataset->get() ? dataset->cache()->get() : nullptr, dataset->get(), scratchpad, node);
 }

src/version.h

@@ -22,7 +22,7 @@
 #define APP_ID        "xmrig"
 #define APP_NAME      "XMRig"
 #define APP_DESC      "XMRig miner"
-#define APP_VERSION   "6.22.0"
+#define APP_VERSION   "6.22.1-dev"
 #define APP_DOMAIN    "xmrig.com"
 #define APP_SITE      "www.xmrig.com"
 #define APP_COPYRIGHT "Copyright (C) 2016-2024 xmrig.com"
@@ -30,7 +30,7 @@
 
 #define APP_VER_MAJOR  6
 #define APP_VER_MINOR  22
-#define APP_VER_PATCH  0
+#define APP_VER_PATCH  1
 
 #ifdef _MSC_VER
 #   if (_MSC_VER >= 1930)