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Author SHA1 Message Date
XMRig
9af8ceb063 v2.4.5 RC 2018-02-19 04:31:50 +07:00
xmrig
f5a0429f0d Update README.md 2018-02-19 04:17:50 +07:00
xmrig
cc22c9d61c Update README.md 2018-02-18 05:49:37 +07:00
xmrig
45f5afd2b7 Merge pull request #379 from DeadManWalkingTO/master
Update README.md
2018-02-18 05:48:09 +07:00
xmrig
c9acc2912e Update CHANGELOG.md 2018-02-18 05:32:36 +07:00
xmrig
f0604d1e97 Update README.md 2018-02-18 05:06:10 +07:00
XMRig
531c657b64 Merge branch 'master' of github.com:xmrig/xmrig 2018-02-08 17:35:20 +07:00
XMRig
c50ccd4e06 Merge branch 'Foudge-master' 2018-02-08 17:34:33 +07:00
XMRig
184f79ad3f Fix code style, replace tabs to space #2. 2018-02-08 17:21:12 +07:00
XMRig
e78e810cfe Fix code style, replace tabs to space. 2018-02-08 17:02:32 +07:00
XMRig
c804ef1888 Merge branch 'master' of https://github.com/Foudge/xmrig into Foudge-master 2018-02-08 16:56:20 +07:00
Foudge
037abd7037 Correct L2 cache size calculation for Intel Core 2 family
This is a workaround for total L2 cache size calculation of Intel Core Solo, Core Duo, Core 2 Duo, Core 2 Quad and their Xeon homologue. These processors have L2 cache shared by 2 cores.

There is maybe more CPU with L2 shared cache, but I am sure that these models are concerned and they are not so numerous.
A better way would be to modify libcpuid to implement L2 cache counting.
2018-02-03 16:31:13 +01:00
DeadManWalking
75f462f0e1 Update README.md 2018-02-02 00:58:11 +02:00
DeadManWalking
9f92449e15 Update README.md 2018-02-02 00:54:58 +02:00
DeadManWalking
a917590862 Update README.md 2018-02-02 00:14:39 +02:00
DeadManWalking
41b92740ea Merge pull request #1 from xmrig/master
!
2018-02-01 23:02:32 +02:00
Foudge
d2964576c7 Compilation error under FreeBSD
ULONG is not recognized under this OS, so replaced it with more portable definition.
2018-01-28 18:13:00 +01:00
Foudge
9a28ad590c up to 20% perf increase with Cryptonight with non-AES CPU
This time, the performance increase is got with MSVC and GCC. On non-AES CPU, there were an useless load/store SSE2 register. The last MSVC "hack" is replaced by a portable code and he's more complete (a load is saved).

On my C2Q6600, with 3 thread, I have +16% with MSVC2015 and +20% with GCC 7.3, compared to official 2.4.4 version.
2018-01-28 12:58:19 +01:00
Foudge
15fe6ce23f Remove compilation warnings under MSVC 2018-01-27 11:42:22 +01:00
xmrig
17f90de677 Merge pull request #353 from Foudge/master
up to 15% boost on CryptoNight algo with non-AES CPU
2018-01-26 00:53:22 +07:00
XMRig
631fd755c8 #341 Added option --dry-run. 2018-01-20 20:43:31 +07:00
Foudge
9bceb65ad8 +15% boost with non-AES CPU
Performance boost validated on Core 2 Quad processor under Windows 10.
But it's Windows/MS Visual C++ specific.
2018-01-20 10:43:56 +01:00
XMRig
56ffa7af79 #341 Fix wrong exit code. 2018-01-20 12:58:43 +07:00
xmrig
f210708f3b Merge pull request #324 from stanz2g/master
can build without microhttpd when WITH_HTTPD=OFF
2018-01-20 01:35:12 +07:00
stanz2g
f93187b024 can build without microhttpd when WITH_HTTPD=OFF 2018-01-06 17:07:07 +08:00
14 changed files with 109 additions and 72 deletions

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@@ -1,3 +1,8 @@
# v2.4.5
- [#324](https://github.com/xmrig/xmrig/pull/324) Fixed build without libmicrohttpd (CMake cache issue).
- [#341](https://github.com/xmrig/xmrig/issues/341) Fixed wrong exit code and added command line option `--dry-run`.
- [#385](https://github.com/xmrig/xmrig/pull/385) Up to 20% performance increase with for non-AES CPU and fixed Intel Core 2 cache detection.
# v2.4.4
- Added libmicrohttpd version to --version output.
- Fixed bug in singal handler, in some cases miner wasn't shutdown properly.

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@@ -195,6 +195,7 @@ if (WITH_HTTPD)
message(FATAL_ERROR "microhttpd NOT found: use `-DWITH_HTTPD=OFF` to build without http deamon support")
endif()
else()
set(MHD_LIBRARY "")
add_definitions(/DXMRIG_NO_HTTPD)
add_definitions(/DXMRIG_NO_API)
endif()

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@@ -1,4 +1,11 @@
# XMRig
[![Github All Releases](https://img.shields.io/github/downloads/xmrig/xmrig/total.svg)](https://github.com/xmrig/xmrig/releases)
[![GitHub release](https://img.shields.io/github/release/xmrig/xmrig/all.svg)](https://github.com/xmrig/xmrig/releases)
[![GitHub Release Date](https://img.shields.io/github/release-date-pre/xmrig/xmrig.svg)](https://github.com/xmrig/xmrig/releases)
[![GitHub license](https://img.shields.io/github/license/xmrig/xmrig.svg)](https://github.com/xmrig/xmrig/blob/master/LICENSE)
[![GitHub stars](https://img.shields.io/github/stars/xmrig/xmrig.svg)](https://github.com/xmrig/xmrig/stargazers)
[![GitHub forks](https://img.shields.io/github/forks/xmrig/xmrig.svg)](https://github.com/xmrig/xmrig/network)
XMRig is a high performance Monero (XMR) CPU miner, with official support for Windows.
Originally based on cpuminer-multi with heavy optimizations/rewrites and removing a lot of legacy code, since version 1.0.0 completely rewritten from scratch on C++.
@@ -37,16 +44,7 @@ Originally based on cpuminer-multi with heavy optimizations/rewrites and removin
* Clone with `git clone https://github.com/xmrig/xmrig.git` :hammer: [Build instructions](https://github.com/xmrig/xmrig/wiki/Build).
## Usage
### Basic example
```
xmrig.exe -o pool.monero.hashvault.pro:5555 -u YOUR_WALLET -p x -k
```
### Failover
```
xmrig.exe -o pool.monero.hashvault.pro:5555 -u YOUR_WALLET1 -p x -k -o pool.supportxmr.com:5555 -u YOUR_WALLET2 -p x -k
```
For failover you can add multiple pools, maximum count not limited.
Use [config.xmrig.com](https://config.xmrig.com/xmrig) to generate, edit or share configurations.
### Options
```

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@@ -113,7 +113,7 @@ App::~App()
int App::exec()
{
if (!m_options) {
return 0;
return 2;
}
uv_signal_start(&m_sigHUP, App::onSignal, SIGHUP);
@@ -130,6 +130,13 @@ int App::exec()
Mem::allocate(m_options->algo(), m_options->threads(), m_options->doubleHash(), m_options->hugePages());
Summary::print();
if (m_options->dryRun()) {
LOG_NOTICE("OK");
release();
return 0;
}
# ifndef XMRIG_NO_API
Api::start();
# endif
@@ -146,12 +153,7 @@ int App::exec()
const int r = uv_run(uv_default_loop(), UV_RUN_DEFAULT);
uv_loop_close(uv_default_loop());
delete m_network;
Options::release();
Mem::release();
Platform::release();
release();
return r;
}
@@ -200,6 +202,18 @@ void App::close()
}
void App::release()
{
if (m_network) {
delete m_network;
}
Options::release();
Mem::release();
Platform::release();
}
void App::onSignal(uv_signal_t *handle, int signum)
{
switch (signum)

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@@ -51,6 +51,7 @@ protected:
private:
void background();
void close();
void release();
static void onSignal(uv_signal_t *handle, int signum);

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@@ -100,7 +100,13 @@ void Cpu::initCommon()
m_l2_cache = data.l2_cache * (m_totalCores / 2) * m_sockets;
m_l2_exclusive = true;
}
else {
// Workaround for Intel Core Solo, Core Duo, Core 2 Duo, Core 2 Quad and their Xeon homologue
// These processors have L2 cache shared by 2 cores.
else if (data.vendor == VENDOR_INTEL && data.family == 0x06 && (data.model == 0x0E || data.model == 0x0F || data.model == 0x07)) {
int l2_count_per_socket = m_totalCores > 1 ? m_totalCores / 2 : 1;
m_l2_cache = data.l2_cache > 0 ? data.l2_cache * l2_count_per_socket * m_sockets : 0;
}
else{
m_l2_cache = data.l2_cache > 0 ? data.l2_cache * m_totalCores * m_sockets : 0;
}

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@@ -101,12 +101,16 @@ static char const short_options[] = "a:c:khBp:Px:r:R:s:t:T:o:u:O:v:Vl:S";
static struct option const options[] = {
{ "algo", 1, nullptr, 'a' },
{ "api-access-token", 1, nullptr, 4001 },
{ "api-port", 1, nullptr, 4000 },
{ "api-worker-id", 1, nullptr, 4002 },
{ "av", 1, nullptr, 'v' },
{ "background", 0, nullptr, 'B' },
{ "config", 1, nullptr, 'c' },
{ "cpu-affinity", 1, nullptr, 1020 },
{ "cpu-priority", 1, nullptr, 1021 },
{ "donate-level", 1, nullptr, 1003 },
{ "dry-run", 0, nullptr, 5000 },
{ "help", 0, nullptr, 'h' },
{ "keepalive", 0, nullptr ,'k' },
{ "log-file", 1, nullptr, 'l' },
@@ -126,9 +130,6 @@ static struct option const options[] = {
{ "user-agent", 1, nullptr, 1008 },
{ "userpass", 1, nullptr, 'O' },
{ "version", 0, nullptr, 'V' },
{ "api-port", 1, nullptr, 4000 },
{ "api-access-token", 1, nullptr, 4001 },
{ "api-worker-id", 1, nullptr, 4002 },
{ 0, 0, 0, 0 }
};
@@ -141,6 +142,7 @@ static struct option const config_options[] = {
{ "cpu-affinity", 1, nullptr, 1020 },
{ "cpu-priority", 1, nullptr, 1021 },
{ "donate-level", 1, nullptr, 1003 },
{ "dry-run", 0, nullptr, 5000 },
{ "huge-pages", 0, nullptr, 1009 },
{ "log-file", 1, nullptr, 'l' },
{ "max-cpu-usage", 1, nullptr, 1004 },
@@ -205,6 +207,7 @@ Options::Options(int argc, char **argv) :
m_background(false),
m_colors(true),
m_doubleHash(false),
m_dryRun(false),
m_hugePages(true),
m_ready(false),
m_safe(false),
@@ -384,6 +387,7 @@ bool Options::parseArg(int key, const char *arg)
case 'S': /* --syslog */
case 1005: /* --safe */
case 1006: /* --nicehash */
case 5000: /* --dry-run */
return parseBoolean(key, true);
case 1002: /* --no-color */
@@ -557,6 +561,10 @@ bool Options::parseBoolean(int key, bool enable)
m_colors = enable;
break;
case 5000: /* --dry-run */
m_dryRun = enable;
break;
default:
break;
}

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@@ -59,6 +59,7 @@ public:
inline bool background() const { return m_background; }
inline bool colors() const { return m_colors; }
inline bool doubleHash() const { return m_doubleHash; }
inline bool dryRun() const { return m_dryRun; }
inline bool hugePages() const { return m_hugePages; }
inline bool syslog() const { return m_syslog; }
inline const char *apiToken() const { return m_apiToken; }
@@ -110,6 +111,7 @@ private:
bool m_background;
bool m_colors;
bool m_doubleHash;
bool m_dryRun;
bool m_hugePages;
bool m_ready;
bool m_safe;

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@@ -46,7 +46,7 @@ NetworkState::NetworkState() :
int NetworkState::connectionTime() const
{
return m_active ? ((uv_now(uv_default_loop()) - m_connectionTime) / 1000) : 0;
return m_active ? (int)((uv_now(uv_default_loop()) - m_connectionTime) / 1000) : 0;
}
@@ -56,7 +56,7 @@ uint32_t NetworkState::avgTime() const
return 0;
}
return (uint32_t) connectionTime() / m_latency.size();
return connectionTime() / (uint32_t)m_latency.size();
}

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@@ -194,14 +194,14 @@ template<bool SOFT_AES>
static inline void aes_round(__m128i key, __m128i* x0, __m128i* x1, __m128i* x2, __m128i* x3, __m128i* x4, __m128i* x5, __m128i* x6, __m128i* x7)
{
if (SOFT_AES) {
*x0 = soft_aesenc(*x0, key);
*x1 = soft_aesenc(*x1, key);
*x2 = soft_aesenc(*x2, key);
*x3 = soft_aesenc(*x3, key);
*x4 = soft_aesenc(*x4, key);
*x5 = soft_aesenc(*x5, key);
*x6 = soft_aesenc(*x6, key);
*x7 = soft_aesenc(*x7, key);
*x0 = soft_aesenc((uint32_t*)x0, key);
*x1 = soft_aesenc((uint32_t*)x1, key);
*x2 = soft_aesenc((uint32_t*)x2, key);
*x3 = soft_aesenc((uint32_t*)x3, key);
*x4 = soft_aesenc((uint32_t*)x4, key);
*x5 = soft_aesenc((uint32_t*)x5, key);
*x6 = soft_aesenc((uint32_t*)x6, key);
*x7 = soft_aesenc((uint32_t*)x7, key);
}
# ifndef XMRIG_ARMv7
else {
@@ -361,12 +361,13 @@ inline void cryptonight_hash(const void *__restrict__ input, size_t size, void *
uint64_t idx0 = h0[0] ^ h0[4];
for (size_t i = 0; i < ITERATIONS; i++) {
__m128i cx = _mm_load_si128((__m128i *) &l0[idx0 & MASK]);
__m128i cx;
if (SOFT_AES) {
cx = soft_aesenc(cx, _mm_set_epi64x(ah0, al0));
cx = soft_aesenc((uint32_t*)&l0[idx0 & MASK], _mm_set_epi64x(ah0, al0));
}
else {
cx = _mm_load_si128((__m128i *) &l0[idx0 & MASK]);
# ifndef XMRIG_ARMv7
cx = vreinterpretq_m128i_u8(vaesmcq_u8(vaeseq_u8(cx, vdupq_n_u8(0)))) ^ _mm_set_epi64x(ah0, al0);
# endif
@@ -425,14 +426,15 @@ inline void cryptonight_double_hash(const void *__restrict__ input, size_t size,
uint64_t idx1 = h1[0] ^ h1[4];
for (size_t i = 0; i < ITERATIONS; i++) {
__m128i cx0 = _mm_load_si128((__m128i *) &l0[idx0 & MASK]);
__m128i cx1 = _mm_load_si128((__m128i *) &l1[idx1 & MASK]);
__m128i cx0, cx1;
if (SOFT_AES) {
cx0 = soft_aesenc(cx0, _mm_set_epi64x(ah0, al0));
cx1 = soft_aesenc(cx1, _mm_set_epi64x(ah1, al1));
cx0 = soft_aesenc((uint32_t*)&l0[idx0 & MASK], _mm_set_epi64x(ah0, al0));
cx1 = soft_aesenc((uint32_t*)&l1[idx1 & MASK], _mm_set_epi64x(ah1, al1));
}
else {
cx0 = _mm_load_si128((__m128i *) &l0[idx0 & MASK]);
cx1 = _mm_load_si128((__m128i *) &l1[idx1 & MASK]);
# ifndef XMRIG_ARMv7
cx0 = vreinterpretq_m128i_u8(vaesmcq_u8(vaeseq_u8(cx0, vdupq_n_u8(0)))) ^ _mm_set_epi64x(ah0, al0);
cx1 = vreinterpretq_m128i_u8(vaesmcq_u8(vaeseq_u8(cx1, vdupq_n_u8(0)))) ^ _mm_set_epi64x(ah1, al1);

View File

@@ -193,14 +193,14 @@ template<bool SOFT_AES>
static inline void aes_round(__m128i key, __m128i* x0, __m128i* x1, __m128i* x2, __m128i* x3, __m128i* x4, __m128i* x5, __m128i* x6, __m128i* x7)
{
if (SOFT_AES) {
*x0 = soft_aesenc(*x0, key);
*x1 = soft_aesenc(*x1, key);
*x2 = soft_aesenc(*x2, key);
*x3 = soft_aesenc(*x3, key);
*x4 = soft_aesenc(*x4, key);
*x5 = soft_aesenc(*x5, key);
*x6 = soft_aesenc(*x6, key);
*x7 = soft_aesenc(*x7, key);
*x0 = soft_aesenc((uint32_t*)x0, key);
*x1 = soft_aesenc((uint32_t*)x1, key);
*x2 = soft_aesenc((uint32_t*)x2, key);
*x3 = soft_aesenc((uint32_t*)x3, key);
*x4 = soft_aesenc((uint32_t*)x4, key);
*x5 = soft_aesenc((uint32_t*)x5, key);
*x6 = soft_aesenc((uint32_t*)x6, key);
*x7 = soft_aesenc((uint32_t*)x7, key);
}
else {
*x0 = _mm_aesenc_si128(*x0, key);
@@ -325,15 +325,14 @@ inline void cryptonight_hash(const void *__restrict__ input, size_t size, void *
for (size_t i = 0; i < ITERATIONS; i++) {
__m128i cx;
cx = _mm_load_si128((__m128i *) &l0[idx0 & MASK]);
if (SOFT_AES) {
cx = soft_aesenc(cx, _mm_set_epi64x(ah0, al0));
cx = soft_aesenc((uint32_t*)&l0[idx0 & MASK], _mm_set_epi64x(ah0, al0));
}
else {
else {
cx = _mm_load_si128((__m128i *) &l0[idx0 & MASK]);
cx = _mm_aesenc_si128(cx, _mm_set_epi64x(ah0, al0));
}
_mm_store_si128((__m128i *) &l0[idx0 & MASK], _mm_xor_si128(bx0, cx));
idx0 = EXTRACT64(cx);
bx0 = cx;
@@ -387,14 +386,15 @@ inline void cryptonight_double_hash(const void *__restrict__ input, size_t size,
uint64_t idx1 = h1[0] ^ h1[4];
for (size_t i = 0; i < ITERATIONS; i++) {
__m128i cx0 = _mm_load_si128((__m128i *) &l0[idx0 & MASK]);
__m128i cx1 = _mm_load_si128((__m128i *) &l1[idx1 & MASK]);
__m128i cx0, cx1;
if (SOFT_AES) {
cx0 = soft_aesenc(cx0, _mm_set_epi64x(ah0, al0));
cx1 = soft_aesenc(cx1, _mm_set_epi64x(ah1, al1));
cx0 = soft_aesenc((uint32_t*)&l0[idx0 & MASK], _mm_set_epi64x(ah0, al0));
cx1 = soft_aesenc((uint32_t*)&l1[idx1 & MASK], _mm_set_epi64x(ah1, al1));
}
else {
cx0 = _mm_load_si128((__m128i *) &l0[idx0 & MASK]);
cx1 = _mm_load_si128((__m128i *) &l1[idx1 & MASK]);
cx0 = _mm_aesenc_si128(cx0, _mm_set_epi64x(ah0, al0));
cx1 = _mm_aesenc_si128(cx1, _mm_set_epi64x(ah1, al1));
}

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@@ -89,34 +89,34 @@
alignas(16) const uint32_t saes_table[4][256] = { saes_data(saes_u0), saes_data(saes_u1), saes_data(saes_u2), saes_data(saes_u3) };
alignas(16) const uint8_t saes_sbox[256] = saes_data(saes_h0);
static inline __m128i soft_aesenc(__m128i in, __m128i key)
static inline __m128i soft_aesenc(const uint32_t* in, __m128i key)
{
const uint32_t x0 = _mm_cvtsi128_si32(in);
const uint32_t x1 = _mm_cvtsi128_si32(_mm_shuffle_epi32(in, 0x55));
const uint32_t x2 = _mm_cvtsi128_si32(_mm_shuffle_epi32(in, 0xAA));
const uint32_t x3 = _mm_cvtsi128_si32(_mm_shuffle_epi32(in, 0xFF));
const uint32_t x0 = in[0];
const uint32_t x1 = in[1];
const uint32_t x2 = in[2];
const uint32_t x3 = in[3];
__m128i out = _mm_set_epi32(
(saes_table[0][x3 & 0xff] ^ saes_table[1][(x0 >> 8) & 0xff] ^ saes_table[2][(x1 >> 16) & 0xff] ^ saes_table[3][x2 >> 24]),
(saes_table[0][x2 & 0xff] ^ saes_table[1][(x3 >> 8) & 0xff] ^ saes_table[2][(x0 >> 16) & 0xff] ^ saes_table[3][x1 >> 24]),
(saes_table[0][x1 & 0xff] ^ saes_table[1][(x2 >> 8) & 0xff] ^ saes_table[2][(x3 >> 16) & 0xff] ^ saes_table[3][x0 >> 24]),
(saes_table[0][x0 & 0xff] ^ saes_table[1][(x1 >> 8) & 0xff] ^ saes_table[2][(x2 >> 16) & 0xff] ^ saes_table[3][x3 >> 24]));
__m128i out = _mm_set_epi32(
(saes_table[0][x3 & 0xff] ^ saes_table[1][(x0 >> 8) & 0xff] ^ saes_table[2][(x1 >> 16) & 0xff] ^ saes_table[3][x2 >> 24]),
(saes_table[0][x2 & 0xff] ^ saes_table[1][(x3 >> 8) & 0xff] ^ saes_table[2][(x0 >> 16) & 0xff] ^ saes_table[3][x1 >> 24]),
(saes_table[0][x1 & 0xff] ^ saes_table[1][(x2 >> 8) & 0xff] ^ saes_table[2][(x3 >> 16) & 0xff] ^ saes_table[3][x0 >> 24]),
(saes_table[0][x0 & 0xff] ^ saes_table[1][(x1 >> 8) & 0xff] ^ saes_table[2][(x2 >> 16) & 0xff] ^ saes_table[3][x3 >> 24]));
return _mm_xor_si128(out, key);
return _mm_xor_si128(out, key);
}
static inline uint32_t sub_word(uint32_t key)
{
return (saes_sbox[key >> 24 ] << 24) |
(saes_sbox[(key >> 16) & 0xff] << 16 ) |
(saes_sbox[(key >> 8) & 0xff] << 8 ) |
saes_sbox[key & 0xff];
return (saes_sbox[key >> 24 ] << 24) |
(saes_sbox[(key >> 16) & 0xff] << 16 ) |
(saes_sbox[(key >> 8) & 0xff] << 8 ) |
saes_sbox[key & 0xff];
}
#if defined(__clang__) || defined(XMRIG_ARM)
static inline uint32_t _rotr(uint32_t value, uint32_t amount)
{
return (value >> amount) | (value << ((32 - amount) & 31));
return (value >> amount) | (value << ((32 - amount) & 31));
}
#endif

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@@ -532,7 +532,7 @@ void Client::onAllocBuffer(uv_handle_t *handle, size_t suggested_size, uv_buf_t
auto client = getClient(handle->data);
buf->base = &client->m_recvBuf.base[client->m_recvBufPos];
buf->len = client->m_recvBuf.len - client->m_recvBufPos;
buf->len = client->m_recvBuf.len - (unsigned long)client->m_recvBufPos;
}

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@@ -27,7 +27,7 @@
#define APP_ID "xmrig"
#define APP_NAME "XMRig"
#define APP_DESC "XMRig CPU miner"
#define APP_VERSION "2.4.4"
#define APP_VERSION "2.4.5"
#define APP_DOMAIN "xmrig.com"
#define APP_SITE "www.xmrig.com"
#define APP_COPYRIGHT "Copyright (C) 2016-2018 xmrig.com"
@@ -35,7 +35,7 @@
#define APP_VER_MAJOR 2
#define APP_VER_MINOR 4
#define APP_VER_BUILD 4
#define APP_VER_BUILD 5
#define APP_VER_REV 0
#ifdef _MSC_VER