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7 Commits

Author SHA1 Message Date
XMRig
6bf43053f7 v6.26.1-dev 2026-03-28 20:43:46 +07:00
XMRig
69b7e60d35 Merge branch 'master' into dev 2026-03-28 20:42:02 +07:00
XMRig
b2ca72480c v6.26.0 2026-03-28 20:04:06 +07:00
XMRig
92705f2dae Merge branch 'dev' 2026-03-28 20:02:42 +07:00
XMRig
4f58a7afff v6.26.0-dev 2026-03-25 23:58:45 +07:00
xmrig
806cfc3f4d Merge pull request #3790 from SChernykh/dev
Fix arm64 builds (attempt number 2)
2026-03-03 18:27:10 +07:00
SChernykh
84352c71ca Fix arm64 builds (attempt number 2) 2026-03-03 12:19:28 +01:00
3 changed files with 20 additions and 6 deletions

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@@ -1,3 +1,17 @@
# v6.26.0
- [#3769](https://github.com/xmrig/xmrig/pull/3769), [#3772](https://github.com/xmrig/xmrig/pull/3772), [#3774](https://github.com/xmrig/xmrig/pull/3774), [#3775](https://github.com/xmrig/xmrig/pull/3775), [#3776](https://github.com/xmrig/xmrig/pull/3776), [#3782](https://github.com/xmrig/xmrig/pull/3782), [#3783](https://github.com/xmrig/xmrig/pull/3783) **Added support for RandomX v2.**
- [#3746](https://github.com/xmrig/xmrig/pull/3746) RISC-V: vectorized RandomX main loop.
- [#3748](https://github.com/xmrig/xmrig/pull/3748) RISC-V: auto-detect and use vector code for all RandomX AES functions.
- [#3749](https://github.com/xmrig/xmrig/pull/3749) RISC-V: detect and use hardware AES.
- [#3750](https://github.com/xmrig/xmrig/pull/3750) RISC-V: use vector hardware AES instead of scalar.
- [#3757](https://github.com/xmrig/xmrig/pull/3757) RISC-V: Fixed scratchpad prefetch, removed an unnecessary instruction.
- [#3758](https://github.com/xmrig/xmrig/pull/3758) RandomX: added VAES-512 support for Zen5.
- [#3759](https://github.com/xmrig/xmrig/pull/3759) RandomX: Optimized VAES code.
- [#3762](https://github.com/xmrig/xmrig/pull/3762) Fixed keepalive timer logic.
- [#3778](https://github.com/xmrig/xmrig/pull/3778) RandomX: ARM64 fixes.
- [#3784](https://github.com/xmrig/xmrig/pull/3784) Fixed OpenCL address-space mismatch in `keccak_f800_round`.
- [#3785](https://github.com/xmrig/xmrig/pull/3785) Don't reset nonce during donation rounds.
# v6.25.0
- [#3680](https://github.com/xmrig/xmrig/pull/3680) Added `armv8l` to the list of 32-bit ARM targets.
- [#3708](https://github.com/xmrig/xmrig/pull/3708) Minor Aarch64 JIT changes (better instruction selection, don't emit instructions that add 0, etc).

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@@ -420,7 +420,7 @@ inline void* rx_aligned_alloc(size_t size, size_t align) {
# define rx_aligned_free(a) free(a)
#endif
inline void rx_prefetch_nta(void* ptr) {
inline void rx_prefetch_nta(const void* ptr) {
asm volatile ("prfm pldl1strm, [%0]\n" : : "r" (ptr));
}

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@@ -1,6 +1,6 @@
/* XMRig
* Copyright (c) 2018-2025 SChernykh <https://github.com/SChernykh>
* Copyright (c) 2016-2025 XMRig <https://github.com/xmrig>, <support@xmrig.com>
* Copyright (c) 2018-2026 SChernykh <https://github.com/SChernykh>
* Copyright (c) 2016-2026 XMRig <https://github.com/xmrig>, <support@xmrig.com>
*
* SPDX-License-Identifier: GPL-3.0-or-later
*/
@@ -11,14 +11,14 @@
#define APP_ID "xmrig"
#define APP_NAME "XMRig"
#define APP_DESC "XMRig miner"
#define APP_VERSION "6.25.1-dev"
#define APP_VERSION "6.26.1-dev"
#define APP_DOMAIN "xmrig.com"
#define APP_SITE "www.xmrig.com"
#define APP_COPYRIGHT "Copyright (C) 2016-2025 xmrig.com"
#define APP_COPYRIGHT "Copyright (C) 2016-2026 xmrig.com"
#define APP_KIND "miner"
#define APP_VER_MAJOR 6
#define APP_VER_MINOR 25
#define APP_VER_MINOR 26
#define APP_VER_PATCH 1
#ifdef _MSC_VER