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Author SHA1 Message Date
XMRig
5feb764b27 Merge branch 'fix-keepalive-timer' of https://github.com/HashVault/vltrig into pr3762 2026-01-21 21:21:48 +07:00
rezky_nightky
cb7511507f fix: cross typos detail below: 
What I did
Repository rules / exclusions
I didn’t find repo-specific spelling tooling already in place (no existing codespell config).
Given this is a C/C++ repo with vendored sources, I treated src/3rdparty/** as third-party and excluded it from typo fixing (and encoded that in the new .codespellrc).
Typos fixed (first-party only)
Docs
CHANGELOG.md: perfomance -> performance
doc/API.md: optionaly -> optionally, Offical -> Official
doc/BENCHMARK.md: parameteres -> parameters
doc/CPU.md: loosing -> losing, instuctions -> instructions
doc/CHANGELOG_OLD.md: multiple obvious text typos like Breaked -> Broken, singal -> signal, previos -> previous, secons -> seconds, automaticaly -> automatically, perfomance -> performance
Code comments / doc comments (safe text-only changes)
src/base/crypto/sha3.cpp: Inteface -> Interface (comment banner)
src/backend/opencl/cl/cn/cryptonight.cl: performe -> perform, crashs -> crashes (comments)
src/backend/opencl/cl/kawpow/kawpow.cl: regsters -> registers, intial -> initial (comments)
src/crypto/randomx/aes_hash.cpp: intial -> initial (comment)
src/crypto/randomx/intrin_portable.h: cant -> can't (comment)
src/crypto/randomx/randomx.h: intialization -> initialization (doc comment)
src/crypto/cn/c_jh.c: intital -> initial (comment)
src/crypto/cn/skein_port.h: varaiable -> variable (comment)
src/backend/opencl/cl/cn/wolf-skein.cl: Build-in -> Built-in (comment)
What I intentionally did NOT change
Anything under src/3rdparty/** (vendored).
A few remaining codespell hits are either:
Upstream/embedded sources we excluded (groestl256.cl, jh.cl contain Projet)
Potentially valid identifier/name (Carmel CPU codename)
Low-risk token in codegen comments (vor inside an instruction comment)
These are handled via ignore rules in .codespellrc instead of modifying code.

Added: .codespellrc
Created /.codespellrc with:

skip entries for vendored / embedded upstream areas:
./src/3rdparty
./src/crypto/ghostrider
./src/crypto/randomx/blake2
./src/crypto/cn/sse2neon.h
./src/backend/opencl/cl/cn/groestl256.cl
./src/backend/opencl/cl/cn/jh.cl
ignore-words-list for:
Carmel
vor
Verification
codespell . --config ./.codespellrc now exits clean (exit code 0).

Signed-off-by: rezky_nightky <with.rezky@gmail.com>
 2026-01-21 20:14:59 +07:00
HashVault
6e6eab1763 Fix keepalive timer logic 
- Reset timer on send instead of receive (pool needs to know we're alive)
- Remove timer disable after first ping to enable continuous keepalives
 2026-01-20 14:39:06 +03:00
xmrig
f35f9d7241 Merge pull request #3759 from SChernykh/dev 
Optimized VAES code
 2026-01-17 21:55:01 +07:00
SChernykh
45d0a15c98 Optimized VAES code 
Use only 1 mask instead of 2
 2026-01-16 20:43:35 +01:00
xmrig
f4845cbd68 Merge pull request #3758 from SChernykh/dev 
RandomX: added VAES-512 support for Zen5
 2026-01-16 19:07:09 +07:00
SChernykh
ed80a8a828 RandomX: added VAES-512 support for Zen5 
+0.1-0.2% hashrate improvement.
 2026-01-16 13:04:40 +01:00
xmrig
9e5492eecc Merge pull request #3757 from SChernykh/dev 
Improved RISC-V code
 2026-01-15 19:51:57 +07:00
SChernykh
e41b28ef78 Improved RISC-V code 2026-01-15 12:48:55 +01:00
xmrig
1bd59129c4 Merge pull request #3750 from SChernykh/dev 
RISC-V: use vector hardware AES instead of scalar
 2026-01-01 15:43:36 +07:00
SChernykh
8ccf7de304 RISC-V: use vector hardware AES instead of scalar 2025-12-31 23:37:55 +01:00
xmrig
30ffb9cb27 Merge pull request #3749 from SChernykh/dev 
RISC-V: detect and use hardware AES
 2025-12-30 14:13:44 +07:00
SChernykh
d3a84c4b52 RISC-V: detect and use hardware AES 2025-12-29 22:10:07 +01:00
xmrig
eb49237aaa Merge pull request #3748 from SChernykh/dev 
RISC-V: auto-detect and use vector code for all RandomX AES functions
 2025-12-28 13:12:50 +07:00
SChernykh
e1efd3dc7f RISC-V: auto-detect and use vector code for all RandomX AES functions 2025-12-27 21:30:14 +01:00
xmrig
e3d0135708 Merge pull request #3746 from SChernykh/dev 
RISC-V: vectorized RandomX main loop
 2025-12-27 18:40:47 +07:00
SChernykh
f661e1eb30 RISC-V: vectorized RandomX main loop 2025-12-26 22:11:39 +01:00
XMRig
99488751f1 v6.25.1-dev 2025-12-23 20:53:43 +07:00
XMRig
5fb0321c84 Merge branch 'master' into dev 2025-12-23 20:53:11 +07:00
XMRig
753859caea v6.25.0 v6.25.0 2025-12-23 19:44:52 +07:00
XMRig
712a5a5e66 Merge branch 'dev' 2025-12-23 19:44:21 +07:00
XMRig
290a0de6e5 v6.25.0-dev 2025-12-23 19:37:24 +07:00
xmrig
e0564b5fdd Merge pull request #3743 from SChernykh/dev 
Linux: added support for transparent huge pages
 2025-12-12 01:20:03 +07:00
SChernykh
482a1f0b40 Linux: added support for transparent huge pages 2025-12-11 11:23:18 +01:00
xmrig
856813c1ae Merge pull request #3740 from SChernykh/dev 
RISC-V: added vectorized soft AES
 2025-12-06 19:39:47 +07:00
SChernykh
23da1a90f5 RISC-V: added vectorized soft AES 2025-12-05 21:09:22 +01:00
xmrig
7981e4a76a Merge pull request #3736 from SChernykh/dev 
RISC-V: added vectorized dataset init
 2025-12-01 10:46:03 +07:00
SChernykh
7ef5142a52 RISC-V: added vectorized dataset init (activated by setting init-avx2 to 1 in config.json) 2025-11-30 19:15:15 +01:00
xmrig
db5c6d9190 Merge pull request #3733 from void-512/master 
Add detection for MSVC/2026
 2025-11-13 15:52:43 +07:00
Tony Wang
e88009d575 add detection for MSVC/2026 2025-11-12 17:32:57 -05:00
XMRig
5115597e7f Improved compatibility for automatically enabling huge pages on Linux systems without NUMA support. 2025-11-07 01:55:00 +07:00
xmrig
4cdc35f966 Merge pull request #3731 from user0-07161/dev-haiku-os-support 
feat: initial haiku os support
 2025-11-05 18:47:22 +07:00
user0-07161
b02519b9f5 feat: initial support for haiku 2025-11-04 13:58:01 +00:00
XMRig
a44b21cef3 Cleanup 2025-10-27 19:18:52 +07:00
XMRig
ea832899f2 Fixed macOS build. 2025-10-23 11:17:59 +07:00
xmrig
3ecacf0ac2 Merge pull request #3725 from SChernykh/dev 
RISC-V integration and JIT compiler
 2025-10-23 11:02:21 +07:00
SChernykh
27c8e60919 Removed unused files 2025-10-22 23:31:02 +02:00
SChernykh
985fe06e8d RISC-V: test for instruction extensions 2025-10-22 19:21:26 +02:00
SChernykh
75b63ddde9 RISC-V JIT compiler 2025-10-22 19:00:20 +02:00
slayingripper
643b65f2c0 RISC-V Intergration 2025-10-22 18:57:20 +02:00
xmrig
116ba1828f Merge pull request #3722 from SChernykh/dev 
Added Zen4 (Hawk Point) CPUs detection
 2025-10-15 13:23:36 +07:00
SChernykh
da5a5674b4 Added Zen4 (Hawk Point) CPUs detection 2025-10-15 08:07:58 +02:00
xmrig
6cc4819cec Merge pull request #3719 from SChernykh/dev 
Fix: correct FCMP++ version number
 2025-10-05 18:28:21 +07:00
SChernykh
a659397c41 Fix: correct FCMP++ version number 2025-10-05 13:24:55 +02:00
xmrig
20acfd0d79 Merge pull request #3718 from SChernykh/dev 
Solo mining: added support for FCMP++ hardfork
 2025-10-05 18:04:23 +07:00
SChernykh
da683d8c3e Solo mining: added support for FCMP++ hardfork 2025-10-05 13:00:21 +02:00
XMRig
255565b533 Merge branch 'xtophyr-master' into dev 2025-09-22 21:31:28 +07:00
XMRig
878e83bf59 Merge branch 'master' of https://github.com/xtophyr/xmrig into xtophyr-master 2025-09-22 21:31:14 +07:00
Christopher Wright
7abf17cb59 adjust instruction/register suffixes to compile with gcc-based assemblers. 2025-09-21 14:57:42 -04:00
Christopher Wright
eeec5ecd10 undo this change 2025-09-20 08:38:40 -04:00