5 Commits

Author	SHA1	Message	Date
SChernykh	906fd4693b	ISUB_R fix for ARM/RISC-V JIT	2026-06-27 13:22:48 +02:00
SChernykh	d82d7f3f20	RandomX v2 (RISC-V)	2026-01-31 21:50:38 +01:00
SChernykh	f661e1eb30	RISC-V: vectorized RandomX main loop	2025-12-26 22:11:39 +01:00
SChernykh	7ef5142a52	RISC-V: added vectorized dataset init (activated by setting init-avx2 to 1 in config.json)	2025-11-30 19:15:15 +01:00
SChernykh	75b63ddde9	RISC-V JIT compiler	2025-10-22 19:00:20 +02:00