mirror of
https://github.com/xmrig/xmrig.git
synced 2025-12-07 07:55:04 -05:00
Removed unused files
This commit is contained in:
SChernykh
@@ -1,186 +0,0 @@
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/* XMRig
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* Copyright (c) 2025 XMRig <https://github.com/xmrig>, <support@xmrig.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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||||||
*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* RISC-V Crypto Extensions (Zbk*) Support
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*
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* Supports detection and usage of RISC-V crypto extensions:
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* - Zkn: NIST approved cryptographic extensions (AES, SHA2, SHA3)
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* - Zknd/Zkne: AES decryption/encryption
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* - Zknh: SHA2/SHA3 hash extensions
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* - Zkb: Bit manipulation extensions (Zba, Zbb, Zbc, Zbs)
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*
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* Falls back gracefully to software implementations on systems without support.
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*/
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#ifndef XMRIG_RISCV_CRYPTO_H
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#define XMRIG_RISCV_CRYPTO_H
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#include <stdint.h>
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#include <stdbool.h>
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#include <string.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(XMRIG_RISCV)
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/* Check if RISC-V crypto extensions are available at compile time */
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#if defined(__riscv_zkne) || defined(__riscv_zknd)
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#define HAVE_RISCV_AES 1
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#else
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#define HAVE_RISCV_AES 0
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#endif
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#if defined(__riscv_zknh)
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#define HAVE_RISCV_SHA 1
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#else
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#define HAVE_RISCV_SHA 0
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#endif
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#if defined(__riscv_zba) && defined(__riscv_zbb) && defined(__riscv_zbc)
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#define HAVE_RISCV_BIT_MANIP 1
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#else
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#define HAVE_RISCV_BIT_MANIP 0
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#endif
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/* Detect CPU support at runtime via /proc/cpuinfo */
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extern bool riscv_cpu_has_aes_support(void);
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extern bool riscv_cpu_has_sha_support(void);
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extern bool riscv_cpu_has_bitmanip_support(void);
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/* Software fallback AES utilities optimized for RISC-V */
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/* AES S-box lookup - cache-friendly implementation */
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typedef struct {
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uint32_t sbox_enc[256];
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uint32_t sbox_dec[256];
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} riscv_aes_sbox_t;
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extern const riscv_aes_sbox_t riscv_aes_tables;
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/* Software AES encryption round optimized for RISC-V */
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static inline uint32_t riscv_aes_enc_round(uint32_t input, const uint32_t *round_key)
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{
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uint32_t result = 0;
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/* Unroll byte-by-byte lookups for better instruction-level parallelism */
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uint32_t b0 = (input >> 0) & 0xFF;
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uint32_t b1 = (input >> 8) & 0xFF;
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uint32_t b2 = (input >> 16) & 0xFF;
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uint32_t b3 = (input >> 24) & 0xFF;
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result = riscv_aes_tables.sbox_enc[b0] ^
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riscv_aes_tables.sbox_enc[b1] ^
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riscv_aes_tables.sbox_enc[b2] ^
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riscv_aes_tables.sbox_enc[b3];
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return result ^ (*round_key);
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}
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/* Bit rotation optimized for RISC-V */
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static inline uint32_t riscv_rotr32(uint32_t x, int r)
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{
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#if defined(__riscv_zbb)
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/* Use RISC-V bit rotation if available */
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uint32_t result;
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asm volatile ("ror %0, %1, %2" : "=r"(result) : "r"(x), "r"(r) : );
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return result;
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#else
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/* Scalar fallback */
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return (x >> r) | (x << (32 - r));
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#endif
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}
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static inline uint64_t riscv_rotr64(uint64_t x, int r)
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{
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#if defined(__riscv_zbb)
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/* Use RISC-V bit rotation if available */
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uint64_t result;
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asm volatile ("ror %0, %1, %2" : "=r"(result) : "r"(x), "r"(r) : );
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return result;
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#else
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/* Scalar fallback */
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return (x >> r) | (x << (64 - r));
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#endif
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}
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/* Bit count operations optimized for RISC-V */
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static inline int riscv_popcount(uint64_t x)
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{
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#if defined(__riscv_zbb)
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/* Use hardware popcount if available */
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int result;
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asm volatile ("cpop %0, %1" : "=r"(result) : "r"(x) : );
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return result;
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#else
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/* Scalar fallback */
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return __builtin_popcountll(x);
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#endif
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}
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static inline int riscv_ctz(uint64_t x)
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{
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#if defined(__riscv_zbb)
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/* Use hardware count trailing zeros if available */
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int result;
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asm volatile ("ctz %0, %1" : "=r"(result) : "r"(x) : );
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return result;
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#else
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/* Scalar fallback */
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return __builtin_ctzll(x);
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#endif
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}
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/* Bit manipulation operations from Zba */
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static inline uint64_t riscv_add_uw(uint64_t a, uint64_t b)
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{
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#if defined(__riscv_zba)
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/* Add unsigned word (add.uw) - zero extends 32-bit addition */
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uint64_t result;
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asm volatile ("add.uw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b) : );
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return result;
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#else
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return ((a & 0xFFFFFFFF) + (b & 0xFFFFFFFF)) & 0xFFFFFFFF;
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#endif
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}
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#else /* !XMRIG_RISCV */
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/* Non-RISC-V fallbacks */
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#define HAVE_RISCV_AES 0
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#define HAVE_RISCV_SHA 0
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#define HAVE_RISCV_BIT_MANIP 0
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static inline bool riscv_cpu_has_aes_support(void) { return false; }
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static inline bool riscv_cpu_has_sha_support(void) { return false; }
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static inline bool riscv_cpu_has_bitmanip_support(void) { return false; }
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static inline uint32_t riscv_rotr32(uint32_t x, int r) { return (x >> r) | (x << (32 - r)); }
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static inline uint64_t riscv_rotr64(uint64_t x, int r) { return (x >> r) | (x << (64 - r)); }
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static inline int riscv_popcount(uint64_t x) { return __builtin_popcountll(x); }
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static inline int riscv_ctz(uint64_t x) { return __builtin_ctzll(x); }
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static inline uint64_t riscv_add_uw(uint64_t a, uint64_t b) { return (a & 0xFFFFFFFF) + (b & 0xFFFFFFFF); }
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif // XMRIG_RISCV_CRYPTO_H
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@@ -1,283 +0,0 @@
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/* XMRig
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* Copyright (c) 2025 XMRig <https://github.com/xmrig>, <support@xmrig.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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||||||
* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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||||||
* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* RISC-V optimized memory operations
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*
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* Provides efficient:
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* - Memory barriers
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* - Cache line operations
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* - Prefetching hints
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* - Aligned memory access
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* - Memory pooling utilities
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*/
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#ifndef XMRIG_RISCV_MEMORY_H
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#define XMRIG_RISCV_MEMORY_H
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#include <stdint.h>
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#include <stddef.h>
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#include <string.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(XMRIG_RISCV)
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#define CACHELINE_SIZE 64
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#define CACHELINE_MASK (~(CACHELINE_SIZE - 1))
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/* Memory barriers - optimized for RISC-V */
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/* Full memory barrier: all reads and writes before must complete before any after */
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static inline void riscv_mfence(void)
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{
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asm volatile ("fence rw,rw" : : : "memory");
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}
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/* Load barrier: all loads before must complete before any after */
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static inline void riscv_lfence(void)
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{
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asm volatile ("fence r,r" : : : "memory");
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}
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/* Store barrier: all stores before must complete before any after */
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static inline void riscv_sfence(void)
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{
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asm volatile ("fence w,w" : : : "memory");
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}
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/* TSO (total store order) - ensures store-release semantics */
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static inline void riscv_fence_tso(void)
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{
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asm volatile ("fence rw,w" : : : "memory");
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}
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/* Acquire barrier - for lock acquisition */
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static inline void riscv_acquire_fence(void)
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{
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asm volatile ("fence r,rw" : : : "memory");
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}
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/* Release barrier - for lock release */
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static inline void riscv_release_fence(void)
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{
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asm volatile ("fence rw,w" : : : "memory");
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}
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/* CPU pause hint (Zihintpause extension, falls back to NOP) */
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static inline void riscv_pause(void)
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{
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asm volatile ("pause");
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}
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/* Prefetch operations - hints to load into L1 cache */
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/* Prefetch for read (temporal locality) */
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static inline void riscv_prefetch_read(const void *addr)
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{
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/* Temporary workaround: use inline asm */
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asm volatile ("# prefetch %0 \n" : : "m"(*(const char *)addr));
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}
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/* Prefetch for write (prepare for store) */
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static inline void riscv_prefetch_write(const void *addr)
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{
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asm volatile ("# prefetch.w %0 \n" : : "m"(*(const char *)addr));
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}
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/* Prefetch with 0 temporal locality (load into L1 but not higher levels) */
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static inline void riscv_prefetch_nta(const void *addr)
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{
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asm volatile ("# prefetch.nta %0 \n" : : "m"(*(const char *)addr));
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}
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/* Cache line flush (if supported) */
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static inline void riscv_clflush(const void *addr)
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{
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/* RISC-V may not have cache flush in userspace */
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/* This is a no-op unless running in privileged mode */
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(void)addr;
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}
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/* Optimized memory copy with cache prefetching */
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static inline void riscv_memcpy_prefetch(void *dest, const void *src, size_t size)
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{
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uint8_t *d = (uint8_t *)dest;
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|
||||||
const uint8_t *s = (const uint8_t *)src;
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||||||
|
|
||||||
/* Process in cache line sized chunks with prefetching */
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||||||
size_t cache_lines = size / CACHELINE_SIZE;
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|
||||||
for (size_t i = 0; i < cache_lines; ++i) {
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|
||||||
/* Prefetch next cache lines ahead */
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||||||
if (i + 4 < cache_lines) {
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||||||
riscv_prefetch_read(s + (i + 4) * CACHELINE_SIZE);
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||||||
}
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||||||
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||||||
/* Copy current cache line - use 64-bit accesses for efficiency */
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|
||||||
const uint64_t *src64 = (const uint64_t *)(s + i * CACHELINE_SIZE);
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||||||
uint64_t *dest64 = (uint64_t *)(d + i * CACHELINE_SIZE);
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|
||||||
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|
||||||
for (int j = 0; j < 8; ++j) { /* 8 * 8 bytes = 64 bytes */
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|
||||||
dest64[j] = src64[j];
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|
||||||
}
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|
||||||
}
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|
||||||
|
|
||||||
/* Handle remainder */
|
|
||||||
size_t remainder = size % CACHELINE_SIZE;
|
|
||||||
if (remainder > 0) {
|
|
||||||
memcpy(d + cache_lines * CACHELINE_SIZE,
|
|
||||||
s + cache_lines * CACHELINE_SIZE,
|
|
||||||
remainder);
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|
||||||
}
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|
||||||
}
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|
||||||
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|
||||||
/* Optimized memory fill with pattern */
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|
||||||
static inline void riscv_memfill64(void *dest, uint64_t value, size_t count)
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|
||||||
{
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||||||
uint64_t *d = (uint64_t *)dest;
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|
||||||
|
|
||||||
/* Unroll loop for better ILP */
|
|
||||||
size_t i = 0;
|
|
||||||
while (i + 8 <= count) {
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|
||||||
d[i + 0] = value;
|
|
||||||
d[i + 1] = value;
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|
||||||
d[i + 2] = value;
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|
||||||
d[i + 3] = value;
|
|
||||||
d[i + 4] = value;
|
|
||||||
d[i + 5] = value;
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|
||||||
d[i + 6] = value;
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|
||||||
d[i + 7] = value;
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|
||||||
i += 8;
|
|
||||||
}
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|
||||||
|
|
||||||
/* Handle remainder */
|
|
||||||
while (i < count) {
|
|
||||||
d[i] = value;
|
|
||||||
i++;
|
|
||||||
}
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|
||||||
}
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|
||||||
|
|
||||||
/* Compare memory with early exit optimization */
|
|
||||||
static inline int riscv_memcmp_fast(const void *s1, const void *s2, size_t n)
|
|
||||||
{
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|
||||||
const uint64_t *a = (const uint64_t *)s1;
|
|
||||||
const uint64_t *b = (const uint64_t *)s2;
|
|
||||||
|
|
||||||
size_t qwords = n / 8;
|
|
||||||
for (size_t i = 0; i < qwords; ++i) {
|
|
||||||
if (a[i] != b[i]) {
|
|
||||||
/* Use byte comparison to find first difference */
|
|
||||||
const uint8_t *ba = (const uint8_t *)a;
|
|
||||||
const uint8_t *bb = (const uint8_t *)b;
|
|
||||||
for (size_t j = i * 8; j < (i + 1) * 8 && j < n; ++j) {
|
|
||||||
if (ba[j] != bb[j]) {
|
|
||||||
return ba[j] - bb[j];
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Check remainder */
|
|
||||||
size_t remainder = n % 8;
|
|
||||||
if (remainder > 0) {
|
|
||||||
const uint8_t *ba = (const uint8_t *)s1 + qwords * 8;
|
|
||||||
const uint8_t *bb = (const uint8_t *)s2 + qwords * 8;
|
|
||||||
for (size_t i = 0; i < remainder; ++i) {
|
|
||||||
if (ba[i] != bb[i]) {
|
|
||||||
return ba[i] - bb[i];
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Atomic operations - optimized for RISC-V A extension */
|
|
||||||
|
|
||||||
typedef volatile uint64_t riscv_atomic64_t;
|
|
||||||
|
|
||||||
static inline uint64_t riscv_atomic64_load(const riscv_atomic64_t *p)
|
|
||||||
{
|
|
||||||
riscv_lfence(); /* Ensure load-acquire semantics */
|
|
||||||
return *p;
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void riscv_atomic64_store(riscv_atomic64_t *p, uint64_t v)
|
|
||||||
{
|
|
||||||
riscv_sfence(); /* Ensure store-release semantics */
|
|
||||||
*p = v;
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline uint64_t riscv_atomic64_exchange(riscv_atomic64_t *p, uint64_t v)
|
|
||||||
{
|
|
||||||
uint64_t old;
|
|
||||||
asm volatile ("amoswap.d.aq %0, %2, (%1)" : "=r"(old) : "r"(p), "r"(v) : "memory");
|
|
||||||
return old;
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline uint64_t riscv_atomic64_add(riscv_atomic64_t *p, uint64_t v)
|
|
||||||
{
|
|
||||||
uint64_t old;
|
|
||||||
asm volatile ("amoadd.d.aq %0, %2, (%1)" : "=r"(old) : "r"(p), "r"(v) : "memory");
|
|
||||||
return old;
|
|
||||||
}
|
|
||||||
|
|
||||||
#else /* !XMRIG_RISCV */
|
|
||||||
|
|
||||||
/* Fallback implementations for non-RISC-V */
|
|
||||||
|
|
||||||
#define CACHELINE_SIZE 64
|
|
||||||
|
|
||||||
static inline void riscv_mfence(void) { __sync_synchronize(); }
|
|
||||||
static inline void riscv_lfence(void) { __sync_synchronize(); }
|
|
||||||
static inline void riscv_sfence(void) { __sync_synchronize(); }
|
|
||||||
static inline void riscv_fence_tso(void) { __sync_synchronize(); }
|
|
||||||
static inline void riscv_acquire_fence(void) { __sync_synchronize(); }
|
|
||||||
static inline void riscv_release_fence(void) { __sync_synchronize(); }
|
|
||||||
static inline void riscv_pause(void) { }
|
|
||||||
|
|
||||||
static inline void riscv_prefetch_read(const void *addr) { __builtin_prefetch(addr, 0, 3); }
|
|
||||||
static inline void riscv_prefetch_write(const void *addr) { __builtin_prefetch(addr, 1, 3); }
|
|
||||||
static inline void riscv_prefetch_nta(const void *addr) { __builtin_prefetch(addr, 0, 0); }
|
|
||||||
static inline void riscv_clflush(const void *addr) { (void)addr; }
|
|
||||||
|
|
||||||
static inline void riscv_memcpy_prefetch(void *dest, const void *src, size_t size)
|
|
||||||
{
|
|
||||||
memcpy(dest, src, size);
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void riscv_memfill64(void *dest, uint64_t value, size_t count)
|
|
||||||
{
|
|
||||||
for (size_t i = 0; i < count; ++i) {
|
|
||||||
((uint64_t *)dest)[i] = value;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline int riscv_memcmp_fast(const void *s1, const void *s2, size_t n)
|
|
||||||
{
|
|
||||||
return memcmp(s1, s2, n);
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif // XMRIG_RISCV_MEMORY_H
|
|
||||||
@@ -1,256 +0,0 @@
|
|||||||
/* XMRig
|
|
||||||
* Copyright (c) 2025 Slayingripper <https://github.com/Slayingripper>
|
|
||||||
* Copyright (c) 2018-2025 SChernykh <https://github.com/SChernykh>
|
|
||||||
* Copyright (c) 2016-2025 XMRig <support@xmrig.com>
|
|
||||||
*
|
|
||||||
* This program is free software: you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation, either version 3 of the License, or
|
|
||||||
* (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* RISC-V Vector Extension (RVV) Optimizations for XMRig
|
|
||||||
*
|
|
||||||
* Leverages RVV for parallel cryptographic operations
|
|
||||||
* Automatically falls back to scalar if RVV unavailable
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef XMRIG_RISCV_RVV_H
|
|
||||||
#define XMRIG_RISCV_RVV_H
|
|
||||||
|
|
||||||
#include <riscv_vector.h>
|
|
||||||
#include <stdint.h>
|
|
||||||
#include <string.h>
|
|
||||||
|
|
||||||
#ifdef __riscv_v_elen
|
|
||||||
#define XMRIG_RVV_ENABLED 1
|
|
||||||
#define XMRIG_RVV_ELEN __riscv_v_elen
|
|
||||||
#else
|
|
||||||
#define XMRIG_RVV_ENABLED 0
|
|
||||||
#define XMRIG_RVV_ELEN 64
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Vector length in bits */
|
|
||||||
#define RVV_VLEN __riscv_v_max_vlen
|
|
||||||
|
|
||||||
/* Detect VLEN at runtime if available */
|
|
||||||
static inline uint32_t riscv_rvv_vlen(void) {
|
|
||||||
#ifdef __riscv_v_max_vlen
|
|
||||||
return __riscv_v_max_vlen;
|
|
||||||
#else
|
|
||||||
/* Fallback: typical VLEN is 128, 256, or 512 bits */
|
|
||||||
return 128;
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Detect if RVV is available at runtime */
|
|
||||||
static inline int riscv_has_rvv(void) {
|
|
||||||
#ifdef __riscv_v
|
|
||||||
return 1;
|
|
||||||
#else
|
|
||||||
return 0;
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
#if XMRIG_RVV_ENABLED
|
|
||||||
|
|
||||||
/* Vectorized 64-bit memory copy using RVV
|
|
||||||
* Copies 'size' bytes from src to dst using vector operations
|
|
||||||
* Assumes size is multiple of vector element width
|
|
||||||
*/
|
|
||||||
static inline void riscv_memcpy_rvv(void *dst, const void *src, size_t size) {
|
|
||||||
const uint8_t *s = (const uint8_t *)src;
|
|
||||||
uint8_t *d = (uint8_t *)dst;
|
|
||||||
|
|
||||||
/* Process in 64-byte chunks with RVV */
|
|
||||||
size_t vl;
|
|
||||||
uint64_t *d64 = (uint64_t *)dst;
|
|
||||||
const uint64_t *s64 = (const uint64_t *)src;
|
|
||||||
size_t count = size / 8;
|
|
||||||
|
|
||||||
size_t i = 0;
|
|
||||||
while (i < count) {
|
|
||||||
vl = __riscv_vsetvl_e64m1(count - i);
|
|
||||||
vfloat64m1_t vs = __riscv_vle64_v_f64m1((double *)(s64 + i), vl);
|
|
||||||
__riscv_vse64_v_f64m1((double *)(d64 + i), vs, vl);
|
|
||||||
i += vl;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Handle remainder */
|
|
||||||
size_t remainder = size % 8;
|
|
||||||
if (remainder) {
|
|
||||||
memcpy((uint8_t *)dst + size - remainder,
|
|
||||||
(uint8_t *)src + size - remainder,
|
|
||||||
remainder);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Vectorized memset using RVV - fill memory with pattern */
|
|
||||||
static inline void riscv_memset_rvv(void *dst, uint32_t pattern, size_t size) {
|
|
||||||
uint32_t *d32 = (uint32_t *)dst;
|
|
||||||
size_t count = size / 4;
|
|
||||||
size_t vl, i = 0;
|
|
||||||
|
|
||||||
while (i < count) {
|
|
||||||
vl = __riscv_vsetvl_e32m1(count - i);
|
|
||||||
vuint32m1_t vp = __riscv_vmv_v_x_u32m1(pattern, vl);
|
|
||||||
__riscv_vse32_v_u32m1(d32 + i, vp, vl);
|
|
||||||
i += vl;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Handle remainder */
|
|
||||||
size_t remainder = size % 4;
|
|
||||||
if (remainder) {
|
|
||||||
memset((uint8_t *)dst + size - remainder,
|
|
||||||
pattern & 0xFF,
|
|
||||||
remainder);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Vectorized XOR operation - a ^= b for size bytes */
|
|
||||||
static inline void riscv_xor_rvv(void *a, const void *b, size_t size) {
|
|
||||||
uint64_t *a64 = (uint64_t *)a;
|
|
||||||
const uint64_t *b64 = (const uint64_t *)b;
|
|
||||||
size_t count = size / 8;
|
|
||||||
size_t vl, i = 0;
|
|
||||||
|
|
||||||
while (i < count) {
|
|
||||||
vl = __riscv_vsetvl_e64m1(count - i);
|
|
||||||
vuint64m1_t va = __riscv_vle64_v_u64m1(a64 + i, vl);
|
|
||||||
vuint64m1_t vb = __riscv_vle64_v_u64m1(b64 + i, vl);
|
|
||||||
vuint64m1_t vc = __riscv_vxor_vv_u64m1(va, vb, vl);
|
|
||||||
__riscv_vse64_v_u64m1(a64 + i, vc, vl);
|
|
||||||
i += vl;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Handle remainder */
|
|
||||||
size_t remainder = size % 8;
|
|
||||||
if (remainder) {
|
|
||||||
uint8_t *a8 = (uint8_t *)a;
|
|
||||||
const uint8_t *b8 = (const uint8_t *)b;
|
|
||||||
for (size_t j = 0; j < remainder; j++) {
|
|
||||||
a8[size - remainder + j] ^= b8[size - remainder + j];
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Vectorized memory comparison - returns 0 if equal, first differing byte difference otherwise */
|
|
||||||
static inline int riscv_memcmp_rvv(const void *a, const void *b, size_t size) {
|
|
||||||
const uint64_t *a64 = (const uint64_t *)a;
|
|
||||||
const uint64_t *b64 = (const uint64_t *)b;
|
|
||||||
size_t count = size / 8;
|
|
||||||
size_t vl, i = 0;
|
|
||||||
|
|
||||||
while (i < count) {
|
|
||||||
vl = __riscv_vsetvl_e64m1(count - i);
|
|
||||||
vuint64m1_t va = __riscv_vle64_v_u64m1(a64 + i, vl);
|
|
||||||
vuint64m1_t vb = __riscv_vle64_v_u64m1(b64 + i, vl);
|
|
||||||
vbool64_t cmp = __riscv_vmsne_vv_u64m1_b64(va, vb, vl);
|
|
||||||
|
|
||||||
if (__riscv_vcpop_m_b64(cmp, vl) > 0) {
|
|
||||||
/* Found difference, fall back to scalar for exact position */
|
|
||||||
goto scalar_fallback;
|
|
||||||
}
|
|
||||||
i += vl;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Check remainder */
|
|
||||||
size_t remainder = size % 8;
|
|
||||||
if (remainder) {
|
|
||||||
const uint8_t *a8 = (const uint8_t *)a;
|
|
||||||
const uint8_t *b8 = (const uint8_t *)b;
|
|
||||||
for (size_t j = 0; j < remainder; j++) {
|
|
||||||
if (a8[size - remainder + j] != b8[size - remainder + j]) {
|
|
||||||
return a8[size - remainder + j] - b8[size - remainder + j];
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
|
|
||||||
scalar_fallback:
|
|
||||||
return memcmp(a, b, size);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Vectorized 256-bit rotation for RandomX AES operations */
|
|
||||||
static inline void riscv_aes_rotate_rvv(uint32_t *data, size_t count) {
|
|
||||||
/* Rotate 32-bit elements by 8 bits within 256-bit vectors */
|
|
||||||
size_t vl, i = 0;
|
|
||||||
|
|
||||||
while (i < count) {
|
|
||||||
vl = __riscv_vsetvl_e32m1(count - i);
|
|
||||||
vuint32m1_t v = __riscv_vle32_v_u32m1(data + i, vl);
|
|
||||||
|
|
||||||
/* Rotate left by 8: (x << 8) | (x >> 24) */
|
|
||||||
vuint32m1_t shifted_left = __riscv_vsll_vx_u32m1(v, 8, vl);
|
|
||||||
vuint32m1_t shifted_right = __riscv_vsrl_vx_u32m1(v, 24, vl);
|
|
||||||
vuint32m1_t result = __riscv_vor_vv_u32m1(shifted_left, shifted_right, vl);
|
|
||||||
|
|
||||||
__riscv_vse32_v_u32m1(data + i, result, vl);
|
|
||||||
i += vl;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Parallel AES SubBytes operation using RVV */
|
|
||||||
static inline void riscv_aes_subbytes_rvv(uint8_t *state, size_t size) {
|
|
||||||
/* This is a simplified version - real AES SubBytes uses lookup tables */
|
|
||||||
size_t vl, i = 0;
|
|
||||||
|
|
||||||
while (i < size) {
|
|
||||||
vl = __riscv_vsetvl_e8m1(size - i);
|
|
||||||
vuint8m1_t v = __riscv_vle8_v_u8m1(state + i, vl);
|
|
||||||
|
|
||||||
/* Placeholder: in real implementation, use AES SBOX lookup */
|
|
||||||
/* For now, just apply a simple transformation */
|
|
||||||
vuint8m1_t result = __riscv_vxor_vx_u8m1(v, 0x63, vl);
|
|
||||||
|
|
||||||
__riscv_vse8_v_u8m1(state + i, result, vl);
|
|
||||||
i += vl;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
#else /* Scalar fallback when RVV unavailable */
|
|
||||||
|
|
||||||
static inline void riscv_memcpy_rvv(void *dst, const void *src, size_t size) {
|
|
||||||
memcpy(dst, src, size);
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void riscv_memset_rvv(void *dst, uint32_t pattern, size_t size) {
|
|
||||||
memset(dst, pattern & 0xFF, size);
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void riscv_xor_rvv(void *a, const void *b, size_t size) {
|
|
||||||
uint8_t *a8 = (uint8_t *)a;
|
|
||||||
const uint8_t *b8 = (const uint8_t *)b;
|
|
||||||
for (size_t i = 0; i < size; i++) {
|
|
||||||
a8[i] ^= b8[i];
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline int riscv_memcmp_rvv(const void *a, const void *b, size_t size) {
|
|
||||||
return memcmp(a, b, size);
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void riscv_aes_rotate_rvv(uint32_t *data, size_t count) {
|
|
||||||
for (size_t i = 0; i < count; i++) {
|
|
||||||
data[i] = (data[i] << 8) | (data[i] >> 24);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void riscv_aes_subbytes_rvv(uint8_t *state, size_t size) {
|
|
||||||
for (size_t i = 0; i < size; i++) {
|
|
||||||
state[i] ^= 0x63;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif /* XMRIG_RVV_ENABLED */
|
|
||||||
|
|
||||||
#endif /* XMRIG_RISCV_RVV_H */
|
|
||||||
@@ -1,124 +0,0 @@
|
|||||||
/* XMRig
|
|
||||||
* Copyright (c) 2025 XMRig <https://github.com/xmrig>, <support@xmrig.com>
|
|
||||||
*
|
|
||||||
* This program is free software: you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation, either version 3 of the License, or
|
|
||||||
* (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* RISC-V optimized RandomX dataset initialization
|
|
||||||
* Optimizations:
|
|
||||||
* - Adaptive thread allocation based on CPU cores
|
|
||||||
* - Prefetch hints for better cache utilization
|
|
||||||
* - Memory alignment optimizations for RISC-V
|
|
||||||
* - Efficient barrier operations
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef XMRIG_RXDATASET_RISCV_H
|
|
||||||
#define XMRIG_RXDATASET_RISCV_H
|
|
||||||
|
|
||||||
#include <stdint.h>
|
|
||||||
#include <unistd.h>
|
|
||||||
#include <sched.h>
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(XMRIG_RISCV)
|
|
||||||
|
|
||||||
/* RISC-V memory prefetch macros */
|
|
||||||
#define PREFETCH_READ(addr) asm volatile ("prefetch.r %0" : : "r"(addr) : "memory")
|
|
||||||
#define PREFETCH_WRITE(addr) asm volatile ("prefetch.w %0" : : "r"(addr) : "memory")
|
|
||||||
#define MEMORY_BARRIER() asm volatile ("fence rw,rw" : : : "memory")
|
|
||||||
#define READ_BARRIER() asm volatile ("fence r,r" : : : "memory")
|
|
||||||
#define WRITE_BARRIER() asm volatile ("fence w,w" : : : "memory")
|
|
||||||
|
|
||||||
/* RISC-V hint pause - tries Zihintpause, falls back to NOP */
|
|
||||||
static inline void cpu_pause(void)
|
|
||||||
{
|
|
||||||
asm volatile ("pause");
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Adaptive thread count calculation for dataset init */
|
|
||||||
static inline uint32_t riscv_optimal_init_threads(uint32_t available_threads)
|
|
||||||
{
|
|
||||||
/* On RISC-V, use 60-75% of available threads for init */
|
|
||||||
/* This leaves some threads available for OS/other tasks */
|
|
||||||
uint32_t recommended = (available_threads * 3) / 4;
|
|
||||||
return recommended > 0 ? recommended : 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Prefetch next dataset item for better cache utilization */
|
|
||||||
static inline void prefetch_dataset_item(const void *item, size_t size)
|
|
||||||
{
|
|
||||||
const uint8_t *ptr = (const uint8_t *)item;
|
|
||||||
/* Prefetch cache line aligned chunks */
|
|
||||||
for (size_t i = 0; i < size; i += 64) {
|
|
||||||
PREFETCH_READ(ptr + i);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Cache-aware aligned memory copy optimized for RISC-V */
|
|
||||||
static inline void aligned_memcpy_opt(void *dst, const void *src, size_t size)
|
|
||||||
{
|
|
||||||
uint64_t *d = (uint64_t *)dst;
|
|
||||||
const uint64_t *s = (const uint64_t *)src;
|
|
||||||
|
|
||||||
/* Process in 64-byte chunks with prefetching */
|
|
||||||
size_t chunks = size / 8;
|
|
||||||
for (size_t i = 0; i < chunks; i += 8) {
|
|
||||||
if (i + 8 < chunks) {
|
|
||||||
prefetch_dataset_item(s + i + 8, 64);
|
|
||||||
}
|
|
||||||
d[i] = s[i];
|
|
||||||
d[i+1] = s[i+1];
|
|
||||||
d[i+2] = s[i+2];
|
|
||||||
d[i+3] = s[i+3];
|
|
||||||
d[i+4] = s[i+4];
|
|
||||||
d[i+5] = s[i+5];
|
|
||||||
d[i+6] = s[i+6];
|
|
||||||
d[i+7] = s[i+7];
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Get optimal CPU core for thread pinning */
|
|
||||||
static inline int get_optimal_cpu_core(int thread_id)
|
|
||||||
{
|
|
||||||
long nprocs = sysconf(_SC_NPROCESSORS_ONLN);
|
|
||||||
if (nprocs <= 0) nprocs = 1;
|
|
||||||
return thread_id % nprocs;
|
|
||||||
}
|
|
||||||
|
|
||||||
#else /* !XMRIG_RISCV */
|
|
||||||
|
|
||||||
/* Fallback for non-RISC-V architectures */
|
|
||||||
#define PREFETCH_READ(addr)
|
|
||||||
#define PREFETCH_WRITE(addr)
|
|
||||||
#define MEMORY_BARRIER() __sync_synchronize()
|
|
||||||
#define READ_BARRIER() __sync_synchronize()
|
|
||||||
#define WRITE_BARRIER() __sync_synchronize()
|
|
||||||
|
|
||||||
static inline void cpu_pause(void) { }
|
|
||||||
static inline uint32_t riscv_optimal_init_threads(uint32_t available) { return available; }
|
|
||||||
static inline void prefetch_dataset_item(const void *item, size_t size) { (void)item; (void)size; }
|
|
||||||
static inline void aligned_memcpy_opt(void *dst, const void *src, size_t size) { memcpy(dst, src, size); }
|
|
||||||
static inline int get_optimal_cpu_core(int thread_id) { return thread_id; }
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif // XMRIG_RXDATASET_RISCV_H
|
|
||||||
Reference in New Issue
Block a user