From 27c8e60919eb8fb6735e315f2406384844a4e2bf Mon Sep 17 00:00:00 2001 From: SChernykh <15806605+SChernykh@users.noreply.github.com> Date: Wed, 22 Oct 2025 23:31:02 +0200 Subject: [PATCH] Removed unused files --- src/crypto/riscv/riscv_crypto.h | 186 --------------------- src/crypto/riscv/riscv_memory.h | 283 -------------------------------- src/crypto/riscv/riscv_rvv.h | 256 ----------------------------- src/crypto/rx/RxDataset_riscv.h | 124 -------------- 4 files changed, 849 deletions(-) delete mode 100644 src/crypto/riscv/riscv_crypto.h delete mode 100644 src/crypto/riscv/riscv_memory.h delete mode 100644 src/crypto/riscv/riscv_rvv.h delete mode 100644 src/crypto/rx/RxDataset_riscv.h diff --git a/src/crypto/riscv/riscv_crypto.h b/src/crypto/riscv/riscv_crypto.h deleted file mode 100644 index 4e0489243..000000000 --- a/src/crypto/riscv/riscv_crypto.h +++ /dev/null @@ -1,186 +0,0 @@ -/* XMRig - * Copyright (c) 2025 XMRig , - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* - * RISC-V Crypto Extensions (Zbk*) Support - * - * Supports detection and usage of RISC-V crypto extensions: - * - Zkn: NIST approved cryptographic extensions (AES, SHA2, SHA3) - * - Zknd/Zkne: AES decryption/encryption - * - Zknh: SHA2/SHA3 hash extensions - * - Zkb: Bit manipulation extensions (Zba, Zbb, Zbc, Zbs) - * - * Falls back gracefully to software implementations on systems without support. - */ - -#ifndef XMRIG_RISCV_CRYPTO_H -#define XMRIG_RISCV_CRYPTO_H - -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined(XMRIG_RISCV) - -/* Check if RISC-V crypto extensions are available at compile time */ -#if defined(__riscv_zkne) || defined(__riscv_zknd) -#define HAVE_RISCV_AES 1 -#else -#define HAVE_RISCV_AES 0 -#endif - -#if defined(__riscv_zknh) -#define HAVE_RISCV_SHA 1 -#else -#define HAVE_RISCV_SHA 0 -#endif - -#if defined(__riscv_zba) && defined(__riscv_zbb) && defined(__riscv_zbc) -#define HAVE_RISCV_BIT_MANIP 1 -#else -#define HAVE_RISCV_BIT_MANIP 0 -#endif - -/* Detect CPU support at runtime via /proc/cpuinfo */ -extern bool riscv_cpu_has_aes_support(void); -extern bool riscv_cpu_has_sha_support(void); -extern bool riscv_cpu_has_bitmanip_support(void); - -/* Software fallback AES utilities optimized for RISC-V */ - -/* AES S-box lookup - cache-friendly implementation */ -typedef struct { - uint32_t sbox_enc[256]; - uint32_t sbox_dec[256]; -} riscv_aes_sbox_t; - -extern const riscv_aes_sbox_t riscv_aes_tables; - -/* Software AES encryption round optimized for RISC-V */ -static inline uint32_t riscv_aes_enc_round(uint32_t input, const uint32_t *round_key) -{ - uint32_t result = 0; - - /* Unroll byte-by-byte lookups for better instruction-level parallelism */ - uint32_t b0 = (input >> 0) & 0xFF; - uint32_t b1 = (input >> 8) & 0xFF; - uint32_t b2 = (input >> 16) & 0xFF; - uint32_t b3 = (input >> 24) & 0xFF; - - result = riscv_aes_tables.sbox_enc[b0] ^ - riscv_aes_tables.sbox_enc[b1] ^ - riscv_aes_tables.sbox_enc[b2] ^ - riscv_aes_tables.sbox_enc[b3]; - - return result ^ (*round_key); -} - -/* Bit rotation optimized for RISC-V */ -static inline uint32_t riscv_rotr32(uint32_t x, int r) -{ -#if defined(__riscv_zbb) - /* Use RISC-V bit rotation if available */ - uint32_t result; - asm volatile ("ror %0, %1, %2" : "=r"(result) : "r"(x), "r"(r) : ); - return result; -#else - /* Scalar fallback */ - return (x >> r) | (x << (32 - r)); -#endif -} - -static inline uint64_t riscv_rotr64(uint64_t x, int r) -{ -#if defined(__riscv_zbb) - /* Use RISC-V bit rotation if available */ - uint64_t result; - asm volatile ("ror %0, %1, %2" : "=r"(result) : "r"(x), "r"(r) : ); - return result; -#else - /* Scalar fallback */ - return (x >> r) | (x << (64 - r)); -#endif -} - -/* Bit count operations optimized for RISC-V */ -static inline int riscv_popcount(uint64_t x) -{ -#if defined(__riscv_zbb) - /* Use hardware popcount if available */ - int result; - asm volatile ("cpop %0, %1" : "=r"(result) : "r"(x) : ); - return result; -#else - /* Scalar fallback */ - return __builtin_popcountll(x); -#endif -} - -static inline int riscv_ctz(uint64_t x) -{ -#if defined(__riscv_zbb) - /* Use hardware count trailing zeros if available */ - int result; - asm volatile ("ctz %0, %1" : "=r"(result) : "r"(x) : ); - return result; -#else - /* Scalar fallback */ - return __builtin_ctzll(x); -#endif -} - -/* Bit manipulation operations from Zba */ -static inline uint64_t riscv_add_uw(uint64_t a, uint64_t b) -{ -#if defined(__riscv_zba) - /* Add unsigned word (add.uw) - zero extends 32-bit addition */ - uint64_t result; - asm volatile ("add.uw %0, %1, %2" : "=r"(result) : "r"(a), "r"(b) : ); - return result; -#else - return ((a & 0xFFFFFFFF) + (b & 0xFFFFFFFF)) & 0xFFFFFFFF; -#endif -} - -#else /* !XMRIG_RISCV */ - -/* Non-RISC-V fallbacks */ -#define HAVE_RISCV_AES 0 -#define HAVE_RISCV_SHA 0 -#define HAVE_RISCV_BIT_MANIP 0 - -static inline bool riscv_cpu_has_aes_support(void) { return false; } -static inline bool riscv_cpu_has_sha_support(void) { return false; } -static inline bool riscv_cpu_has_bitmanip_support(void) { return false; } - -static inline uint32_t riscv_rotr32(uint32_t x, int r) { return (x >> r) | (x << (32 - r)); } -static inline uint64_t riscv_rotr64(uint64_t x, int r) { return (x >> r) | (x << (64 - r)); } -static inline int riscv_popcount(uint64_t x) { return __builtin_popcountll(x); } -static inline int riscv_ctz(uint64_t x) { return __builtin_ctzll(x); } -static inline uint64_t riscv_add_uw(uint64_t a, uint64_t b) { return (a & 0xFFFFFFFF) + (b & 0xFFFFFFFF); } - -#endif - -#ifdef __cplusplus -} -#endif - -#endif // XMRIG_RISCV_CRYPTO_H diff --git a/src/crypto/riscv/riscv_memory.h b/src/crypto/riscv/riscv_memory.h deleted file mode 100644 index f2dc9b19f..000000000 --- a/src/crypto/riscv/riscv_memory.h +++ /dev/null @@ -1,283 +0,0 @@ -/* XMRig - * Copyright (c) 2025 XMRig , - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* - * RISC-V optimized memory operations - * - * Provides efficient: - * - Memory barriers - * - Cache line operations - * - Prefetching hints - * - Aligned memory access - * - Memory pooling utilities - */ - -#ifndef XMRIG_RISCV_MEMORY_H -#define XMRIG_RISCV_MEMORY_H - -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined(XMRIG_RISCV) - -#define CACHELINE_SIZE 64 -#define CACHELINE_MASK (~(CACHELINE_SIZE - 1)) - -/* Memory barriers - optimized for RISC-V */ - -/* Full memory barrier: all reads and writes before must complete before any after */ -static inline void riscv_mfence(void) -{ - asm volatile ("fence rw,rw" : : : "memory"); -} - -/* Load barrier: all loads before must complete before any after */ -static inline void riscv_lfence(void) -{ - asm volatile ("fence r,r" : : : "memory"); -} - -/* Store barrier: all stores before must complete before any after */ -static inline void riscv_sfence(void) -{ - asm volatile ("fence w,w" : : : "memory"); -} - -/* TSO (total store order) - ensures store-release semantics */ -static inline void riscv_fence_tso(void) -{ - asm volatile ("fence rw,w" : : : "memory"); -} - -/* Acquire barrier - for lock acquisition */ -static inline void riscv_acquire_fence(void) -{ - asm volatile ("fence r,rw" : : : "memory"); -} - -/* Release barrier - for lock release */ -static inline void riscv_release_fence(void) -{ - asm volatile ("fence rw,w" : : : "memory"); -} - -/* CPU pause hint (Zihintpause extension, falls back to NOP) */ -static inline void riscv_pause(void) -{ - asm volatile ("pause"); -} - -/* Prefetch operations - hints to load into L1 cache */ - -/* Prefetch for read (temporal locality) */ -static inline void riscv_prefetch_read(const void *addr) -{ - /* Temporary workaround: use inline asm */ - asm volatile ("# prefetch %0 \n" : : "m"(*(const char *)addr)); -} - -/* Prefetch for write (prepare for store) */ -static inline void riscv_prefetch_write(const void *addr) -{ - asm volatile ("# prefetch.w %0 \n" : : "m"(*(const char *)addr)); -} - -/* Prefetch with 0 temporal locality (load into L1 but not higher levels) */ -static inline void riscv_prefetch_nta(const void *addr) -{ - asm volatile ("# prefetch.nta %0 \n" : : "m"(*(const char *)addr)); -} - -/* Cache line flush (if supported) */ -static inline void riscv_clflush(const void *addr) -{ - /* RISC-V may not have cache flush in userspace */ - /* This is a no-op unless running in privileged mode */ - (void)addr; -} - -/* Optimized memory copy with cache prefetching */ -static inline void riscv_memcpy_prefetch(void *dest, const void *src, size_t size) -{ - uint8_t *d = (uint8_t *)dest; - const uint8_t *s = (const uint8_t *)src; - - /* Process in cache line sized chunks with prefetching */ - size_t cache_lines = size / CACHELINE_SIZE; - for (size_t i = 0; i < cache_lines; ++i) { - /* Prefetch next cache lines ahead */ - if (i + 4 < cache_lines) { - riscv_prefetch_read(s + (i + 4) * CACHELINE_SIZE); - } - - /* Copy current cache line - use 64-bit accesses for efficiency */ - const uint64_t *src64 = (const uint64_t *)(s + i * CACHELINE_SIZE); - uint64_t *dest64 = (uint64_t *)(d + i * CACHELINE_SIZE); - - for (int j = 0; j < 8; ++j) { /* 8 * 8 bytes = 64 bytes */ - dest64[j] = src64[j]; - } - } - - /* Handle remainder */ - size_t remainder = size % CACHELINE_SIZE; - if (remainder > 0) { - memcpy(d + cache_lines * CACHELINE_SIZE, - s + cache_lines * CACHELINE_SIZE, - remainder); - } -} - -/* Optimized memory fill with pattern */ -static inline void riscv_memfill64(void *dest, uint64_t value, size_t count) -{ - uint64_t *d = (uint64_t *)dest; - - /* Unroll loop for better ILP */ - size_t i = 0; - while (i + 8 <= count) { - d[i + 0] = value; - d[i + 1] = value; - d[i + 2] = value; - d[i + 3] = value; - d[i + 4] = value; - d[i + 5] = value; - d[i + 6] = value; - d[i + 7] = value; - i += 8; - } - - /* Handle remainder */ - while (i < count) { - d[i] = value; - i++; - } -} - -/* Compare memory with early exit optimization */ -static inline int riscv_memcmp_fast(const void *s1, const void *s2, size_t n) -{ - const uint64_t *a = (const uint64_t *)s1; - const uint64_t *b = (const uint64_t *)s2; - - size_t qwords = n / 8; - for (size_t i = 0; i < qwords; ++i) { - if (a[i] != b[i]) { - /* Use byte comparison to find first difference */ - const uint8_t *ba = (const uint8_t *)a; - const uint8_t *bb = (const uint8_t *)b; - for (size_t j = i * 8; j < (i + 1) * 8 && j < n; ++j) { - if (ba[j] != bb[j]) { - return ba[j] - bb[j]; - } - } - } - } - - /* Check remainder */ - size_t remainder = n % 8; - if (remainder > 0) { - const uint8_t *ba = (const uint8_t *)s1 + qwords * 8; - const uint8_t *bb = (const uint8_t *)s2 + qwords * 8; - for (size_t i = 0; i < remainder; ++i) { - if (ba[i] != bb[i]) { - return ba[i] - bb[i]; - } - } - } - - return 0; -} - -/* Atomic operations - optimized for RISC-V A extension */ - -typedef volatile uint64_t riscv_atomic64_t; - -static inline uint64_t riscv_atomic64_load(const riscv_atomic64_t *p) -{ - riscv_lfence(); /* Ensure load-acquire semantics */ - return *p; -} - -static inline void riscv_atomic64_store(riscv_atomic64_t *p, uint64_t v) -{ - riscv_sfence(); /* Ensure store-release semantics */ - *p = v; -} - -static inline uint64_t riscv_atomic64_exchange(riscv_atomic64_t *p, uint64_t v) -{ - uint64_t old; - asm volatile ("amoswap.d.aq %0, %2, (%1)" : "=r"(old) : "r"(p), "r"(v) : "memory"); - return old; -} - -static inline uint64_t riscv_atomic64_add(riscv_atomic64_t *p, uint64_t v) -{ - uint64_t old; - asm volatile ("amoadd.d.aq %0, %2, (%1)" : "=r"(old) : "r"(p), "r"(v) : "memory"); - return old; -} - -#else /* !XMRIG_RISCV */ - -/* Fallback implementations for non-RISC-V */ - -#define CACHELINE_SIZE 64 - -static inline void riscv_mfence(void) { __sync_synchronize(); } -static inline void riscv_lfence(void) { __sync_synchronize(); } -static inline void riscv_sfence(void) { __sync_synchronize(); } -static inline void riscv_fence_tso(void) { __sync_synchronize(); } -static inline void riscv_acquire_fence(void) { __sync_synchronize(); } -static inline void riscv_release_fence(void) { __sync_synchronize(); } -static inline void riscv_pause(void) { } - -static inline void riscv_prefetch_read(const void *addr) { __builtin_prefetch(addr, 0, 3); } -static inline void riscv_prefetch_write(const void *addr) { __builtin_prefetch(addr, 1, 3); } -static inline void riscv_prefetch_nta(const void *addr) { __builtin_prefetch(addr, 0, 0); } -static inline void riscv_clflush(const void *addr) { (void)addr; } - -static inline void riscv_memcpy_prefetch(void *dest, const void *src, size_t size) -{ - memcpy(dest, src, size); -} - -static inline void riscv_memfill64(void *dest, uint64_t value, size_t count) -{ - for (size_t i = 0; i < count; ++i) { - ((uint64_t *)dest)[i] = value; - } -} - -static inline int riscv_memcmp_fast(const void *s1, const void *s2, size_t n) -{ - return memcmp(s1, s2, n); -} - -#endif - -#ifdef __cplusplus -} -#endif - -#endif // XMRIG_RISCV_MEMORY_H diff --git a/src/crypto/riscv/riscv_rvv.h b/src/crypto/riscv/riscv_rvv.h deleted file mode 100644 index da69d12c6..000000000 --- a/src/crypto/riscv/riscv_rvv.h +++ /dev/null @@ -1,256 +0,0 @@ -/* XMRig - * Copyright (c) 2025 Slayingripper - * Copyright (c) 2018-2025 SChernykh - * Copyright (c) 2016-2025 XMRig - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* - * RISC-V Vector Extension (RVV) Optimizations for XMRig - * - * Leverages RVV for parallel cryptographic operations - * Automatically falls back to scalar if RVV unavailable - */ - -#ifndef XMRIG_RISCV_RVV_H -#define XMRIG_RISCV_RVV_H - -#include -#include -#include - -#ifdef __riscv_v_elen - #define XMRIG_RVV_ENABLED 1 - #define XMRIG_RVV_ELEN __riscv_v_elen -#else - #define XMRIG_RVV_ENABLED 0 - #define XMRIG_RVV_ELEN 64 -#endif - -/* Vector length in bits */ -#define RVV_VLEN __riscv_v_max_vlen - -/* Detect VLEN at runtime if available */ -static inline uint32_t riscv_rvv_vlen(void) { -#ifdef __riscv_v_max_vlen - return __riscv_v_max_vlen; -#else - /* Fallback: typical VLEN is 128, 256, or 512 bits */ - return 128; -#endif -} - -/* Detect if RVV is available at runtime */ -static inline int riscv_has_rvv(void) { -#ifdef __riscv_v - return 1; -#else - return 0; -#endif -} - -#if XMRIG_RVV_ENABLED - -/* Vectorized 64-bit memory copy using RVV - * Copies 'size' bytes from src to dst using vector operations - * Assumes size is multiple of vector element width - */ -static inline void riscv_memcpy_rvv(void *dst, const void *src, size_t size) { - const uint8_t *s = (const uint8_t *)src; - uint8_t *d = (uint8_t *)dst; - - /* Process in 64-byte chunks with RVV */ - size_t vl; - uint64_t *d64 = (uint64_t *)dst; - const uint64_t *s64 = (const uint64_t *)src; - size_t count = size / 8; - - size_t i = 0; - while (i < count) { - vl = __riscv_vsetvl_e64m1(count - i); - vfloat64m1_t vs = __riscv_vle64_v_f64m1((double *)(s64 + i), vl); - __riscv_vse64_v_f64m1((double *)(d64 + i), vs, vl); - i += vl; - } - - /* Handle remainder */ - size_t remainder = size % 8; - if (remainder) { - memcpy((uint8_t *)dst + size - remainder, - (uint8_t *)src + size - remainder, - remainder); - } -} - -/* Vectorized memset using RVV - fill memory with pattern */ -static inline void riscv_memset_rvv(void *dst, uint32_t pattern, size_t size) { - uint32_t *d32 = (uint32_t *)dst; - size_t count = size / 4; - size_t vl, i = 0; - - while (i < count) { - vl = __riscv_vsetvl_e32m1(count - i); - vuint32m1_t vp = __riscv_vmv_v_x_u32m1(pattern, vl); - __riscv_vse32_v_u32m1(d32 + i, vp, vl); - i += vl; - } - - /* Handle remainder */ - size_t remainder = size % 4; - if (remainder) { - memset((uint8_t *)dst + size - remainder, - pattern & 0xFF, - remainder); - } -} - -/* Vectorized XOR operation - a ^= b for size bytes */ -static inline void riscv_xor_rvv(void *a, const void *b, size_t size) { - uint64_t *a64 = (uint64_t *)a; - const uint64_t *b64 = (const uint64_t *)b; - size_t count = size / 8; - size_t vl, i = 0; - - while (i < count) { - vl = __riscv_vsetvl_e64m1(count - i); - vuint64m1_t va = __riscv_vle64_v_u64m1(a64 + i, vl); - vuint64m1_t vb = __riscv_vle64_v_u64m1(b64 + i, vl); - vuint64m1_t vc = __riscv_vxor_vv_u64m1(va, vb, vl); - __riscv_vse64_v_u64m1(a64 + i, vc, vl); - i += vl; - } - - /* Handle remainder */ - size_t remainder = size % 8; - if (remainder) { - uint8_t *a8 = (uint8_t *)a; - const uint8_t *b8 = (const uint8_t *)b; - for (size_t j = 0; j < remainder; j++) { - a8[size - remainder + j] ^= b8[size - remainder + j]; - } - } -} - -/* Vectorized memory comparison - returns 0 if equal, first differing byte difference otherwise */ -static inline int riscv_memcmp_rvv(const void *a, const void *b, size_t size) { - const uint64_t *a64 = (const uint64_t *)a; - const uint64_t *b64 = (const uint64_t *)b; - size_t count = size / 8; - size_t vl, i = 0; - - while (i < count) { - vl = __riscv_vsetvl_e64m1(count - i); - vuint64m1_t va = __riscv_vle64_v_u64m1(a64 + i, vl); - vuint64m1_t vb = __riscv_vle64_v_u64m1(b64 + i, vl); - vbool64_t cmp = __riscv_vmsne_vv_u64m1_b64(va, vb, vl); - - if (__riscv_vcpop_m_b64(cmp, vl) > 0) { - /* Found difference, fall back to scalar for exact position */ - goto scalar_fallback; - } - i += vl; - } - - /* Check remainder */ - size_t remainder = size % 8; - if (remainder) { - const uint8_t *a8 = (const uint8_t *)a; - const uint8_t *b8 = (const uint8_t *)b; - for (size_t j = 0; j < remainder; j++) { - if (a8[size - remainder + j] != b8[size - remainder + j]) { - return a8[size - remainder + j] - b8[size - remainder + j]; - } - } - } - return 0; - -scalar_fallback: - return memcmp(a, b, size); -} - -/* Vectorized 256-bit rotation for RandomX AES operations */ -static inline void riscv_aes_rotate_rvv(uint32_t *data, size_t count) { - /* Rotate 32-bit elements by 8 bits within 256-bit vectors */ - size_t vl, i = 0; - - while (i < count) { - vl = __riscv_vsetvl_e32m1(count - i); - vuint32m1_t v = __riscv_vle32_v_u32m1(data + i, vl); - - /* Rotate left by 8: (x << 8) | (x >> 24) */ - vuint32m1_t shifted_left = __riscv_vsll_vx_u32m1(v, 8, vl); - vuint32m1_t shifted_right = __riscv_vsrl_vx_u32m1(v, 24, vl); - vuint32m1_t result = __riscv_vor_vv_u32m1(shifted_left, shifted_right, vl); - - __riscv_vse32_v_u32m1(data + i, result, vl); - i += vl; - } -} - -/* Parallel AES SubBytes operation using RVV */ -static inline void riscv_aes_subbytes_rvv(uint8_t *state, size_t size) { - /* This is a simplified version - real AES SubBytes uses lookup tables */ - size_t vl, i = 0; - - while (i < size) { - vl = __riscv_vsetvl_e8m1(size - i); - vuint8m1_t v = __riscv_vle8_v_u8m1(state + i, vl); - - /* Placeholder: in real implementation, use AES SBOX lookup */ - /* For now, just apply a simple transformation */ - vuint8m1_t result = __riscv_vxor_vx_u8m1(v, 0x63, vl); - - __riscv_vse8_v_u8m1(state + i, result, vl); - i += vl; - } -} - -#else /* Scalar fallback when RVV unavailable */ - -static inline void riscv_memcpy_rvv(void *dst, const void *src, size_t size) { - memcpy(dst, src, size); -} - -static inline void riscv_memset_rvv(void *dst, uint32_t pattern, size_t size) { - memset(dst, pattern & 0xFF, size); -} - -static inline void riscv_xor_rvv(void *a, const void *b, size_t size) { - uint8_t *a8 = (uint8_t *)a; - const uint8_t *b8 = (const uint8_t *)b; - for (size_t i = 0; i < size; i++) { - a8[i] ^= b8[i]; - } -} - -static inline int riscv_memcmp_rvv(const void *a, const void *b, size_t size) { - return memcmp(a, b, size); -} - -static inline void riscv_aes_rotate_rvv(uint32_t *data, size_t count) { - for (size_t i = 0; i < count; i++) { - data[i] = (data[i] << 8) | (data[i] >> 24); - } -} - -static inline void riscv_aes_subbytes_rvv(uint8_t *state, size_t size) { - for (size_t i = 0; i < size; i++) { - state[i] ^= 0x63; - } -} - -#endif /* XMRIG_RVV_ENABLED */ - -#endif /* XMRIG_RISCV_RVV_H */ diff --git a/src/crypto/rx/RxDataset_riscv.h b/src/crypto/rx/RxDataset_riscv.h deleted file mode 100644 index b3761ca9f..000000000 --- a/src/crypto/rx/RxDataset_riscv.h +++ /dev/null @@ -1,124 +0,0 @@ -/* XMRig - * Copyright (c) 2025 XMRig , - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* - * RISC-V optimized RandomX dataset initialization - * Optimizations: - * - Adaptive thread allocation based on CPU cores - * - Prefetch hints for better cache utilization - * - Memory alignment optimizations for RISC-V - * - Efficient barrier operations - */ - -#ifndef XMRIG_RXDATASET_RISCV_H -#define XMRIG_RXDATASET_RISCV_H - -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined(XMRIG_RISCV) - -/* RISC-V memory prefetch macros */ -#define PREFETCH_READ(addr) asm volatile ("prefetch.r %0" : : "r"(addr) : "memory") -#define PREFETCH_WRITE(addr) asm volatile ("prefetch.w %0" : : "r"(addr) : "memory") -#define MEMORY_BARRIER() asm volatile ("fence rw,rw" : : : "memory") -#define READ_BARRIER() asm volatile ("fence r,r" : : : "memory") -#define WRITE_BARRIER() asm volatile ("fence w,w" : : : "memory") - -/* RISC-V hint pause - tries Zihintpause, falls back to NOP */ -static inline void cpu_pause(void) -{ - asm volatile ("pause"); -} - -/* Adaptive thread count calculation for dataset init */ -static inline uint32_t riscv_optimal_init_threads(uint32_t available_threads) -{ - /* On RISC-V, use 60-75% of available threads for init */ - /* This leaves some threads available for OS/other tasks */ - uint32_t recommended = (available_threads * 3) / 4; - return recommended > 0 ? recommended : 1; -} - -/* Prefetch next dataset item for better cache utilization */ -static inline void prefetch_dataset_item(const void *item, size_t size) -{ - const uint8_t *ptr = (const uint8_t *)item; - /* Prefetch cache line aligned chunks */ - for (size_t i = 0; i < size; i += 64) { - PREFETCH_READ(ptr + i); - } -} - -/* Cache-aware aligned memory copy optimized for RISC-V */ -static inline void aligned_memcpy_opt(void *dst, const void *src, size_t size) -{ - uint64_t *d = (uint64_t *)dst; - const uint64_t *s = (const uint64_t *)src; - - /* Process in 64-byte chunks with prefetching */ - size_t chunks = size / 8; - for (size_t i = 0; i < chunks; i += 8) { - if (i + 8 < chunks) { - prefetch_dataset_item(s + i + 8, 64); - } - d[i] = s[i]; - d[i+1] = s[i+1]; - d[i+2] = s[i+2]; - d[i+3] = s[i+3]; - d[i+4] = s[i+4]; - d[i+5] = s[i+5]; - d[i+6] = s[i+6]; - d[i+7] = s[i+7]; - } -} - -/* Get optimal CPU core for thread pinning */ -static inline int get_optimal_cpu_core(int thread_id) -{ - long nprocs = sysconf(_SC_NPROCESSORS_ONLN); - if (nprocs <= 0) nprocs = 1; - return thread_id % nprocs; -} - -#else /* !XMRIG_RISCV */ - -/* Fallback for non-RISC-V architectures */ -#define PREFETCH_READ(addr) -#define PREFETCH_WRITE(addr) -#define MEMORY_BARRIER() __sync_synchronize() -#define READ_BARRIER() __sync_synchronize() -#define WRITE_BARRIER() __sync_synchronize() - -static inline void cpu_pause(void) { } -static inline uint32_t riscv_optimal_init_threads(uint32_t available) { return available; } -static inline void prefetch_dataset_item(const void *item, size_t size) { (void)item; (void)size; } -static inline void aligned_memcpy_opt(void *dst, const void *src, size_t size) { memcpy(dst, src, size); } -static inline int get_optimal_cpu_core(int thread_id) { return thread_id; } - -#endif - -#ifdef __cplusplus -} -#endif - -#endif // XMRIG_RXDATASET_RISCV_H