v6.3.0

Merge branch 'dev'
v6.3.0-dev
2025-12-08 08:23:34 -05:00 · 2020-07-17 00:17:55 +07:00 · 2020-07-17 00:17:24 +07:00 · 2020-07-17 00:04:31 +07:00 · 2020-07-16 23:29:21 +07:00 · 2020-07-16 19:56:20 +07:00
47 changed files with 9615 additions and 6613 deletions
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,4 +1,24 @@
+# v6.3.0
+- [#1771](https://github.com/xmrig/xmrig/pull/1771) Adopted new SSE2NEON and reduced ARM-specific changes.
+- [#1774](https://github.com/xmrig/xmrig/pull/1774) RandomX: Added new option `cache_qos` in `randomx` object for cache QoS support.
+- [#1777](https://github.com/xmrig/xmrig/pull/1777) Added support for upcoming Haven offshore fork.
+  - [#1780](https://github.com/xmrig/xmrig/pull/1780) CryptoNight OpenCL: fix for long input data.
+
+# v6.2.3
+- [#1745](https://github.com/xmrig/xmrig/pull/1745) AstroBWT: fixed OpenCL compilation on some systems.
+- [#1749](https://github.com/xmrig/xmrig/pull/1749) KawPow: optimized CPU share verification.
+- [#1752](https://github.com/xmrig/xmrig/pull/1752) RandomX: added error message when MSR mod fails.
+- [#1754](https://github.com/xmrig/xmrig/issues/1754) Fixed GPU health readings for pre Vega GPUs on Linux.
+- [#1756](https://github.com/xmrig/xmrig/issues/1756) Added results and connection reports.
+- [#1759](https://github.com/xmrig/xmrig/pull/1759) KawPow: fixed DAG initialization on slower AMD GPUs.
+- [#1763](https://github.com/xmrig/xmrig/pull/1763) KawPow: fixed rare duplicate share errors.
+- [#1766](https://github.com/xmrig/xmrig/pull/1766) RandomX: small speedup on Ryzen CPUs.
+
+# v6.2.2
+- [#1742](https://github.com/xmrig/xmrig/issues/1742) Fixed crash when use HTTP API.
+
 # v6.2.1
+- [#1726](https://github.com/xmrig/xmrig/issues/1726) Fixed detection of AVX2/AVX512.
 - [#1728](https://github.com/xmrig/xmrig/issues/1728) Fixed, 32 bit Windows builds was crash on start.
 - [#1729](https://github.com/xmrig/xmrig/pull/1729) Fixed KawPow crash on old CPUs.
 - [#1730](https://github.com/xmrig/xmrig/pull/1730) Improved displaying information for compute errors on GPUs.
--- a/src/3rdparty/libethash/ethash_internal.c
+++ b/src/3rdparty/libethash/ethash_internal.c
@@ -33,6 +33,18 @@
 #include "data_sizes.h"
 #include "base/crypto/sha3.h"

+#if defined(_M_X64) || defined(__x86_64__) || defined(__SSE2__)
+	#ifdef __GNUC__
+		#include <x86intrin.h>
+	#else
+		#include <intrin.h>
+	#endif
+
+	#define kp_prefetch(x) _mm_prefetch((x), _MM_HINT_T0);
+#else
+	#define kp_prefetch(x)
+#endif
+
 #define SHA3_256(a, b, c) sha3_HashBuffer(256, SHA3_FLAGS_KECCAK, b, c, a, 32)
 #define SHA3_512(a, b, c) sha3_HashBuffer(512, SHA3_FLAGS_KECCAK, b, c, a, 64)

@@ -157,46 +169,53 @@ void ethash_calculate_dag_item_opt(
 	memcpy(ret, init, sizeof(node));
 	ret->words[0] ^= node_index;
 	SHA3_512(ret->bytes, ret->bytes, sizeof(node));
-#if defined(_M_X64) && ENABLE_SSE
-	__m128i const fnv_prime = _mm_set1_epi32(FNV_PRIME);
-	__m128i xmm0 = ret->xmm[0];
-	__m128i xmm1 = ret->xmm[1];
-	__m128i xmm2 = ret->xmm[2];
-	__m128i xmm3 = ret->xmm[3];
-#endif

 	for (uint32_t i = 0; i != num_parents; ++i) {
 		uint32_t parent_index = fast_mod(fnv_hash(node_index ^ i, ret->words[i % NODE_WORDS]), light->num_parent_nodes, light->reciprocal, light->increment, light->shift);
 		node const* parent = &cache_nodes[parent_index];
-
-#if defined(_M_X64) && ENABLE_SSE
-		{
-			xmm0 = _mm_mullo_epi32(xmm0, fnv_prime);
-			xmm1 = _mm_mullo_epi32(xmm1, fnv_prime);
-			xmm2 = _mm_mullo_epi32(xmm2, fnv_prime);
-			xmm3 = _mm_mullo_epi32(xmm3, fnv_prime);
-			xmm0 = _mm_xor_si128(xmm0, parent->xmm[0]);
-			xmm1 = _mm_xor_si128(xmm1, parent->xmm[1]);
-			xmm2 = _mm_xor_si128(xmm2, parent->xmm[2]);
-			xmm3 = _mm_xor_si128(xmm3, parent->xmm[3]);
-
-			// have to write to ret as values are used to compute index
-			ret->xmm[0] = xmm0;
-			ret->xmm[1] = xmm1;
-			ret->xmm[2] = xmm2;
-			ret->xmm[3] = xmm3;
+		for (unsigned w = 0; w != NODE_WORDS; ++w) {
+			ret->words[w] = fnv_hash(ret->words[w], parent->words[w]);
 		}
-#else
-		{
-			for (unsigned w = 0; w != NODE_WORDS; ++w) {
-				ret->words[w] = fnv_hash(ret->words[w], parent->words[w]);
-			}
-		}
-#endif
 	}
 	SHA3_512(ret->bytes, ret->bytes, sizeof(node));
 }

+void ethash_calculate_dag_item4_opt(
+	node* ret,
+	uint32_t node_index,
+	uint32_t num_parents,
+	ethash_light_t const light
+)
+{
+	node const* cache_nodes = (node const*)light->cache;
+
+	for (size_t i = 0; i < 4; ++i) {
+		node const* init = &cache_nodes[fast_mod(node_index + i, light->num_parent_nodes, light->reciprocal, light->increment, light->shift)];
+		memcpy(ret + i, init, sizeof(node));
+		ret[i].words[0] ^= node_index + i;
+		SHA3_512(ret[i].bytes, ret[i].bytes, sizeof(node));
+	}
+
+	for (uint32_t i = 0; i != num_parents; ++i) {
+		node const* parent[4];
+
+		for (uint32_t j = 0; j < 4; ++j) {
+			const uint32_t parent_index = fast_mod(fnv_hash((node_index + j) ^ i, ret[j].words[i % NODE_WORDS]), light->num_parent_nodes, light->reciprocal, light->increment, light->shift);
+			parent[j] = &cache_nodes[parent_index];
+			kp_prefetch(parent[j]);
+		}
+
+		for (unsigned w = 0; w != NODE_WORDS; ++w) ret[0].words[w] = fnv_hash(ret[0].words[w], parent[0]->words[w]);
+		for (unsigned w = 0; w != NODE_WORDS; ++w) ret[1].words[w] = fnv_hash(ret[1].words[w], parent[1]->words[w]);
+		for (unsigned w = 0; w != NODE_WORDS; ++w) ret[2].words[w] = fnv_hash(ret[2].words[w], parent[2]->words[w]);
+		for (unsigned w = 0; w != NODE_WORDS; ++w) ret[3].words[w] = fnv_hash(ret[3].words[w], parent[3]->words[w]);
+	}
+
+	for (size_t i = 0; i < 4; ++i) {
+		SHA3_512(ret[i].bytes, ret[i].bytes, sizeof(node));
+	}
+}
+
 bool ethash_compute_full_data(
 	void* mem,
 	uint64_t full_size,
--- a/src/3rdparty/libethash/ethash_internal.h
+++ b/src/3rdparty/libethash/ethash_internal.h
@@ -161,6 +161,13 @@ void ethash_calculate_dag_item_opt(
 	ethash_light_t const cache
 );

+void ethash_calculate_dag_item4_opt(
+	node* ret,
+	uint32_t node_index,
+	uint32_t num_parents,
+	ethash_light_t const cache
+);
+
 void ethash_quick_hash(
 	ethash_h256_t* return_hash,
 	ethash_h256_t const* header_hash,
--- a/src/App.cpp
+++ b/src/App.cpp
@@ -37,8 +37,6 @@
 #include "base/kernel/Platform.h"
 #include "core/config/Config.h"
 #include "core/Controller.h"
-#include "core/Miner.h"
-#include "net/Network.h"
 #include "Summary.h"
 #include "version.h"

@@ -107,7 +105,7 @@ void xmrig::App::onConsoleCommand(char command)
        close();
    }
    else {
-        m_controller->miner()->execCommand(command);
+        m_controller->execCommand(command);
    }
 }

--- a/src/Summary.cpp
+++ b/src/Summary.cpp
@@ -161,11 +161,14 @@ static void print_commands(Config *)
 {
    if (Log::isColors()) {
        Log::print(GREEN_BOLD(" * ") WHITE_BOLD("COMMANDS     ") MAGENTA_BG(WHITE_BOLD_S "h") WHITE_BOLD("ashrate, ")
-                                                                     MAGENTA_BG(WHITE_BOLD_S "p") WHITE_BOLD("ause, ")
-                                                                     MAGENTA_BG(WHITE_BOLD_S "r") WHITE_BOLD("esume"));
+                                                                 MAGENTA_BG(WHITE_BOLD_S "p") WHITE_BOLD("ause, ")
+                                                                 MAGENTA_BG(WHITE_BOLD_S "r") WHITE_BOLD("esume, ")
+                                                                 WHITE_BOLD("re") MAGENTA_BG(WHITE_BOLD_S "s") WHITE_BOLD("ults, ")
+                                                                 MAGENTA_BG(WHITE_BOLD_S "c") WHITE_BOLD("onnection")
+                   );
    }
    else {
-        Log::print(" * COMMANDS     'h' hashrate, 'p' pause, 'r' resume");
+        Log::print(" * COMMANDS     'h' hashrate, 'p' pause, 'r' resume, 's' results, 'c' connection");
    }
 }

--- a/src/backend/common/WorkerJob.h
+++ b/src/backend/common/WorkerJob.h
@@ -139,11 +139,24 @@ inline bool xmrig::WorkerJob<1>::nextRound(uint32_t rounds, uint32_t roundSize)
    }

    // Increment higher 32 bits of a 64-bit nonce when lower 32 bits overflow
-    if (!currentJob().isNicehash() && (nonceSize() == sizeof(uint64_t)) && (*n < prev_nonce)) {
-        ++n[1];
+    if (!currentJob().isNicehash() && (nonceSize() == sizeof(uint64_t))) {
+        const bool wrapped = (*n < prev_nonce);
+        const bool wraps_this_round = (static_cast<uint64_t>(*n) + roundSize > (1ULL << 32));

-        Job& job = m_jobs[index()];
-        memcpy(job.blob(), blob(), job.size());
+        // Account for the case when starting nonce hasn't wrapped yet, but some nonces in the current round will wrap
+        if (wrapped || wraps_this_round) {
+            // Set lower 32 bits to 0 when higher 32 bits change
+            Nonce::reset(index());
+
+            // Sets *n to 0 and Nonce::m_nonce[index] to the correct next value
+            *n = 0;
+            Nonce::next(index(), *n, rounds * roundSize, currentJob().isNicehash(), &ok);
+
+            ++n[1];
+
+            Job& job = m_jobs[index()];
+            memcpy(job.blob(), blob(), job.size());
+        }
    }

    return ok;
--- a/src/backend/cpu/interfaces/ICpuInfo.h
+++ b/src/backend/cpu/interfaces/ICpuInfo.h
@@ -62,6 +62,7 @@ public:
        FLAG_SSSE3,
        FLAG_XOP,
        FLAG_POPCNT,
+        FLAG_CAT_L3,
        FLAG_MAX
    };

@@ -79,6 +80,7 @@ public:
    virtual bool hasAVX2() const                                                    = 0;
    virtual bool hasBMI2() const                                                    = 0;
    virtual bool hasOneGbPages() const                                              = 0;
+    virtual bool hasCatL3() const                                                   = 0;
    virtual const char *backend() const                                             = 0;
    virtual const char *brand() const                                               = 0;
    virtual CpuThreads threads(const Algorithm &algorithm, uint32_t limit) const    = 0;
--- a/src/backend/cpu/platform/BasicCpuInfo.cpp
+++ b/src/backend/cpu/platform/BasicCpuInfo.cpp
@@ -57,7 +57,7 @@
 namespace xmrig {


-static const std::array<const char *, ICpuInfo::FLAG_MAX> flagNames     = { "aes", "avx2", "avx512f", "bmi2", "osxsave", "pdpe1gb", "sse2", "ssse3", "xop" };
+static const std::array<const char *, ICpuInfo::FLAG_MAX> flagNames     = { "aes", "avx2", "avx512f", "bmi2", "osxsave", "pdpe1gb", "sse2", "ssse3", "xop", "popcnt", "cat_l3" };
 static const std::array<const char *, ICpuInfo::MSR_MOD_MAX> msrNames   = { "none", "ryzen", "intel", "custom" };


@@ -66,7 +66,7 @@ static inline void cpuid(uint32_t level, int32_t output[4])
    memset(output, 0, sizeof(int32_t) * 4);

 #   ifdef _MSC_VER
-    __cpuid(output, static_cast<int>(level));
+    __cpuidex(output, static_cast<int>(level), 0);
 #   else
    __cpuid_count(level, 0, output[0], output[1], output[2], output[3]);
 #   endif
@@ -143,6 +143,7 @@ static inline bool has_sse2()       { return has_feature(PROCESSOR_INFO,
 static inline bool has_ssse3()      { return has_feature(PROCESSOR_INFO,        ECX_Reg, 1 << 9); }
 static inline bool has_xop()        { return has_feature(0x80000001,            ECX_Reg, 1 << 11); }
 static inline bool has_popcnt()     { return has_feature(PROCESSOR_INFO,        ECX_Reg, 1 << 23); }
+static inline bool has_cat_l3()     { return has_feature(EXTENDED_FEATURES,     EBX_Reg, 1 << 15) && has_feature(0x10, EBX_Reg, 1 << 1); }


 } // namespace xmrig
@@ -178,6 +179,7 @@ xmrig::BasicCpuInfo::BasicCpuInfo() :
    m_flags.set(FLAG_SSSE3,   has_ssse3());
    m_flags.set(FLAG_XOP,     has_xop());
    m_flags.set(FLAG_POPCNT,  has_popcnt());
+    m_flags.set(FLAG_CAT_L3,  has_cat_l3());

 #   ifdef XMRIG_FEATURE_ASM
    if (hasAES()) {
--- a/src/backend/cpu/platform/BasicCpuInfo.h
+++ b/src/backend/cpu/platform/BasicCpuInfo.h
@@ -51,6 +51,7 @@ protected:
    inline bool hasAVX2() const override            { return has(FLAG_AVX2); }
    inline bool hasBMI2() const override            { return has(FLAG_BMI2); }
    inline bool hasOneGbPages() const override      { return has(FLAG_PDPE1GB); }
+    inline bool hasCatL3() const override           { return has(FLAG_CAT_L3); }
    inline const char *brand() const override       { return m_brand; }
    inline MsrMod msrMod() const override           { return m_msrMod; }
    inline size_t cores() const override            { return 0; }
--- a/src/backend/opencl/cl/astrobwt/BWT.cl
+++ b/src/backend/opencl/cl/astrobwt/BWT.cl
@@ -163,7 +163,7 @@ __kernel void filter(uint32_t nonce, uint32_t bwt_max_size, __global const uint3

 		filtered_hashes[index] = nonce + global_id;

-		#pragma unroll(8)
+		#pragma unroll 8
 		for (uint32_t i = 0; i < 8; ++i)
 			filtered_hashes[index + i + 1] = hash[i];
 	}
@@ -183,7 +183,7 @@ __kernel void prepare_batch2(__global uint32_t* hashes, __global uint32_t* filte
 	const uint32_t stage2_size = STAGE1_SIZE + (filtered_hash[1] & 0xfffff);
 	data_sizes[global_id] = stage2_size;

-	#pragma unroll(8)
+	#pragma unroll 8
 	for (uint32_t i = 0; i < 8; ++i)
 		hash[i] = filtered_hash[i + 1];
 }
--- a/src/backend/opencl/cl/astrobwt/astrobwt_cl.h
+++ b/src/backend/opencl/cl/astrobwt/astrobwt_cl.h
@@ -2,7 +2,7 @@

 namespace xmrig {

-static const char astrobwt_cl[12440] = {
+static const char astrobwt_cl[12434] = {
    0x74,0x79,0x70,0x65,0x64,0x65,0x66,0x20,0x75,0x63,0x68,0x61,0x72,0x20,0x75,0x69,0x6e,0x74,0x38,0x5f,0x74,0x3b,0x0a,0x74,0x79,0x70,0x65,0x64,0x65,0x66,0x20,0x75,
    0x73,0x68,0x6f,0x72,0x74,0x20,0x75,0x69,0x6e,0x74,0x31,0x36,0x5f,0x74,0x3b,0x0a,0x74,0x79,0x70,0x65,0x64,0x65,0x66,0x20,0x75,0x69,0x6e,0x74,0x20,0x75,0x69,0x6e,
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@@ -119,279 +119,279 @@ static const char astrobwt_cl[12440] = {
    0x66,0x69,0x6c,0x74,0x65,0x72,0x65,0x64,0x5f,0x68,0x61,0x73,0x68,0x65,0x73,0x29,0x2c,0x31,0x29,0x2a,0x28,0x33,0x36,0x2f,0x73,0x69,0x7a,0x65,0x6f,0x66,0x28,0x75,
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 };

 } // namespace xmrig
--- a/src/backend/opencl/cl/astrobwt/salsa20.cl
+++ b/src/backend/opencl/cl/astrobwt/salsa20.cl
@@ -82,7 +82,7 @@ __kernel void Salsa20_XORKeyStream(__global const uint32_t* keys, __global uint3
 		uint32_t x14 = j14;
 		uint32_t x15 = j15;

-		#pragma unroll(5)
+		#pragma unroll 5
 		for (uint32_t j = 0; j < 10; ++j)
 		{
 			x4  = XOR( x4,ROTATE(PLUS( x0,x12), 7));
--- a/src/backend/opencl/cl/astrobwt/sha3.cl
+++ b/src/backend/opencl/cl/astrobwt/sha3.cl
@@ -111,7 +111,7 @@ __kernel void sha3(__global const uint8_t* inputs, __global const uint32_t* inpu
 		++wordIndex;
 		if (wordIndex == 17)
 		{
-			#pragma unroll(ROUNDS)
+			#pragma unroll ROUNDS
 			for (int i = 0; i < ROUNDS; ++i)
 			{
 				C[t] = A[s] ^ A[s+5] ^ A[s+10] ^ A[s+15] ^ A[s+20];
@@ -133,7 +133,7 @@ __kernel void sha3(__global const uint8_t* inputs, __global const uint32_t* inpu
 	A[wordIndex] ^= tail ^ ((uint64_t)(((uint64_t)(0x02 | (1 << 2))) << (tail_size * 8)));
 	A[16] ^= 0x8000000000000000UL;

-	#pragma unroll(1)
+	#pragma unroll 1
 	for (int i = 0; i < ROUNDS; ++i)
 	{
 		C[t] = A[s] ^ A[s+5] ^ A[s+10] ^ A[s+15] ^ A[s+20];
@@ -180,7 +180,7 @@ __kernel void sha3_initial(__global const uint8_t* input_data, uint32_t input_si
 	A[wordIndex] ^= (uint64_t)(((uint64_t)(0x02 | (1 << 2))) << (tail_size * 8));
 	A[16] ^= 0x8000000000000000UL;

-	#pragma unroll(ROUNDS)
+	#pragma unroll ROUNDS
 	for (int i = 0; i < ROUNDS; ++i)
 	{
 		C[t] = A[s] ^ A[s+5] ^ A[s+10] ^ A[s+15] ^ A[s+20];
--- a/src/backend/opencl/cl/cn/cryptonight.cl
+++ b/src/backend/opencl/cl/cn/cryptonight.cl
@@ -71,7 +71,7 @@ inline ulong getIdx()


 __attribute__((reqd_work_group_size(8, 8, 1)))
-__kernel void cn0(__global ulong *input, __global uint4 *Scratchpad, __global ulong *states, uint Threads)
+__kernel void cn0(__global ulong *input, int inlen, __global uint4 *Scratchpad, __global ulong *states, uint Threads)
 {
    uint ExpandedKey1[40];
    __local uint AES0[256], AES1[256], AES2[256], AES3[256];
@@ -109,34 +109,25 @@ __kernel void cn0(__global ulong *input, __global uint4 *Scratchpad, __global ul
        if (get_local_id(1) == 0) {
            __local ulong* State = State_buf + get_local_id(0) * 25;

-            ((__local ulong8 *)State)[0] = vload8(0, input);
-            State[8]  = input[8];
-            State[9]  = input[9];
-            State[10] = input[10];
-            State[11] = input[11];
-            State[12] = input[12];
-            State[13] = input[13];
-            State[14] = input[14];
-            State[15] = input[15];
-
-            ((__local uint *)State)[9]  &= 0x00FFFFFFU;
-            ((__local uint *)State)[9]  |= (((uint)get_global_id(0)) & 0xFF) << 24;
-            ((__local uint *)State)[10] &= 0xFF000000U;
-            /* explicit cast to `uint` is required because some OpenCL implementations (e.g. NVIDIA)
-             * handle get_global_id and get_global_offset as signed long long int and add
-             * 0xFFFFFFFF... to `get_global_id` if we set on host side a 32bit offset where the first bit is `1`
-             * (even if it is correct casted to unsigned on the host)
-             */
-            ((__local uint *)State)[10] |= (((uint)get_global_id(0) >> 8));
-
-            // Last bit of padding
-            State[16] = 0x8000000000000000UL;
-
-            for (int i = 17; i < 25; ++i) {
-                State[i] = 0x00UL;
+            #pragma unroll
+            for (int i = 0; i < 25; ++i) {
+                State[i] = 0;
            }

-            keccakf1600_2(State);
+            // Input length must be a multiple of 136 and padded on the host side
+            for (int i = 0; inlen > 0; i += 17, inlen -= 136) {
+                #pragma unroll
+                for (int j = 0; j < 17; ++j) {
+                    State[j] ^= input[i + j];
+                }
+                if (i == 0) {
+                    ((__local uint *)State)[9]  &= 0x00FFFFFFU;
+                    ((__local uint *)State)[9]  |= (((uint)get_global_id(0)) & 0xFF) << 24;
+                    ((__local uint *)State)[10] &= 0xFF000000U;
+                    ((__local uint *)State)[10] |= (((uint)get_global_id(0) >> 8));
+                }
+                keccakf1600_2(State);
+            }

            #pragma unroll 1
            for (int i = 0; i < 25; ++i) {
--- a/src/backend/opencl/cl/cn/cryptonight_cl.h
+++ b/src/backend/opencl/cl/cn/cryptonight_cl.h
--- a/src/backend/opencl/cl/rx/randomx_cl.h
+++ b/src/backend/opencl/cl/rx/randomx_cl.h
--- a/src/backend/opencl/kernels/Cn0Kernel.cpp
+++ b/src/backend/opencl/kernels/Cn0Kernel.cpp
@@ -38,10 +38,11 @@ void xmrig::Cn0Kernel::enqueue(cl_command_queue queue, uint32_t nonce, size_t th


 // __kernel void cn0(__global ulong *input, __global uint4 *Scratchpad, __global ulong *states, uint Threads)
-void xmrig::Cn0Kernel::setArgs(cl_mem input, cl_mem scratchpads, cl_mem states, uint32_t threads)
+void xmrig::Cn0Kernel::setArgs(cl_mem input, int inlen, cl_mem scratchpads, cl_mem states, uint32_t threads)
 {
    setArg(0, sizeof(cl_mem), &input);
-    setArg(1, sizeof(cl_mem), &scratchpads);
-    setArg(2, sizeof(cl_mem), &states);
-    setArg(3, sizeof(uint32_t), &threads);
+    setArg(1, sizeof(int), &inlen);
+    setArg(2, sizeof(cl_mem), &scratchpads);
+    setArg(3, sizeof(cl_mem), &states);
+    setArg(4, sizeof(uint32_t), &threads);
 }
--- a/src/backend/opencl/kernels/Cn0Kernel.h
+++ b/src/backend/opencl/kernels/Cn0Kernel.h
@@ -38,7 +38,7 @@ public:
    inline Cn0Kernel(cl_program program) : OclKernel(program, "cn0") {}

    void enqueue(cl_command_queue queue, uint32_t nonce, size_t threads);
-    void setArgs(cl_mem input, cl_mem scratchpads, cl_mem states, uint32_t threads);
+    void setArgs(cl_mem input, int inlen, cl_mem scratchpads, cl_mem states, uint32_t threads);
 };


--- a/src/backend/opencl/runners/OclCnRunner.cpp
+++ b/src/backend/opencl/runners/OclCnRunner.cpp
@@ -122,10 +122,16 @@ void xmrig::OclCnRunner::set(const Job &job, uint8_t *blob)
        throw std::length_error("job size too big");
    }

-    blob[job.size()] = 0x01;
-    memset(blob + job.size() + 1, 0, Job::kMaxBlobSize - job.size() - 1);
+    const int inlen = static_cast<int>(job.size() + 136 - (job.size() % 136));

-    enqueueWriteBuffer(m_input, CL_TRUE, 0, Job::kMaxBlobSize, blob);
+    blob[job.size()] = 0x01;
+    memset(blob + job.size() + 1, 0, inlen - job.size() - 1);
+
+    blob[inlen - 1] |= 0x80;
+
+    enqueueWriteBuffer(m_input, CL_TRUE, 0, inlen, blob);
+
+    m_cn0->setArg(1, sizeof(int), &inlen);

    if (m_algorithm == Algorithm::CN_R && m_height != job.height()) {
        delete m_cn1;
@@ -152,7 +158,7 @@ void xmrig::OclCnRunner::build()
    OclBaseRunner::build();

    m_cn0 = new Cn0Kernel(m_program);
-    m_cn0->setArgs(m_input, m_scratchpads, m_states, m_intensity);
+    m_cn0->setArgs(m_input, 0, m_scratchpads, m_states, m_intensity);

    m_cn2 = new Cn2Kernel(m_program);
    m_cn2->setArgs(m_scratchpads, m_states, m_branches, m_intensity);
--- a/src/backend/opencl/runners/OclKawPowRunner.cpp
+++ b/src/backend/opencl/runners/OclKawPowRunner.cpp
@@ -157,7 +157,7 @@ void OclKawPowRunner::set(const Job &job, uint8_t *blob)
        const uint32_t dag_words = dag_size / sizeof(node);
        m_calculateDagKernel->setArgs(0, m_lightCache, m_dag, dag_words, m_lightCacheSize / sizeof(node));

-        constexpr uint32_t N = 1 << 20;
+        constexpr uint32_t N = 1 << 18;

        for (uint32_t start = 0; start < dag_words; start += N) {
            m_calculateDagKernel->setArg(0, sizeof(start), &start);
--- a/src/backend/opencl/wrappers/AdlLib_linux.cpp
+++ b/src/backend/opencl/wrappers/AdlLib_linux.cpp
@@ -1,6 +1,7 @@
 /* XMRig
 * Copyright 2008-2018 Advanced Micro Devices, Inc.
 * Copyright 2018-2020 SChernykh                    <https://github.com/SChernykh>
+ * Copyright 2020      Patrick Bollinger            <https://github.com/pjbollinger>
 * Copyright 2016-2020 XMRig                        <https://github.com/xmrig>, <support@xmrig.com>
 *
 *   This program is free software: you can redistribute it and/or modify
@@ -82,7 +83,7 @@ static inline std::string sysfs_prefix(const PciTopology &topology)

    for (uint32_t i = 1; i < 10; ++i) {
        const std::string prefix = path + std::to_string(i) + "/";
-        if (sysfs_is_amdgpu(prefix + "name") && sysfs_read(prefix + "freq1_input")) {
+        if (sysfs_is_amdgpu(prefix + "name") && (sysfs_read(prefix + "temp1_input") || sysfs_read(prefix + "power1_average"))) {
            return prefix;
        }
    }
@@ -116,6 +117,7 @@ void xmrig::AdlLib::close()
 }


+// https://dri.freedesktop.org/docs/drm/gpu/amdgpu.html#gpu-power-thermal-controls-and-monitoring
 AdlHealth xmrig::AdlLib::health(const OclDevice &device)
 {
    if (!isReady() || device.vendorId() != OCL_VENDOR_AMD) {
@@ -134,6 +136,10 @@ AdlHealth xmrig::AdlLib::health(const OclDevice &device)
    health.rpm          = sysfs_read(prefix + "fan1_input");
    health.temperature  = sysfs_read(prefix + "temp2_input") / 1000;

+    if (!health.temperature) {
+        health.temperature = sysfs_read(prefix + "temp1_input") / 1000;
+    }
+
    return health;
 }

--- a/src/base/io/json/JsonChain.cpp
+++ b/src/base/io/json/JsonChain.cpp
@@ -36,9 +36,7 @@ static const rapidjson::Value kNullValue;
 }


-xmrig::JsonChain::JsonChain()
-{
-}
+xmrig::JsonChain::JsonChain() = default;


 bool xmrig::JsonChain::add(rapidjson::Document &&doc)
@@ -66,8 +64,10 @@ bool xmrig::JsonChain::addFile(const char *fileName)
    if (doc.HasParseError()) {
        const size_t offset = doc.GetErrorOffset();

-        size_t line, pos;
+        size_t line;
+        size_t pos;
        std::vector<std::string> s;
+
        if (Json::convertOffset(fileName, offset, line, pos, s)) {
            for (const auto& t : s) {
                LOG_ERR("%s", t.c_str());
--- a/src/base/io/log/Tags.cpp
+++ b/src/base/io/log/Tags.cpp
@@ -73,6 +73,16 @@ const char *xmrig::Tags::randomx()
 #endif


+#ifdef XMRIG_PROXY_PROJECT
+const char *xmrig::Tags::proxy()
+{
+    static const char *tag = MAGENTA_BG_BOLD(WHITE_BOLD_S " proxy   ");
+
+    return tag;
+}
+#endif
+
+
 #ifdef XMRIG_FEATURE_CUDA
 const char *xmrig::Tags::nvidia()
 {
--- a/src/base/io/log/Tags.h
+++ b/src/base/io/log/Tags.h
@@ -42,6 +42,10 @@ public:
 #   endif
 #   endif

+#   ifdef XMRIG_PROXY_PROJECT
+    static const char *proxy();
+#   endif
+
 #   ifdef XMRIG_FEATURE_CUDA
    static const char *nvidia();
 #   endif
--- a/src/base/net/stratum/Job.h
+++ b/src/base/net/stratum/Job.h
@@ -45,7 +45,9 @@ class Job
 public:
    // Max blob size is 84 (75 fixed + 9 variable), aligned to 96. https://github.com/xmrig/xmrig/issues/1 Thanks fireice-uk.
    // SECOR increase requirements for blob size: https://github.com/xmrig/xmrig/issues/913
-    static constexpr const size_t kMaxBlobSize = 128;
+    // Haven (XHV) offshore increases requirements by adding pricing_record struct (192 bytes) to block_header.
+    // Round it up to 408 (136*3) for a convenient keccak calculation in OpenCL
+    static constexpr const size_t kMaxBlobSize = 408;
    static constexpr const size_t kMaxSeedSize = 32;

    Job() = default;
--- a/src/base/net/stratum/NetworkState.cpp
+++ b/src/base/net/stratum/NetworkState.cpp
@@ -25,6 +25,7 @@

 #include "base/net/stratum/NetworkState.h"
 #include "3rdparty/rapidjson/document.h"
+#include "base/io/log/Log.h"
 #include "base/kernel/interfaces/IClient.h"
 #include "base/kernel/interfaces/IStrategy.h"
 #include "base/net/stratum/Job.h"
@@ -40,6 +41,80 @@



+namespace xmrig {
+
+
+inline static void printCount(uint64_t accepted, uint64_t rejected)
+{
+    float percent   = 100.0;
+    int color       = 2;
+
+    if (!accepted) {
+        percent     = 0.0;
+        color       = 1;
+    }
+    else if (rejected) {
+        percent     = static_cast<float>(accepted) / (accepted + rejected) * 100.0;
+        color       = 3;
+    }
+
+    Log::print(GREEN_BOLD(" * ") WHITE_BOLD("%-17s") CSI "1;3%dm%" PRIu64 CLEAR CSI "0;3%dm (%1.1f%%)", "accepted", color, accepted, color, percent);
+
+    if (rejected) {
+        Log::print(GREEN_BOLD(" * ") WHITE_BOLD("%-17s") RED_BOLD("%" PRIu64), "rejected", rejected);
+    }
+}
+
+
+inline static void printHashes(uint64_t accepted, uint64_t hashes)
+{
+    Log::print(GREEN_BOLD(" * ") WHITE_BOLD("%-17s") CYAN_BOLD("%" PRIu64) " avg " CYAN("%1.0f"),
+               "pool-side hashes", hashes, static_cast<double>(hashes) / accepted);
+}
+
+
+inline static void printAvgTime(uint64_t time)
+{
+    Log::print(GREEN_BOLD(" * ") WHITE_BOLD("%-17s") CSI "1;3%dm%1.1fs", "avg result time", (time < 10000 ? 3 : 2), time / 1000.0);
+}
+
+
+static void printDiff(uint64_t diff)
+{
+    Log::print(GREEN_BOLD(" * ") WHITE_BOLD("%-17s") CYAN_BOLD("%s"), "difficulty", NetworkState::humanDiff(diff).c_str());
+}
+
+
+inline static void printDiff(size_t i, uint64_t diff, uint64_t hashes)
+{
+    if (!diff) {
+        return;
+    }
+
+    const double effort = static_cast<double>(hashes) / diff * 100.0;
+    const double target = (i + 1) * 100.0;
+    const int color     = effort > (target + 100.0) ? 1 : (effort > target ? 3 : 2);
+
+    Log::print("%3zu | %10s | " CSI "0;3%dm%8.2f" CLEAR " |", i + 1, NetworkState::humanDiff(diff).c_str(), color, effort);
+}
+
+
+inline static void printLatency(uint32_t latency)
+{
+    if (!latency) {
+        return;
+    }
+
+    const int color = latency < 100 ? 2 : (latency > 500 ? 1 : 3);
+
+    Log::print(GREEN_BOLD(" * ") WHITE_BOLD("%-17s") CSI "1;3%dm%ums", "ping time", color, latency);
+}
+
+
+} // namespace xmrig
+
+
+
 xmrig::NetworkState::NetworkState(IStrategyListener *listener) : StrategyProxy(listener)
 {
 }
@@ -54,7 +129,8 @@ rapidjson::Value xmrig::NetworkState::getConnection(rapidjson::Document &doc, in
    Value connection(kObjectType);
    connection.AddMember("pool",            StringRef(m_pool), allocator);
    connection.AddMember("ip",              m_ip.toJSON(), allocator);
-    connection.AddMember("uptime",          connectionTime(), allocator);
+    connection.AddMember("uptime",          connectionTime() / 1000, allocator);
+    connection.AddMember("uptime_ms",       connectionTime(), allocator);
    connection.AddMember("ping",            latency(), allocator);
    connection.AddMember("failures",        m_failures, allocator);
    connection.AddMember("tls",             m_tls.toJSON(), allocator);
@@ -64,7 +140,8 @@ rapidjson::Value xmrig::NetworkState::getConnection(rapidjson::Document &doc, in
    connection.AddMember("diff",            m_diff, allocator);
    connection.AddMember("accepted",        m_accepted, allocator);
    connection.AddMember("rejected",        m_rejected, allocator);
-    connection.AddMember("avg_time",        avgTime(), allocator);
+    connection.AddMember("avg_time",        avgTime() / 1000, allocator);
+    connection.AddMember("avg_time_ms",     avgTime(), allocator);
    connection.AddMember("hashes_total",    m_hashes, allocator);

    if (version == 1) {
@@ -85,11 +162,14 @@ rapidjson::Value xmrig::NetworkState::getResults(rapidjson::Document &doc, int v
    results.AddMember("diff_current",  m_diff, allocator);
    results.AddMember("shares_good",   m_accepted, allocator);
    results.AddMember("shares_total",  m_accepted + m_rejected, allocator);
-    results.AddMember("avg_time",      avgTime(), allocator);
+    results.AddMember("avg_time",      avgTime() / 1000, allocator);
+    results.AddMember("avg_time_ms",   avgTime(), allocator);
    results.AddMember("hashes_total",  m_hashes, allocator);

    Value best(kArrayType);
-    for (uint64_t i : topDiff) {
+    best.Reserve(m_topDiff.size(), allocator);
+
+    for (uint64_t i : m_topDiff) {
        best.PushBack(i, allocator);
    }

@@ -104,6 +184,84 @@ rapidjson::Value xmrig::NetworkState::getResults(rapidjson::Document &doc, int v
 #endif


+void xmrig::NetworkState::printConnection() const
+{
+    if (!m_active) {
+        LOG_NOTICE(YELLOW_BOLD_S "no active connection");
+
+        return;
+    }
+
+    Log::print(MAGENTA_BOLD_S " - CONNECTION");
+    Log::print(GREEN_BOLD(" * ") WHITE_BOLD("%-17s") CYAN_BOLD("%s ") BLACK_BOLD("(%s) ") GREEN_BOLD("%s"),
+               "pool address", m_pool, m_ip.data(), m_tls.isNull() ? "" : m_tls.data());
+
+    Log::print(GREEN_BOLD(" * ") WHITE_BOLD("%-17s") WHITE_BOLD("%s"), "algorithm", m_algorithm.shortName());
+    printDiff(m_diff);
+    printLatency(latency());
+    Log::print(GREEN_BOLD(" * ") WHITE_BOLD("%-17s") CYAN_BOLD("%" PRIu64 "s"), "connection time", connectionTime() / 1000);
+}
+
+
+void xmrig::NetworkState::printResults() const
+{
+    if (!m_hashes) {
+        LOG_NOTICE(YELLOW_BOLD_S "no any results yet");
+
+        return;
+    }
+
+    Log::print(MAGENTA_BOLD_S " - RESULTS");
+
+    printCount(m_accepted, m_rejected);
+    printHashes(m_accepted, m_hashes);
+    printDiff(m_diff);
+
+    if (m_active && !m_latency.empty()) {
+        printAvgTime(avgTime());
+    }
+
+    Log::print(MAGENTA_BOLD_S " - TOP 10");
+    Log::print(WHITE_BOLD_S "  # | DIFFICULTY | EFFORT %% |");
+
+    for (size_t i = 0; i < m_topDiff.size(); ++i) {
+        printDiff(i, m_topDiff[i], m_hashes);
+    }
+}
+
+
+const char *xmrig::NetworkState::scaleDiff(uint64_t &diff)
+{
+    if (diff >= 100000000000) {
+        diff /= 1000000000;
+
+        return "G";
+    }
+
+    if (diff >= 100000000) {
+        diff /= 1000000;
+
+        return "M";
+    }
+
+    if (diff >= 1000000) {
+        diff /= 1000;
+
+        return "K";
+    }
+
+    return "";
+}
+
+
+std::string xmrig::NetworkState::humanDiff(uint64_t diff)
+{
+    const char *scale = scaleDiff(diff);
+
+    return std::to_string(diff) + scale;
+}
+
+
 void xmrig::NetworkState::onActive(IStrategy *strategy, IClient *client)
 {
    snprintf(m_pool, sizeof(m_pool) - 1, "%s:%d", client->pool().host().data(), client->pool().port());
@@ -145,16 +303,6 @@ void xmrig::NetworkState::onResultAccepted(IStrategy *strategy, IClient *client,
 }


-uint32_t xmrig::NetworkState::avgTime() const
-{
-    if (m_latency.empty()) {
-        return 0;
-    }
-
-    return connectionTime() / (uint32_t)m_latency.size();
-}
-
-
 uint32_t xmrig::NetworkState::latency() const
 {
    const size_t calls = m_latency.size();
@@ -169,9 +317,19 @@ uint32_t xmrig::NetworkState::latency() const
 }


+uint64_t xmrig::NetworkState::avgTime() const
+{
+    if (m_latency.empty()) {
+        return 0;
+    }
+
+    return connectionTime() / m_latency.size();
+}
+
+
 uint64_t xmrig::NetworkState::connectionTime() const
 {
-    return m_active ? ((Chrono::steadyMSecs() - m_connectionTime) / 1000) : 0;
+    return m_active ? ((Chrono::steadyMSecs() - m_connectionTime)) : 0;
 }


@@ -185,10 +343,10 @@ void xmrig::NetworkState::add(const SubmitResult &result, const char *error)
    m_accepted++;
    m_hashes += result.diff;

-    const size_t ln = topDiff.size() - 1;
-    if (result.actualDiff > topDiff[ln]) {
-        topDiff[ln] = result.actualDiff;
-        std::sort(topDiff.rbegin(), topDiff.rend());
+    const size_t ln = m_topDiff.size() - 1;
+    if (result.actualDiff > m_topDiff[ln]) {
+        m_topDiff[ln] = result.actualDiff;
+        std::sort(m_topDiff.rbegin(), m_topDiff.rend());
    }

    m_latency.push_back(result.elapsed > 0xFFFF ? 0xFFFF : static_cast<uint16_t>(result.elapsed));
--- a/src/base/net/stratum/NetworkState.h
+++ b/src/base/net/stratum/NetworkState.h
@@ -32,6 +32,7 @@


 #include <array>
+#include <string>
 #include <vector>


@@ -52,6 +53,12 @@ public:
    rapidjson::Value getResults(rapidjson::Document &doc, int version) const;
 #   endif

+    void printConnection() const;
+    void printResults() const;
+
+    static const char *scaleDiff(uint64_t &diff);
+    static std::string humanDiff(uint64_t diff);
+
 protected:
    void onActive(IStrategy *strategy, IClient *client) override;
    void onJob(IStrategy *strategy, IClient *client, const Job &job, const rapidjson::Value &params) override;
@@ -59,8 +66,8 @@ protected:
    void onResultAccepted(IStrategy *strategy, IClient *client, const SubmitResult &result, const char *error) override;

 private:
-    uint32_t avgTime() const;
    uint32_t latency() const;
+    uint64_t avgTime() const;
    uint64_t connectionTime() const;
    void add(const SubmitResult &result, const char *error);
    void stop();
@@ -68,7 +75,7 @@ private:
    Algorithm m_algorithm;
    bool m_active               = false;
    char m_pool[256]{};
-    std::array<uint64_t, 10> topDiff { { } };
+    std::array<uint64_t, 10> m_topDiff { { } };
    std::vector<uint16_t> m_latency;
    String m_fingerprint;
    String m_ip;
--- a/src/config.json
+++ b/src/config.json
@@ -20,6 +20,7 @@
        "1gb-pages": false,
        "rdmsr": true,
        "wrmsr": true,
+        "cache_qos": false,
        "numa": true
    },
    "cpu": {
--- a/src/core/Controller.cpp
+++ b/src/core/Controller.cpp
@@ -98,3 +98,10 @@ xmrig::Network *xmrig::Controller::network() const

    return m_network;
 }
+
+
+void xmrig::Controller::execCommand(char command)
+{
+    miner()->execCommand(command);
+    network()->execCommand(command);
+}
--- a/src/core/Controller.h
+++ b/src/core/Controller.h
@@ -52,6 +52,7 @@ public:

    Miner *miner() const;
    Network *network() const;
+    void execCommand(char command);

 private:
    Miner *m_miner     = nullptr;
--- a/src/crypto/cn/CryptoNight_arm.h
+++ b/src/crypto/cn/CryptoNight_arm.h
@@ -33,7 +33,6 @@
 #include "crypto/cn/CryptoNight_monero.h"
 #include "crypto/cn/CryptoNight.h"
 #include "crypto/cn/soft_aes.h"
-#include "crypto/common/portable/mm_malloc.h"


 extern "C"
@@ -68,34 +67,6 @@ static inline void do_skein_hash(const uint8_t *input, size_t len, uint8_t *outp
 void (* const extra_hashes[4])(const uint8_t *, size_t, uint8_t *) = {do_blake_hash, do_groestl_hash, do_jh_hash, do_skein_hash};


-static inline __attribute__((always_inline)) __m128i _mm_set_epi64x(const uint64_t a, const uint64_t b)
-{
-    return vcombine_u64(vcreate_u64(b), vcreate_u64(a));
-}
-
-
-#if __ARM_FEATURE_CRYPTO
-static inline __attribute__((always_inline)) __m128i _mm_aesenc_si128(__m128i v, __m128i rkey)
-{
-    alignas(16) const __m128i zero = { 0 };
-    return veorq_u8(vaesmcq_u8(vaeseq_u8(v, zero)), rkey );
-}
-#else
-static inline __attribute__((always_inline)) __m128i _mm_aesenc_si128(__m128i v, __m128i rkey)
-{
-    alignas(16) const __m128i zero = { 0 };
-    return zero;
-}
-#endif
-
-
-/* this one was not implemented yet so here it is */
-static inline __attribute__((always_inline)) uint64_t _mm_cvtsi128_si64(__m128i a)
-{
-    return vgetq_lane_u64(a, 0);
-}
-
-
 #if defined (__arm64__) || defined (__aarch64__)
 static inline uint64_t __umul128(uint64_t a, uint64_t b, uint64_t* hi)
 {
--- a/src/crypto/cn/SSE2NEON.h
+++ b/src/crypto/cn/SSE2NEON.h
--- a/src/crypto/cn/soft_aes.h
+++ b/src/crypto/cn/soft_aes.h
@@ -28,7 +28,7 @@


 #if defined(XMRIG_ARM)
-#   include "crypto/cn/SSE2NEON.h"
+#   include "crypto/cn/sse2neon.h"
 #elif defined(__GNUC__)
 #   include <x86intrin.h>
 #else
--- a/src/crypto/cn/sse2neon.h
+++ b/src/crypto/cn/sse2neon.h
--- a/src/crypto/kawpow/KPCache.cpp
+++ b/src/crypto/kawpow/KPCache.cpp
@@ -92,9 +92,9 @@ bool KPCache::init(uint32_t epoch)
            const uint32_t b = (cache_nodes * (i + 1)) / n;

            threads.emplace_back([this, a, b, cache_nodes, &cache]() {
-                for (uint32_t j = a; j < b; ++j) {
-                    ethash_calculate_dag_item_opt(((node*)m_DAGCache.data()) + j, j, num_dataset_parents, &cache);
-                }
+                uint32_t j = a;
+                for (; j + 4 <= b; j += 4) ethash_calculate_dag_item4_opt(((node*)m_DAGCache.data()) + j, j, num_dataset_parents, &cache);
+                for (; j < b; ++j) ethash_calculate_dag_item_opt(((node*)m_DAGCache.data()) + j, j, num_dataset_parents, &cache);
            });
        }

--- a/src/crypto/kawpow/KPHash.cpp
+++ b/src/crypto/kawpow/KPHash.cpp
@@ -285,10 +285,7 @@ void KPHash::calculate(const KPCache& light_cache, uint32_t block_height, const
        uint32_t item_index = (mix[r % LANES][0] % num_items) * 4;

        node item[4];
-        ethash_calculate_dag_item_opt(item + 0, item_index + 0, KPCache::num_dataset_parents, &cache);
-        ethash_calculate_dag_item_opt(item + 1, item_index + 1, KPCache::num_dataset_parents, &cache);
-        ethash_calculate_dag_item_opt(item + 2, item_index + 2, KPCache::num_dataset_parents, &cache);
-        ethash_calculate_dag_item_opt(item + 3, item_index + 3, KPCache::num_dataset_parents, &cache);
+        ethash_calculate_dag_item4_opt(item, item_index, KPCache::num_dataset_parents, &cache);

        uint32_t dst_counter = 0;
        uint32_t src_counter = 0;
--- a/src/crypto/randomx/asm/program_read_dataset_ryzen.inc
+++ b/src/crypto/randomx/asm/program_read_dataset_ryzen.inc
@@ -1,13 +1,12 @@
 	mov rcx, rbp                       ;# ecx = ma
 	shr rcx, 32
 	and ecx, RANDOMX_DATASET_BASE_MASK
+	xor r8, qword ptr [rdi+rcx]
 	xor rbp, rax                       ;# modify "mx"
-	mov rax, qword ptr [rdi+rcx]
 	mov edx, ebp                       ;# edx = mx
 	and edx, RANDOMX_DATASET_BASE_MASK
 	prefetchnta byte ptr [rdi+rdx]
 	ror rbp, 32                        ;# swap "ma" and "mx"
-	xor r8,  rax
 	xor r9,  qword ptr [rdi+rcx+8]
 	xor r10, qword ptr [rdi+rcx+16]
 	xor r11, qword ptr [rdi+rcx+24]
--- a/src/crypto/randomx/randomx.h
+++ b/src/crypto/randomx/randomx.h
@@ -121,7 +121,7 @@ struct RandomX_ConfigurationBase
 	uint8_t codeShhPrefetchTweaked[20];
 	uint8_t codeReadDatasetTweaked[64];
 	uint32_t codeReadDatasetTweakedSize;
-	uint8_t codeReadDatasetRyzenTweaked[76];
+	uint8_t codeReadDatasetRyzenTweaked[72];
 	uint32_t codeReadDatasetRyzenTweakedSize;
 	uint8_t codeReadDatasetLightSshInitTweaked[68];
 	uint8_t codePrefetchScratchpadTweaked[32];
--- a/src/crypto/rx/Rx.cpp
+++ b/src/crypto/rx/Rx.cpp
@@ -28,6 +28,7 @@
 #include "crypto/rx/Rx.h"
 #include "backend/common/Tags.h"
 #include "backend/cpu/CpuConfig.h"
+#include "backend/cpu/CpuThreads.h"
 #include "base/io/log/Log.h"
 #include "base/io/log/Tags.h"
 #include "crypto/rx/RxConfig.h"
@@ -78,7 +79,7 @@ bool xmrig::Rx::init(const Job &job, const RxConfig &config, const CpuConfig &cp
    }

    if (!msrInitialized) {
-        msrInit(config);
+        msrInit(config, cpu.threads().get(job.algorithm()).data());
        msrInitialized = true;
    }

@@ -130,7 +131,7 @@ void xmrig::Rx::init(IRxListener *listener)


 #ifndef XMRIG_FEATURE_MSR
-void xmrig::Rx::msrInit(const RxConfig &)
+void xmrig::Rx::msrInit(const RxConfig &, const std::vector<CpuThread> &)
 {
 }

--- a/src/crypto/rx/Rx.h
+++ b/src/crypto/rx/Rx.h
@@ -30,6 +30,7 @@

 #include <cstdint>
 #include <utility>
+#include <vector>


 #include "crypto/common/HugePagesInfo.h"
@@ -41,6 +42,7 @@ namespace xmrig

 class Algorithm;
 class CpuConfig;
+class CpuThread;
 class IRxListener;
 class Job;
 class RxConfig;
@@ -62,7 +64,7 @@ public:
 #   endif

 private:
-    static void msrInit(const RxConfig &config);
+    static void msrInit(const RxConfig &config, const std::vector<CpuThread>& threads);
    static void msrDestroy();
    static void setupMainLoopExceptionFrame();
 };
--- a/src/crypto/rx/RxConfig.cpp
+++ b/src/crypto/rx/RxConfig.cpp
@@ -51,6 +51,7 @@ static const char *kMode        = "mode";
 static const char *kOneGbPages  = "1gb-pages";
 static const char *kRdmsr       = "rdmsr";
 static const char *kWrmsr       = "wrmsr";
+static const char *kCacheQoS    = "cache_qos";

 #ifdef XMRIG_FEATURE_HWLOC
 static const char *kNUMA        = "numa";
@@ -89,6 +90,8 @@ bool xmrig::RxConfig::read(const rapidjson::Value &value)
        readMSR(Json::getValue(value, kWrmsr));
 #       endif

+        m_cacheQoS = Json::getBool(value, kCacheQoS, m_cacheQoS);
+
 #       ifdef XMRIG_OS_LINUX
        m_oneGbPages = Json::getBool(value, kOneGbPages, m_oneGbPages);
 #       endif
@@ -151,6 +154,8 @@ rapidjson::Value xmrig::RxConfig::toJSON(rapidjson::Document &doc) const
    obj.AddMember(StringRef(kWrmsr), false, allocator);
 #   endif

+    obj.AddMember(StringRef(kCacheQoS), m_cacheQoS, allocator);
+
 #   ifdef XMRIG_FEATURE_HWLOC
    if (!m_nodeset.empty()) {
        Value numa(kArrayType);
--- a/src/crypto/rx/RxConfig.h
+++ b/src/crypto/rx/RxConfig.h
@@ -65,6 +65,7 @@ public:
    inline bool isOneGbPages() const    { return m_oneGbPages; }
    inline bool rdmsr() const           { return m_rdmsr; }
    inline bool wrmsr() const           { return m_wrmsr; }
+    inline bool cacheQoS() const        { return m_cacheQoS; }
    inline Mode mode() const            { return m_mode; }

 #   ifdef XMRIG_FEATURE_MSR
@@ -83,6 +84,8 @@ private:
    bool m_wrmsr = false;
 #   endif

+    bool m_cacheQoS = false;
+
    Mode readMode(const rapidjson::Value &value) const;

    bool m_numa         = true;
--- a/src/crypto/rx/Rx_linux.cpp
+++ b/src/crypto/rx/Rx_linux.cpp
@@ -29,6 +29,7 @@

 #include "crypto/rx/Rx.h"
 #include "backend/cpu/Cpu.h"
+#include "backend/cpu/CpuThread.h"
 #include "base/io/log/Log.h"
 #include "base/tools/Chrono.h"
 #include "crypto/rx/RxConfig.h"
@@ -123,14 +124,15 @@ static bool wrmsr_on_cpu(uint32_t reg, uint32_t cpu, uint64_t value, uint64_t ma
 }


-static bool wrmsr_on_all_cpus(uint32_t reg, uint64_t value, uint64_t mask)
+template<typename T>
+static bool wrmsr_on_all_cpus(uint32_t reg, uint64_t value, uint64_t mask, T&& callback)
 {
    struct dirent **namelist;
    int dir_entries = scandir("/dev/cpu", &namelist, dir_filter, 0);
    int errors      = 0;

    while (dir_entries--) {
-        if (!wrmsr_on_cpu(reg, strtoul(namelist[dir_entries]->d_name, nullptr, 10), value, mask)) {
+        if (!callback(reg, strtoul(namelist[dir_entries]->d_name, nullptr, 10), value, mask)) {
            ++errors;
        }

@@ -159,7 +161,7 @@ static bool wrmsr_modprobe()
 }


-static bool wrmsr(const MsrItems &preset, bool save)
+static bool wrmsr(const MsrItems& preset, const std::vector<CpuThread>& threads, bool cache_qos, bool save)
 {
    if (!wrmsr_modprobe()) {
        return false;
@@ -177,12 +179,66 @@ static bool wrmsr(const MsrItems &preset, bool save)
    }

    for (const auto &i : preset) {
-        if (!wrmsr_on_all_cpus(i.reg(), i.value(), i.mask())) {
+        if (!wrmsr_on_all_cpus(i.reg(), i.value(), i.mask(), [](uint32_t reg, uint32_t cpu, uint64_t value, uint64_t mask) { return wrmsr_on_cpu(reg, cpu, value, mask); })) {
            return false;
        }
    }

-    return true;
+    const uint32_t n = Cpu::info()->threads();
+
+    // Which CPU cores will have access to the full L3 cache
+    std::vector<bool> cacheEnabled(n, false);
+    bool cacheQoSDisabled = threads.empty();
+
+    for (const CpuThread& t : threads) {
+        // If some thread has no affinity or wrong affinity, disable cache QoS
+        if ((t.affinity() < 0) || (t.affinity() >= n)) {
+            cacheQoSDisabled = true;
+            if (cache_qos) {
+                LOG_WARN(CLEAR "%s" YELLOW_BOLD_S "Cache QoS can only be enabled when all mining threads have affinity set", tag);
+            }
+            break;
+        }
+
+        cacheEnabled[t.affinity()] = true;
+    }
+
+    if (cache_qos && !Cpu::info()->hasCatL3()) {
+        if (!threads.empty()) {
+            LOG_WARN(CLEAR "%s" YELLOW_BOLD_S "This CPU doesn't support cat_l3, cache QoS is unavailable", tag);
+        }
+        cache_qos = false;
+    }
+
+    bool result = true;
+
+    if (cache_qos) {
+        result = wrmsr_on_all_cpus(0xC8F, 0, MsrItem::kNoMask, [&cacheEnabled, cacheQoSDisabled](uint32_t, uint32_t cpu, uint64_t, uint64_t) {
+            if (cacheQoSDisabled || (cpu >= cacheEnabled.size()) || cacheEnabled[cpu]) {
+                // Assign Class Of Service 0 to current CPU core (default, full L3 cache available)
+                if (!wrmsr_on_cpu(0xC8F, cpu, 0, MsrItem::kNoMask)) {
+                    return false;
+                }
+            }
+            else {
+                // Disable L3 cache for Class Of Service 1
+                if (!wrmsr_on_cpu(0xC91, cpu, 0, MsrItem::kNoMask)) {
+                    // Some CPUs don't let set it to all zeros
+                    if (!wrmsr_on_cpu(0xC91, cpu, 1, MsrItem::kNoMask)) {
+                        return false;
+                    }
+                }
+
+                // Assign Class Of Service 1 to current CPU core
+                if (!wrmsr_on_cpu(0xC8F, cpu, 1ULL << 32, MsrItem::kNoMask)) {
+                    return false;
+                }
+            }
+            return true;
+        });
+    }
+
+    return result;
 }


@@ -216,7 +272,7 @@ void Rx::setMainLoopBounds(const std::pair<const void*, const void*>& bounds)
 } // namespace xmrig


-void xmrig::Rx::msrInit(const RxConfig &config)
+void xmrig::Rx::msrInit(const RxConfig &config, const std::vector<CpuThread>& threads)
 {
    const auto &preset = config.msrPreset();
    if (preset.empty()) {
@@ -225,9 +281,12 @@ void xmrig::Rx::msrInit(const RxConfig &config)

    const uint64_t ts = Chrono::steadyMSecs();

-    if (wrmsr(preset, config.rdmsr())) {
+    if (wrmsr(preset, threads, config.cacheQoS(), config.rdmsr())) {
        LOG_NOTICE(CLEAR "%s" GREEN_BOLD_S "register values for \"%s\" preset has been set successfully" BLACK_BOLD(" (%" PRIu64 " ms)"), tag, config.msrPresetName(), Chrono::steadyMSecs() - ts);
    }
+    else {
+        LOG_ERR(CLEAR "%s" RED_BOLD_S "FAILED TO APPLY MSR MOD, HASHRATE WILL BE LOW", tag);
+    }
 }


@@ -239,7 +298,7 @@ void xmrig::Rx::msrDestroy()

    const uint64_t ts = Chrono::steadyMSecs();

-    if (!wrmsr(savedState, false)) {
+    if (!wrmsr(savedState, std::vector<CpuThread>(), true, false)) {
        LOG_ERR(CLEAR "%s" RED_BOLD_S "failed to restore initial state" BLACK_BOLD(" (%" PRIu64 " ms)"), tag, Chrono::steadyMSecs() - ts);
    }
 }
--- a/src/crypto/rx/Rx_win.cpp
+++ b/src/crypto/rx/Rx_win.cpp
@@ -30,6 +30,7 @@

 #include "crypto/rx/Rx.h"
 #include "backend/cpu/Cpu.h"
+#include "backend/cpu/CpuThread.h"
 #include "base/io/log/Log.h"
 #include "base/kernel/Platform.h"
 #include "base/tools/Chrono.h"
@@ -256,7 +257,7 @@ static bool wrmsr(HANDLE driver, uint32_t reg, uint64_t value, uint64_t mask)
 }


-static bool wrmsr(const MsrItems &preset, bool save)
+static bool wrmsr(const MsrItems &preset, const std::vector<CpuThread>& threads, bool cache_qos, bool save)
 {
    bool success = true;

@@ -282,14 +283,59 @@ static bool wrmsr(const MsrItems &preset, bool save)
        }
    }

-    std::thread wrmsr_thread([driver, &preset, &success]() {
-        for (uint32_t i = 0, n = Cpu::info()->threads(); i < n; ++i) {
+    const uint32_t n = Cpu::info()->threads();
+
+    // Which CPU cores will have access to the full L3 cache
+    std::vector<bool> cacheEnabled(n, false);
+    bool cacheQoSDisabled = threads.empty();
+
+    for (const CpuThread& t : threads) {
+        // If some thread has no affinity or wrong affinity, disable cache QoS
+        if ((t.affinity() < 0) || (t.affinity() >= n)) {
+            cacheQoSDisabled = true;
+            if (cache_qos) {
+                LOG_WARN(CLEAR "%s" YELLOW_BOLD_S "Cache QoS can only be enabled when all mining threads have affinity set", tag);
+            }
+            break;
+        }
+
+        cacheEnabled[t.affinity()] = true;
+    }
+
+    if (cache_qos && !Cpu::info()->hasCatL3()) {
+        if (!threads.empty()) {
+            LOG_WARN(CLEAR "%s" YELLOW_BOLD_S "This CPU doesn't support cat_l3, cache QoS is unavailable", tag);
+        }
+        cache_qos = false;
+    }
+
+    std::thread wrmsr_thread([n, driver, &preset, &cacheEnabled, cache_qos, cacheQoSDisabled, &success]() {
+        for (uint32_t i = 0; i < n; ++i) {
            if (!Platform::setThreadAffinity(i)) {
                continue;
            }

            for (const auto &i : preset) {
-                success = wrmsr(driver, i.reg(), i.value(), i.mask());
+                success &= wrmsr(driver, i.reg(), i.value(), i.mask());
+            }
+
+            if (cache_qos) {
+                if (cacheQoSDisabled || cacheEnabled[i]) {
+                    // Assign Class Of Service 0 to current CPU core (default, full L3 cache available)
+                    success &= wrmsr(driver, 0xC8F, 0, MsrItem::kNoMask);
+                }
+                else {
+                    // Disable L3 cache for Class Of Service 1
+                    if (!wrmsr(driver, 0xC91, 0, MsrItem::kNoMask)) {
+                        // Some CPUs don't let set it to all zeros
+                        if (!wrmsr(driver, 0xC91, 1, MsrItem::kNoMask)) {
+                            success = false;
+                        }
+                    }
+
+                    // Assign Class Of Service 1 to current CPU core
+                    success &= wrmsr(driver, 0xC8F, 1ULL << 32, MsrItem::kNoMask);
+                }
            }

            if (!success) {
@@ -349,7 +395,7 @@ void Rx::setMainLoopBounds(const std::pair<const void*, const void*>& bounds)
 } // namespace xmrig


-void xmrig::Rx::msrInit(const RxConfig &config)
+void xmrig::Rx::msrInit(const RxConfig &config, const std::vector<CpuThread>& threads)
 {
    const auto &preset = config.msrPreset();
    if (preset.empty()) {
@@ -358,9 +404,12 @@ void xmrig::Rx::msrInit(const RxConfig &config)

    const uint64_t ts = Chrono::steadyMSecs();

-    if (wrmsr(preset, config.rdmsr())) {
+    if (wrmsr(preset, threads, config.cacheQoS(), config.rdmsr())) {
        LOG_NOTICE(CLEAR "%s" GREEN_BOLD_S "register values for \"%s\" preset has been set successfully" BLACK_BOLD(" (%" PRIu64 " ms)"), tag, config.msrPresetName(), Chrono::steadyMSecs() - ts);
    }
+    else {
+        LOG_ERR(CLEAR "%s" RED_BOLD_S "FAILED TO APPLY MSR MOD, HASHRATE WILL BE LOW", tag);
+    }
 }


@@ -372,7 +421,7 @@ void xmrig::Rx::msrDestroy()

    const uint64_t ts = Chrono::steadyMSecs();

-    if (!wrmsr(savedState, false)) {
+    if (!wrmsr(savedState, std::vector<CpuThread>(), true, false)) {
        LOG_ERR(CLEAR "%s" RED_BOLD_S "failed to restore initial state" BLACK_BOLD(" (%" PRIu64 " ms)"), tag, Chrono::steadyMSecs() - ts);
    }
 }
--- a/src/net/Network.cpp
+++ b/src/net/Network.cpp
@@ -98,6 +98,25 @@ void xmrig::Network::connect()
 }


+void xmrig::Network::execCommand(char command)
+{
+    switch (command) {
+    case 's':
+    case 'S':
+        m_state->printResults();
+        break;
+
+    case 'c':
+    case 'C':
+        m_state->printConnection();
+        break;
+
+    default:
+        break;
+    }
+}
+
+
 void xmrig::Network::onActive(IStrategy *strategy, IClient *client)
 {
    if (m_donate && m_donate == strategy) {
@@ -192,24 +211,10 @@ void xmrig::Network::onPause(IStrategy *strategy)
 }


-static void scale_diff(uint64_t& diff, const char* &scale)
-{
-    if (diff >= 100000000) {
-        diff /= 1000000;
-        scale = "M";
-    }
-    else if (diff >= 1000000) {
-        diff /= 1000;
-        scale = "K";
-    }
-}
-
-
 void xmrig::Network::onResultAccepted(IStrategy *, IClient *, const SubmitResult &result, const char *error)
 {
-    uint64_t diff = result.diff;
-    const char* scale = "";
-    scale_diff(diff, scale);
+    uint64_t diff     = result.diff;
+    const char *scale = NetworkState::scaleDiff(diff);

    if (error) {
        LOG_INFO("%s " RED_BOLD("rejected") " (%" PRId64 "/%" PRId64 ") diff " WHITE_BOLD("%" PRIu64 "%s") " " RED("\"%s\"") " " BLACK_BOLD("(%" PRIu64 " ms)"),
@@ -247,9 +252,8 @@ void xmrig::Network::onRequest(IApiRequest &request)

 void xmrig::Network::setJob(IClient *client, const Job &job, bool donate)
 {
-    uint64_t diff = job.diff();
-    const char* scale = "";
-    scale_diff(diff, scale);
+    uint64_t diff     = job.diff();;
+    const char *scale = NetworkState::scaleDiff(diff);

    if (job.height()) {
        LOG_INFO("%s " MAGENTA_BOLD("new job") " from " WHITE_BOLD("%s:%d") " diff " WHITE_BOLD("%" PRIu64 "%s") " algo " WHITE_BOLD("%s") " height " WHITE_BOLD("%" PRIu64),
--- a/src/net/Network.h
+++ b/src/net/Network.h
@@ -58,6 +58,7 @@ public:
    inline IStrategy *strategy() const { return m_strategy; }

    void connect();
+    void execCommand(char command);

 protected:
    inline void onTimer(const Timer *) override { tick(); }
--- a/src/version.h
+++ b/src/version.h
@@ -28,15 +28,15 @@
 #define APP_ID        "xmrig"
 #define APP_NAME      "XMRig"
 #define APP_DESC      "XMRig miner"
-#define APP_VERSION   "6.2.1"
+#define APP_VERSION   "6.3.0"
 #define APP_DOMAIN    "xmrig.com"
 #define APP_SITE      "www.xmrig.com"
 #define APP_COPYRIGHT "Copyright (C) 2016-2020 xmrig.com"
 #define APP_KIND      "miner"

 #define APP_VER_MAJOR  6
-#define APP_VER_MINOR  2
-#define APP_VER_PATCH  1
+#define APP_VER_MINOR  3
+#define APP_VER_PATCH  0

 #ifdef _MSC_VER
 #   if (_MSC_VER >= 1920)
Author	SHA1	Message	Date
XMRig	10ea567084	v6.3.0	2020-07-17 00:17:55 +07:00
XMRig	028d6503aa	Merge branch 'dev'	2020-07-17 00:17:24 +07:00
XMRig	51346c2b2b	v6.3.0-dev	2020-07-17 00:04:31 +07:00
XMRig	ca535c7813	Sync changes with the proxy.	2020-07-16 23:29:21 +07:00
xmrig	ba80e27349	Merge pull request #1780 from SChernykh/dev Cryptonight OpenCL: fix for long input data	2020-07-16 19:56:20 +07:00
SChernykh	bd8cf54a0b	Cryptonight OpenCL: fix for long input data	2020-07-16 10:39:32 +02:00
XMRig	e0eed7d5d6	Fixed build without MSR support.	2020-07-16 05:15:35 +07:00
XMRig	8dff08f15f	Merge branch 'haven-protocol-org-master' into dev	2020-07-15 23:33:53 +07:00
XMRig	47d68b068b	Merge branch 'master' of https://github.com/haven-protocol-org/xmrig into haven-protocol-org-master	2020-07-15 23:33:17 +07:00
Neil Coggins	a648a8b9be	Increased max blob size to support Haven offshore capability	2020-07-14 11:52:43 +01:00
xmrig	7eefccc6bc	Merge pull request #1776 from SChernykh/dev Removed cache QoS warning at exit on unsupported CPUs	2020-07-14 01:45:18 +07:00
SChernykh	1bf159d1e8	Removed cache QoS warning at exit on unsupported CPUs	2020-07-13 20:43:49 +02:00
xmrig	bf46cb8684	Merge pull request #1774 from SChernykh/dev RandomX: added cache QoS support	2020-07-14 01:35:46 +07:00
SChernykh	72c385c870	Cache QoS: fix for seting MSR	2020-07-13 20:30:44 +02:00
SChernykh	c83429c55c	RandomX: added cache QoS support False by default. If set to true, all non-mining CPU cores will not have access to L3 cache.	2020-07-13 17:23:18 +02:00
xmrig	e5a2689052	Merge pull request #1771 from jserv/update-sse2neon Adopt new SSE2NEON and reduce ARM-specific changes	2020-07-11 02:32:56 +07:00
Jim Huang	b665d2d865	Adopt new SSE2NEON and reduce ARM-specific changes This patch updated SSE2NEON [1], which contains more functions provided by Intel intrinsics, only implemented with NEON-based counterparts to produce the exact semantics of the intrinsics. Consequently, ARM-specific changes against CryptoNight_arm can be reduced as well. [1] https://github.com/DLTcollab/sse2neon/	2020-07-11 01:55:11 +08:00
XMRig	e06a76ef1c	v6.2.4-dev	2020-07-10 03:12:00 +07:00
XMRig	f523fddbfd	Merge branch 'master' into dev	2020-07-10 02:49:33 +07:00
XMRig	30165ce4be	v6.2.3	2020-07-09 22:24:35 +07:00
XMRig	83a10cce8c	Merge branch 'dev'	2020-07-09 22:24:01 +07:00
xmrig	71cc486553	Update CHANGELOG.md	2020-07-09 22:23:16 +07:00
xmrig	2eaf8edf0e	Merge pull request #1766 from SChernykh/dev RandomX: tweaked Ryzen code	2020-07-05 21:16:21 +07:00
SChernykh	3d740e81a2	RandomX: tweaked Ryzen code Very small speedup	2020-07-05 16:06:59 +02:00
xmrig	ef475d98da	Update CHANGELOG.md	2020-07-04 19:11:29 +07:00
xmrig	5e92acab34	Merge pull request #1763 from SChernykh/dev KawPow: fixed more duplicate share errors	2020-07-04 02:37:03 +07:00
SChernykh	935b8a1106	KawPow: fixed more duplicate share errors	2020-07-03 21:33:44 +02:00
xmrig	c371a7a2bb	Update CHANGELOG.md	2020-07-04 00:29:50 +07:00
XMRig	4fe011b469	Fix tab/space inconsistency.	2020-07-03 21:36:06 +07:00
XMRig	bf32802a82	#1754 Fixed GPU health readings for pre Vega GPUs.	2020-07-03 21:14:21 +07:00
xmrig	ccfbba94f2	Merge pull request #1761 from SChernykh/dev Fix typo	2020-07-02 19:41:19 +07:00
SChernykh	70d7fe9b59	Fix typo	2020-07-02 14:29:52 +02:00
xmrig	34a5c89ee2	Merge pull request #1760 from SChernykh/dev KawPow: fixed rare duplicate share errors	2020-07-02 19:23:28 +07:00
SChernykh	39ed25cf7b	KawPow: fixed rare duplicate share errors	2020-07-02 11:36:31 +02:00
XMRig	26c2200af3	#1756 Added results and connection reports.	2020-07-01 23:10:37 +07:00
xmrig	aa5a7c3c13	Merge pull request #1759 from SChernykh/dev Fixed DAG initialization on slower AMD GPUs	2020-06-30 21:59:32 +07:00
SChernykh	08ca51ec4c	Fixed DAG initialization on slower AMD GPUs Display driver could reset on GPUs with screen connected.	2020-06-30 16:53:56 +02:00
xmrig	bbd9945866	Merge pull request #1752 from SChernykh/dev Print error message when MSR mod fails	2020-06-27 00:59:25 +07:00
SChernykh	59313d9cc3	Print error message when MSR mod fails Make sure user knows that hashrate is worse than it could be.	2020-06-26 19:54:06 +02:00
xmrig	2da5d31a5d	Merge pull request #1749 from SChernykh/dev KawPow: optimized CPU share verification	2020-06-26 17:39:37 +07:00
SChernykh	5724d8beb6	KawPow: optimized CPU share verification - 2 times faster CPU share verification (11 -> 5 ms) - 1.5 times faster light cache initialization	2020-06-26 12:31:26 +02:00
XMRig	03e9797b92	Merge branch 'dev' of https://github.com/SChernykh/xmrig into dev	2020-06-23 19:12:34 +07:00
XMRig	74bd9460d7	v6.2.3-dev	2020-06-23 19:05:54 +07:00
XMRig	f033cb7f46	Merge branch 'master' into dev	2020-06-23 19:05:21 +07:00
SChernykh	38cf5b6324	Fixed AstroBWT OpenCL compilation on some systems	2020-06-23 13:55:43 +02:00
XMRig	16863763d3	#1742 Fixed crash when use HTTP API.	2020-06-23 16:17:06 +07:00
xmrig	aa1934d273	Update CHANGELOG.md	2020-06-23 12:55:48 +07:00