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https://github.com/xmrig/xmrig.git
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2 Commits
v6.19.3
...
1f45acd576
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1f45acd576 | ||
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df031be628 |
@@ -1,11 +1,3 @@
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# v6.19.3
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- [#3245](https://github.com/xmrig/xmrig/issues/3245) Improved algorithm negotiation for donation rounds by sending extra information about current mining job.
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- [#3254](https://github.com/xmrig/xmrig/pull/3254) Tweaked auto-tuning for Intel CPUs.
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- [#3271](https://github.com/xmrig/xmrig/pull/3271) RandomX: optimized program generation.
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- [#3273](https://github.com/xmrig/xmrig/pull/3273) RandomX: fixed undefined behavior.
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- [#3275](https://github.com/xmrig/xmrig/pull/3275) RandomX: fixed `jccErratum` list.
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- [#3280](https://github.com/xmrig/xmrig/pull/3280) Updated example scripts.
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# v6.19.2
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# v6.19.2
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- [#3230](https://github.com/xmrig/xmrig/pull/3230) Fixed parsing of `TX_EXTRA_MERGE_MINING_TAG`.
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- [#3230](https://github.com/xmrig/xmrig/pull/3230) Fixed parsing of `TX_EXTRA_MERGE_MINING_TAG`.
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- [#3232](https://github.com/xmrig/xmrig/pull/3232) Added new `X-Hash-Difficulty` HTTP header.
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- [#3232](https://github.com/xmrig/xmrig/pull/3232) Added new `X-Hash-Difficulty` HTTP header.
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45
Dockerfile
Normal file
45
Dockerfile
Normal file
@@ -0,0 +1,45 @@
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# Build in disposable container so run-time container is small
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FROM alpine:latest as build
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# Build from master by default but allow build time specification
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ARG ref=master
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ENV my_ref=$ref
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# Developers may wish to specify an alternate repository for source
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ARG repo=https://github.com/xmrig/xmrig.git
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ENV my_repo=$repo
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RUN set -ex && \
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# testing required for hwloc
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echo @testing http://nl.alpinelinux.org/alpine/edge/testing >> /etc/apk/repositories
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RUN set -ex && \
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apk --no-cache --update add \
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coreutils file grep openssl tar binutils \
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cmake g++ git linux-headers libpthread-stubs make hwloc-dev@testing \
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libuv-dev openssl-dev
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WORKDIR /usr/local/src
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RUN set -ex && \
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git clone $my_repo xmrig && \
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cd xmrig && git checkout $my_ref && \
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cmake -B build && \
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cd build && \
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make
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# runtime container
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FROM alpine:latest
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RUN set -ex && \
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# testing required for hwloc
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echo @testing http://nl.alpinelinux.org/alpine/edge/testing >> /etc/apk/repositories
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RUN set -ex && \
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apk --no-cache --update add \
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# required libraries packages
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openssl libuv hwloc@testing
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COPY --from=build /usr/local/src/xmrig/build/xmrig /bin/
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ENTRYPOINT ["/bin/xmrig"]
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@@ -16,5 +16,5 @@
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:: Smaller pools also often have smaller fees/payout limits.
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:: Smaller pools also often have smaller fees/payout limits.
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cd /d "%~dp0"
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cd /d "%~dp0"
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xmrig.exe -o xmrpool.eu:3333 -u 48edfHu7V9Z84YzzMa6fUueoELZ9ZRXq9VetWzYGzKt52XU5xvqgzYnDK9URnRoJMk1j8nLwEVsaSWJ4fhdUyZijBGUicoD -p x
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xmrig.exe -o pool.hashvault.pro:3333 -u 48edfHu7V9Z84YzzMa6fUueoELZ9ZRXq9VetWzYGzKt52XU5xvqgzYnDK9URnRoJMk1j8nLwEVsaSWJ4fhdUyZijBGUicoD -p x
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pause
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pause
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@@ -12,5 +12,5 @@
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:: But you will only get a payout when you find a block which can take more than a year for a single low-end PC.
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:: But you will only get a payout when you find a block which can take more than a year for a single low-end PC.
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cd /d "%~dp0"
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cd /d "%~dp0"
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xmrig.exe -o YOUR_NODE_IP:18081 -a rx/0 -u 48edfHu7V9Z84YzzMa6fUueoELZ9ZRXq9VetWzYGzKt52XU5xvqgzYnDK9URnRoJMk1j8nLwEVsaSWJ4fhdUyZijBGUicoD --daemon
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xmrig.exe -o node.xmr.to:18081 -a rx/0 -u 48edfHu7V9Z84YzzMa6fUueoELZ9ZRXq9VetWzYGzKt52XU5xvqgzYnDK9URnRoJMk1j8nLwEVsaSWJ4fhdUyZijBGUicoD --daemon
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pause
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pause
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@@ -296,7 +296,7 @@ xmrig::BasicCpuInfo::BasicCpuInfo() :
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// Affected CPU models and stepping numbers are taken from https://www.intel.com/content/dam/support/us/en/documents/processors/mitigations-jump-conditional-code-erratum.pdf
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// Affected CPU models and stepping numbers are taken from https://www.intel.com/content/dam/support/us/en/documents/processors/mitigations-jump-conditional-code-erratum.pdf
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m_jccErratum =
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m_jccErratum =
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((model == 0x4E) && (stepping == 0x3)) ||
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((model == 0x4E) && (stepping == 0x3)) ||
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((model == 0x55) && ((stepping == 0x4) || (stepping == 0x7))) ||
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((model == 0x55) && (stepping == 0x4)) ||
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((model == 0x5E) && (stepping == 0x3)) ||
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((model == 0x5E) && (stepping == 0x3)) ||
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((model == 0x8E) && (stepping >= 0x9) && (stepping <= 0xC)) ||
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((model == 0x8E) && (stepping >= 0x9) && (stepping <= 0xC)) ||
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((model == 0x9E) && (stepping >= 0x9) && (stepping <= 0xD)) ||
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((model == 0x9E) && (stepping >= 0x9) && (stepping <= 0xD)) ||
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@@ -34,8 +34,6 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#include "base/tools/Chrono.h"
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#include "base/tools/Chrono.h"
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#include "crypto/randomx/randomx.h"
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#include "crypto/randomx/randomx.h"
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#include "crypto/randomx/soft_aes.h"
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#include "crypto/randomx/soft_aes.h"
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#include "crypto/randomx/instruction.hpp"
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#include "crypto/randomx/common.hpp"
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#include "crypto/rx/Profiler.h"
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#include "crypto/rx/Profiler.h"
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#define AES_HASH_1R_STATE0 0xd7983aad, 0xcc82db47, 0x9fa856de, 0x92b52c0d
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#define AES_HASH_1R_STATE0 0xd7983aad, 0xcc82db47, 0x9fa856de, 0x92b52c0d
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@@ -167,9 +165,6 @@ void fillAes1Rx4(void *state, size_t outputSize, void *buffer) {
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template void fillAes1Rx4<true>(void *state, size_t outputSize, void *buffer);
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template void fillAes1Rx4<true>(void *state, size_t outputSize, void *buffer);
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template void fillAes1Rx4<false>(void *state, size_t outputSize, void *buffer);
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template void fillAes1Rx4<false>(void *state, size_t outputSize, void *buffer);
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static constexpr randomx::Instruction inst{ 0xFF, 7, 7, 0xFF, 0xFFFFFFFFU };
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alignas(16) static const randomx::Instruction inst_mask[2] = { inst, inst };
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template<int softAes>
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template<int softAes>
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void fillAes4Rx4(void *state, size_t outputSize, void *buffer) {
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void fillAes4Rx4(void *state, size_t outputSize, void *buffer) {
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const uint8_t* outptr = (uint8_t*)buffer;
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const uint8_t* outptr = (uint8_t*)buffer;
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@@ -192,42 +187,32 @@ void fillAes4Rx4(void *state, size_t outputSize, void *buffer) {
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state2 = rx_load_vec_i128((rx_vec_i128*)state + 2);
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state2 = rx_load_vec_i128((rx_vec_i128*)state + 2);
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state3 = rx_load_vec_i128((rx_vec_i128*)state + 3);
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state3 = rx_load_vec_i128((rx_vec_i128*)state + 3);
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#define TRANSFORM do { \
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while (outptr < outputEnd) {
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state0 = aesdec<softAes>(state0, key0); \
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state0 = aesdec<softAes>(state0, key0);
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state1 = aesenc<softAes>(state1, key0); \
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state1 = aesenc<softAes>(state1, key0);
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state2 = aesdec<softAes>(state2, key4); \
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state2 = aesdec<softAes>(state2, key4);
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state3 = aesenc<softAes>(state3, key4); \
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state3 = aesenc<softAes>(state3, key4);
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state0 = aesdec<softAes>(state0, key1); \
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state1 = aesenc<softAes>(state1, key1); \
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state0 = aesdec<softAes>(state0, key1);
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state2 = aesdec<softAes>(state2, key5); \
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state1 = aesenc<softAes>(state1, key1);
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state3 = aesenc<softAes>(state3, key5); \
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state2 = aesdec<softAes>(state2, key5);
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state0 = aesdec<softAes>(state0, key2); \
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state3 = aesenc<softAes>(state3, key5);
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state1 = aesenc<softAes>(state1, key2); \
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state2 = aesdec<softAes>(state2, key6); \
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state0 = aesdec<softAes>(state0, key2);
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state3 = aesenc<softAes>(state3, key6); \
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state1 = aesenc<softAes>(state1, key2);
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state0 = aesdec<softAes>(state0, key3); \
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state2 = aesdec<softAes>(state2, key6);
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state1 = aesenc<softAes>(state1, key3); \
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state3 = aesenc<softAes>(state3, key6);
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state2 = aesdec<softAes>(state2, key7); \
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state3 = aesenc<softAes>(state3, key7); \
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state0 = aesdec<softAes>(state0, key3);
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} while (0)
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state1 = aesenc<softAes>(state1, key3);
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state2 = aesdec<softAes>(state2, key7);
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state3 = aesenc<softAes>(state3, key7);
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for (int i = 0; i < 2; ++i, outptr += 64) {
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TRANSFORM;
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rx_store_vec_i128((rx_vec_i128*)outptr + 0, state0);
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rx_store_vec_i128((rx_vec_i128*)outptr + 0, state0);
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rx_store_vec_i128((rx_vec_i128*)outptr + 1, state1);
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rx_store_vec_i128((rx_vec_i128*)outptr + 1, state1);
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rx_store_vec_i128((rx_vec_i128*)outptr + 2, state2);
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rx_store_vec_i128((rx_vec_i128*)outptr + 2, state2);
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rx_store_vec_i128((rx_vec_i128*)outptr + 3, state3);
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rx_store_vec_i128((rx_vec_i128*)outptr + 3, state3);
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}
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static_assert(sizeof(inst_mask) == sizeof(rx_vec_i128), "Incorrect inst_mask size");
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const rx_vec_i128 mask = *reinterpret_cast<const rx_vec_i128*>(inst_mask);
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while (outptr < outputEnd) {
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TRANSFORM;
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rx_store_vec_i128((rx_vec_i128*)outptr + 0, rx_and_vec_i128(state0, mask));
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rx_store_vec_i128((rx_vec_i128*)outptr + 1, rx_and_vec_i128(state1, mask));
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rx_store_vec_i128((rx_vec_i128*)outptr + 2, rx_and_vec_i128(state2, mask));
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rx_store_vec_i128((rx_vec_i128*)outptr + 3, rx_and_vec_i128(state3, mask));
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outptr += 64;
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outptr += 64;
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}
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}
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}
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}
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@@ -126,7 +126,6 @@ FORCE_INLINE rx_vec_f128 rx_set1_vec_f128(uint64_t x) {
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#define rx_xor_vec_f128 _mm_xor_pd
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#define rx_xor_vec_f128 _mm_xor_pd
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#define rx_and_vec_f128 _mm_and_pd
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#define rx_and_vec_f128 _mm_and_pd
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#define rx_and_vec_i128 _mm_and_si128
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#define rx_or_vec_f128 _mm_or_pd
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#define rx_or_vec_f128 _mm_or_pd
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#ifdef __AES__
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#ifdef __AES__
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@@ -279,10 +278,6 @@ FORCE_INLINE rx_vec_f128 rx_and_vec_f128(rx_vec_f128 a, rx_vec_f128 b) {
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return (rx_vec_f128)vec_and(a,b);
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return (rx_vec_f128)vec_and(a,b);
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}
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}
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FORCE_INLINE rx_vec_i128 rx_and_vec_i128(rx_vec_i128 a, rx_vec_i128 b) {
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return (rx_vec_i128)vec_and(a, b);
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}
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FORCE_INLINE rx_vec_f128 rx_or_vec_f128(rx_vec_f128 a, rx_vec_f128 b) {
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FORCE_INLINE rx_vec_f128 rx_or_vec_f128(rx_vec_f128 a, rx_vec_f128 b) {
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return (rx_vec_f128)vec_or(a,b);
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return (rx_vec_f128)vec_or(a,b);
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}
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}
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@@ -449,8 +444,6 @@ FORCE_INLINE rx_vec_f128 rx_and_vec_f128(rx_vec_f128 a, rx_vec_f128 b) {
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return vreinterpretq_f64_u8(vandq_u8(vreinterpretq_u8_f64(a), vreinterpretq_u8_f64(b)));
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return vreinterpretq_f64_u8(vandq_u8(vreinterpretq_u8_f64(a), vreinterpretq_u8_f64(b)));
|
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}
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}
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#define rx_and_vec_i128 vandq_u8
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FORCE_INLINE rx_vec_f128 rx_or_vec_f128(rx_vec_f128 a, rx_vec_f128 b) {
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FORCE_INLINE rx_vec_f128 rx_or_vec_f128(rx_vec_f128 a, rx_vec_f128 b) {
|
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return vreinterpretq_f64_u8(vorrq_u8(vreinterpretq_u8_f64(a), vreinterpretq_u8_f64(b)));
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return vreinterpretq_f64_u8(vorrq_u8(vreinterpretq_u8_f64(a), vreinterpretq_u8_f64(b)));
|
||||||
}
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}
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@@ -642,13 +635,6 @@ FORCE_INLINE rx_vec_f128 rx_and_vec_f128(rx_vec_f128 a, rx_vec_f128 b) {
|
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return x;
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return x;
|
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}
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}
|
||||||
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|
||||||
FORCE_INLINE rx_vec_i128 rx_and_vec_i128(rx_vec_i128 a, rx_vec_i128 b) {
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|
||||||
rx_vec_i128 x;
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|
||||||
x.u64[0] = a.u64[0] & b.u64[0];
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|
||||||
x.u64[1] = a.u64[1] & b.u64[1];
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|
||||||
return x;
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|
||||||
}
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|
||||||
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|
||||||
FORCE_INLINE rx_vec_f128 rx_or_vec_f128(rx_vec_f128 a, rx_vec_f128 b) {
|
FORCE_INLINE rx_vec_f128 rx_or_vec_f128(rx_vec_f128 a, rx_vec_f128 b) {
|
||||||
rx_vec_f128 x;
|
rx_vec_f128 x;
|
||||||
x.i.u64[0] = a.i.u64[0] | b.i.u64[0];
|
x.i.u64[0] = a.i.u64[0] | b.i.u64[0];
|
||||||
|
|||||||
@@ -144,6 +144,8 @@ void JitCompilerA64::generateProgram(Program& program, ProgramConfiguration& con
|
|||||||
for (uint32_t i = 0; i < program.getSize(); ++i)
|
for (uint32_t i = 0; i < program.getSize(); ++i)
|
||||||
{
|
{
|
||||||
Instruction& instr = program(i);
|
Instruction& instr = program(i);
|
||||||
|
instr.src %= RegistersCount;
|
||||||
|
instr.dst %= RegistersCount;
|
||||||
(this->*engine[instr.opcode])(instr, codePos);
|
(this->*engine[instr.opcode])(instr, codePos);
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -202,6 +204,8 @@ void JitCompilerA64::generateProgramLight(Program& program, ProgramConfiguration
|
|||||||
for (uint32_t i = 0; i < program.getSize(); ++i)
|
for (uint32_t i = 0; i < program.getSize(); ++i)
|
||||||
{
|
{
|
||||||
Instruction& instr = program(i);
|
Instruction& instr = program(i);
|
||||||
|
instr.src %= RegistersCount;
|
||||||
|
instr.dst %= RegistersCount;
|
||||||
(this->*engine[instr.opcode])(instr, codePos);
|
(this->*engine[instr.opcode])(instr, codePos);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|||||||
@@ -312,19 +312,11 @@ namespace randomx {
|
|||||||
freePagedMemory(allocatedCode, allocatedSize);
|
freePagedMemory(allocatedCode, allocatedSize);
|
||||||
}
|
}
|
||||||
|
|
||||||
template<size_t N>
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|
||||||
static FORCE_INLINE void prefetch_data(const void* data) {
|
|
||||||
rx_prefetch_nta(data);
|
|
||||||
prefetch_data<N - 1>(reinterpret_cast<const char*>(data) + 64);
|
|
||||||
}
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|
||||||
|
|
||||||
template<> FORCE_INLINE void prefetch_data<0>(const void*) {}
|
|
||||||
|
|
||||||
template<typename T> static FORCE_INLINE void prefetch_data(const T& data) { prefetch_data<(sizeof(T) + 63) / 64>(&data); }
|
|
||||||
|
|
||||||
void JitCompilerX86::prepare() {
|
void JitCompilerX86::prepare() {
|
||||||
prefetch_data(engine);
|
for (size_t i = 0; i < sizeof(engine); i += 64)
|
||||||
prefetch_data(RandomX_CurrentConfig);
|
rx_prefetch_nta((const char*)(&engine) + i);
|
||||||
|
for (size_t i = 0; i < sizeof(RandomX_CurrentConfig); i += 64)
|
||||||
|
rx_prefetch_nta((const char*)(&RandomX_CurrentConfig) + i);
|
||||||
}
|
}
|
||||||
|
|
||||||
void JitCompilerX86::generateProgram(Program& prog, ProgramConfiguration& pcfg, uint32_t flags) {
|
void JitCompilerX86::generateProgram(Program& prog, ProgramConfiguration& pcfg, uint32_t flags) {
|
||||||
@@ -756,7 +748,7 @@ namespace randomx {
|
|||||||
template void JitCompilerX86::genAddressReg<true>(const Instruction& instr, const uint32_t src, uint8_t* code, uint32_t& codePos);
|
template void JitCompilerX86::genAddressReg<true>(const Instruction& instr, const uint32_t src, uint8_t* code, uint32_t& codePos);
|
||||||
|
|
||||||
FORCE_INLINE void JitCompilerX86::genAddressRegDst(const Instruction& instr, uint8_t* code, uint32_t& codePos) {
|
FORCE_INLINE void JitCompilerX86::genAddressRegDst(const Instruction& instr, uint8_t* code, uint32_t& codePos) {
|
||||||
const uint32_t dst = static_cast<uint32_t>(instr.dst) << 16;
|
const uint32_t dst = static_cast<uint32_t>(instr.dst % RegistersCount) << 16;
|
||||||
*(uint32_t*)(code + codePos) = 0x24808d41 + dst;
|
*(uint32_t*)(code + codePos) = 0x24808d41 + dst;
|
||||||
codePos += (dst == (RegisterNeedsSib << 16)) ? 4 : 3;
|
codePos += (dst == (RegisterNeedsSib << 16)) ? 4 : 3;
|
||||||
|
|
||||||
@@ -776,8 +768,8 @@ namespace randomx {
|
|||||||
uint32_t pos = codePos;
|
uint32_t pos = codePos;
|
||||||
uint8_t* const p = code + pos;
|
uint8_t* const p = code + pos;
|
||||||
|
|
||||||
const uint32_t dst = instr.dst;
|
const uint32_t dst = instr.dst % RegistersCount;
|
||||||
const uint32_t sib = (instr.getModShift() << 6) | (instr.src << 3) | dst;
|
const uint32_t sib = (instr.getModShift() << 6) | ((instr.src % RegistersCount) << 3) | dst;
|
||||||
|
|
||||||
uint32_t k = 0x048d4f + (dst << 19);
|
uint32_t k = 0x048d4f + (dst << 19);
|
||||||
if (dst == RegisterNeedsDisplacement)
|
if (dst == RegisterNeedsDisplacement)
|
||||||
@@ -796,8 +788,8 @@ namespace randomx {
|
|||||||
uint8_t* const p = code;
|
uint8_t* const p = code;
|
||||||
uint32_t pos = codePos;
|
uint32_t pos = codePos;
|
||||||
|
|
||||||
const uint32_t src = instr.src;
|
const uint32_t src = instr.src % RegistersCount;
|
||||||
const uint32_t dst = instr.dst;
|
const uint32_t dst = instr.dst % RegistersCount;
|
||||||
|
|
||||||
if (src != dst) {
|
if (src != dst) {
|
||||||
genAddressReg<true>(instr, src, p, pos);
|
genAddressReg<true>(instr, src, p, pos);
|
||||||
@@ -817,8 +809,8 @@ namespace randomx {
|
|||||||
uint8_t* const p = code;
|
uint8_t* const p = code;
|
||||||
uint32_t pos = codePos;
|
uint32_t pos = codePos;
|
||||||
|
|
||||||
const uint32_t src = instr.src;
|
const uint32_t src = instr.src % RegistersCount;
|
||||||
const uint32_t dst = instr.dst;
|
const uint32_t dst = instr.dst % RegistersCount;
|
||||||
|
|
||||||
if (src != dst) {
|
if (src != dst) {
|
||||||
*(uint32_t*)(p + pos) = 0xc02b4d + (dst << 19) + (src << 16);
|
*(uint32_t*)(p + pos) = 0xc02b4d + (dst << 19) + (src << 16);
|
||||||
@@ -838,8 +830,8 @@ namespace randomx {
|
|||||||
uint8_t* const p = code;
|
uint8_t* const p = code;
|
||||||
uint32_t pos = codePos;
|
uint32_t pos = codePos;
|
||||||
|
|
||||||
const uint32_t src = instr.src;
|
const uint32_t src = instr.src % RegistersCount;
|
||||||
const uint32_t dst = instr.dst;
|
const uint32_t dst = instr.dst % RegistersCount;
|
||||||
|
|
||||||
if (src != dst) {
|
if (src != dst) {
|
||||||
genAddressReg<true>(instr, src, p, pos);
|
genAddressReg<true>(instr, src, p, pos);
|
||||||
@@ -859,8 +851,8 @@ namespace randomx {
|
|||||||
uint8_t* const p = code;
|
uint8_t* const p = code;
|
||||||
uint32_t pos = codePos;
|
uint32_t pos = codePos;
|
||||||
|
|
||||||
const uint32_t src = instr.src;
|
const uint32_t src = instr.src % RegistersCount;
|
||||||
const uint32_t dst = instr.dst;
|
const uint32_t dst = instr.dst % RegistersCount;
|
||||||
|
|
||||||
if (src != dst) {
|
if (src != dst) {
|
||||||
emit32(0xc0af0f4d + ((dst * 8 + src) << 24), p, pos);
|
emit32(0xc0af0f4d + ((dst * 8 + src) << 24), p, pos);
|
||||||
@@ -879,8 +871,8 @@ namespace randomx {
|
|||||||
uint8_t* const p = code;
|
uint8_t* const p = code;
|
||||||
uint32_t pos = codePos;
|
uint32_t pos = codePos;
|
||||||
|
|
||||||
const uint64_t src = instr.src;
|
const uint64_t src = instr.src % RegistersCount;
|
||||||
const uint64_t dst = instr.dst;
|
const uint64_t dst = instr.dst % RegistersCount;
|
||||||
|
|
||||||
if (src != dst) {
|
if (src != dst) {
|
||||||
genAddressReg<true>(instr, src, p, pos);
|
genAddressReg<true>(instr, src, p, pos);
|
||||||
@@ -900,8 +892,8 @@ namespace randomx {
|
|||||||
uint8_t* const p = code;
|
uint8_t* const p = code;
|
||||||
uint32_t pos = codePos;
|
uint32_t pos = codePos;
|
||||||
|
|
||||||
const uint32_t src = instr.src;
|
const uint32_t src = instr.src % RegistersCount;
|
||||||
const uint32_t dst = instr.dst;
|
const uint32_t dst = instr.dst % RegistersCount;
|
||||||
|
|
||||||
*(uint32_t*)(p + pos) = 0xc08b49 + (dst << 16);
|
*(uint32_t*)(p + pos) = 0xc08b49 + (dst << 16);
|
||||||
*(uint32_t*)(p + pos + 3) = 0xe0f749 + (src << 16);
|
*(uint32_t*)(p + pos + 3) = 0xe0f749 + (src << 16);
|
||||||
@@ -916,8 +908,8 @@ namespace randomx {
|
|||||||
uint8_t* const p = code;
|
uint8_t* const p = code;
|
||||||
uint32_t pos = codePos;
|
uint32_t pos = codePos;
|
||||||
|
|
||||||
const uint32_t src = instr.src;
|
const uint32_t src = instr.src % RegistersCount;
|
||||||
const uint32_t dst = instr.dst;
|
const uint32_t dst = instr.dst % RegistersCount;
|
||||||
|
|
||||||
*(uint32_t*)(p + pos) = 0xC4D08B49 + (dst << 16);
|
*(uint32_t*)(p + pos) = 0xC4D08B49 + (dst << 16);
|
||||||
*(uint32_t*)(p + pos + 4) = 0xC0F6FB42 + (dst << 27) + (src << 24);
|
*(uint32_t*)(p + pos + 4) = 0xC0F6FB42 + (dst << 27) + (src << 24);
|
||||||
@@ -931,8 +923,8 @@ namespace randomx {
|
|||||||
uint8_t* const p = code;
|
uint8_t* const p = code;
|
||||||
uint32_t pos = codePos;
|
uint32_t pos = codePos;
|
||||||
|
|
||||||
const uint64_t src = instr.src;
|
const uint64_t src = instr.src % RegistersCount;
|
||||||
const uint64_t dst = instr.dst;
|
const uint64_t dst = instr.dst % RegistersCount;
|
||||||
|
|
||||||
if (src != dst) {
|
if (src != dst) {
|
||||||
genAddressReg<false>(instr, src, p, pos);
|
genAddressReg<false>(instr, src, p, pos);
|
||||||
@@ -955,8 +947,8 @@ namespace randomx {
|
|||||||
uint8_t* const p = code;
|
uint8_t* const p = code;
|
||||||
uint32_t pos = codePos;
|
uint32_t pos = codePos;
|
||||||
|
|
||||||
const uint64_t src = instr.src;
|
const uint64_t src = instr.src % RegistersCount;
|
||||||
const uint64_t dst = instr.dst;
|
const uint64_t dst = instr.dst % RegistersCount;
|
||||||
|
|
||||||
if (src != dst) {
|
if (src != dst) {
|
||||||
genAddressReg<false>(instr, src, p, pos);
|
genAddressReg<false>(instr, src, p, pos);
|
||||||
@@ -978,8 +970,8 @@ namespace randomx {
|
|||||||
uint8_t* const p = code;
|
uint8_t* const p = code;
|
||||||
uint32_t pos = codePos;
|
uint32_t pos = codePos;
|
||||||
|
|
||||||
const uint64_t src = instr.src;
|
const uint64_t src = instr.src % RegistersCount;
|
||||||
const uint64_t dst = instr.dst;
|
const uint64_t dst = instr.dst % RegistersCount;
|
||||||
|
|
||||||
*(uint64_t*)(p + pos) = 0x8b4ce8f749c08b49ull + (dst << 16) + (src << 40);
|
*(uint64_t*)(p + pos) = 0x8b4ce8f749c08b49ull + (dst << 16) + (src << 40);
|
||||||
pos += 8;
|
pos += 8;
|
||||||
@@ -993,8 +985,8 @@ namespace randomx {
|
|||||||
uint8_t* const p = code;
|
uint8_t* const p = code;
|
||||||
uint32_t pos = codePos;
|
uint32_t pos = codePos;
|
||||||
|
|
||||||
const uint64_t src = instr.src;
|
const uint64_t src = instr.src % RegistersCount;
|
||||||
const uint64_t dst = instr.dst;
|
const uint64_t dst = instr.dst % RegistersCount;
|
||||||
|
|
||||||
if (src != dst) {
|
if (src != dst) {
|
||||||
genAddressReg<false>(instr, src, p, pos);
|
genAddressReg<false>(instr, src, p, pos);
|
||||||
@@ -1019,7 +1011,7 @@ namespace randomx {
|
|||||||
|
|
||||||
uint64_t divisor = instr.getImm32();
|
uint64_t divisor = instr.getImm32();
|
||||||
if (!isZeroOrPowerOf2(divisor)) {
|
if (!isZeroOrPowerOf2(divisor)) {
|
||||||
const uint32_t dst = instr.dst;
|
const uint32_t dst = instr.dst % RegistersCount;
|
||||||
|
|
||||||
const uint64_t reciprocal = randomx_reciprocal_fast(divisor);
|
const uint64_t reciprocal = randomx_reciprocal_fast(divisor);
|
||||||
if (imul_rcp_storage_used < 16) {
|
if (imul_rcp_storage_used < 16) {
|
||||||
@@ -1048,7 +1040,7 @@ namespace randomx {
|
|||||||
uint8_t* const p = code;
|
uint8_t* const p = code;
|
||||||
uint32_t pos = codePos;
|
uint32_t pos = codePos;
|
||||||
|
|
||||||
const uint32_t dst = instr.dst;
|
const uint32_t dst = instr.dst % RegistersCount;
|
||||||
*(uint32_t*)(p + pos) = 0xd8f749 + (dst << 16);
|
*(uint32_t*)(p + pos) = 0xd8f749 + (dst << 16);
|
||||||
pos += 3;
|
pos += 3;
|
||||||
|
|
||||||
@@ -1060,8 +1052,8 @@ namespace randomx {
|
|||||||
uint8_t* const p = code;
|
uint8_t* const p = code;
|
||||||
uint32_t pos = codePos;
|
uint32_t pos = codePos;
|
||||||
|
|
||||||
const uint64_t src = instr.src;
|
const uint64_t src = instr.src % RegistersCount;
|
||||||
const uint64_t dst = instr.dst;
|
const uint64_t dst = instr.dst % RegistersCount;
|
||||||
|
|
||||||
if (src != dst) {
|
if (src != dst) {
|
||||||
*(uint32_t*)(p + pos) = 0xc0334d + (((dst << 3) + src) << 16);
|
*(uint32_t*)(p + pos) = 0xc0334d + (((dst << 3) + src) << 16);
|
||||||
@@ -1081,8 +1073,8 @@ namespace randomx {
|
|||||||
uint8_t* const p = code;
|
uint8_t* const p = code;
|
||||||
uint32_t pos = codePos;
|
uint32_t pos = codePos;
|
||||||
|
|
||||||
const uint64_t src = instr.src;
|
const uint64_t src = instr.src % RegistersCount;
|
||||||
const uint64_t dst = instr.dst;
|
const uint64_t dst = instr.dst % RegistersCount;
|
||||||
|
|
||||||
if (src != dst) {
|
if (src != dst) {
|
||||||
genAddressReg<true>(instr, src, p, pos);
|
genAddressReg<true>(instr, src, p, pos);
|
||||||
@@ -1102,8 +1094,8 @@ namespace randomx {
|
|||||||
uint8_t* const p = code;
|
uint8_t* const p = code;
|
||||||
uint32_t pos = codePos;
|
uint32_t pos = codePos;
|
||||||
|
|
||||||
const uint64_t src = instr.src;
|
const uint64_t src = instr.src % RegistersCount;
|
||||||
const uint64_t dst = instr.dst;
|
const uint64_t dst = instr.dst % RegistersCount;
|
||||||
|
|
||||||
if (src != dst) {
|
if (src != dst) {
|
||||||
*(uint64_t*)(p + pos) = 0xc8d349c88b41ull + (src << 16) + (dst << 40);
|
*(uint64_t*)(p + pos) = 0xc8d349c88b41ull + (src << 16) + (dst << 40);
|
||||||
@@ -1123,8 +1115,8 @@ namespace randomx {
|
|||||||
uint8_t* const p = code;
|
uint8_t* const p = code;
|
||||||
uint32_t pos = codePos;
|
uint32_t pos = codePos;
|
||||||
|
|
||||||
const uint64_t src = instr.src;
|
const uint64_t src = instr.src % RegistersCount;
|
||||||
const uint64_t dst = instr.dst;
|
const uint64_t dst = instr.dst % RegistersCount;
|
||||||
|
|
||||||
if (src != dst) {
|
if (src != dst) {
|
||||||
*(uint64_t*)(p + pos) = 0xc0d349c88b41ull + (src << 16) + (dst << 40);
|
*(uint64_t*)(p + pos) = 0xc0d349c88b41ull + (src << 16) + (dst << 40);
|
||||||
@@ -1144,8 +1136,8 @@ namespace randomx {
|
|||||||
uint8_t* const p = code;
|
uint8_t* const p = code;
|
||||||
uint32_t pos = codePos;
|
uint32_t pos = codePos;
|
||||||
|
|
||||||
const uint32_t src = instr.src;
|
const uint32_t src = instr.src % RegistersCount;
|
||||||
const uint32_t dst = instr.dst;
|
const uint32_t dst = instr.dst % RegistersCount;
|
||||||
|
|
||||||
if (src != dst) {
|
if (src != dst) {
|
||||||
*(uint32_t*)(p + pos) = 0xc0874d + (((dst << 3) + src) << 16);
|
*(uint32_t*)(p + pos) = 0xc0874d + (((dst << 3) + src) << 16);
|
||||||
@@ -1161,7 +1153,7 @@ namespace randomx {
|
|||||||
uint8_t* const p = code;
|
uint8_t* const p = code;
|
||||||
uint32_t pos = codePos;
|
uint32_t pos = codePos;
|
||||||
|
|
||||||
const uint64_t dst = instr.dst;
|
const uint64_t dst = instr.dst % RegistersCount;
|
||||||
|
|
||||||
*(uint64_t*)(p + pos) = 0x01c0c60f66ull + (((dst << 3) + dst) << 24);
|
*(uint64_t*)(p + pos) = 0x01c0c60f66ull + (((dst << 3) + dst) << 24);
|
||||||
pos += 5;
|
pos += 5;
|
||||||
@@ -1190,7 +1182,7 @@ namespace randomx {
|
|||||||
|
|
||||||
prevFPOperation = pos;
|
prevFPOperation = pos;
|
||||||
|
|
||||||
const uint32_t src = instr.src;
|
const uint32_t src = instr.src % RegistersCount;
|
||||||
const uint32_t dst = instr.dst % RegisterCountFlt;
|
const uint32_t dst = instr.dst % RegisterCountFlt;
|
||||||
|
|
||||||
genAddressReg<true>(instr, src, p, pos);
|
genAddressReg<true>(instr, src, p, pos);
|
||||||
@@ -1222,7 +1214,7 @@ namespace randomx {
|
|||||||
|
|
||||||
prevFPOperation = pos;
|
prevFPOperation = pos;
|
||||||
|
|
||||||
const uint32_t src = instr.src;
|
const uint32_t src = instr.src % RegistersCount;
|
||||||
const uint32_t dst = instr.dst % RegisterCountFlt;
|
const uint32_t dst = instr.dst % RegisterCountFlt;
|
||||||
|
|
||||||
genAddressReg<true>(instr, src, p, pos);
|
genAddressReg<true>(instr, src, p, pos);
|
||||||
@@ -1265,7 +1257,7 @@ namespace randomx {
|
|||||||
|
|
||||||
prevFPOperation = pos;
|
prevFPOperation = pos;
|
||||||
|
|
||||||
const uint32_t src = instr.src;
|
const uint32_t src = instr.src % RegistersCount;
|
||||||
const uint64_t dst = instr.dst % RegisterCountFlt;
|
const uint64_t dst = instr.dst % RegisterCountFlt;
|
||||||
|
|
||||||
genAddressReg<true>(instr, src, p, pos);
|
genAddressReg<true>(instr, src, p, pos);
|
||||||
@@ -1315,7 +1307,7 @@ namespace randomx {
|
|||||||
uint32_t pos = codePos;
|
uint32_t pos = codePos;
|
||||||
prevCFROUND = pos;
|
prevCFROUND = pos;
|
||||||
|
|
||||||
const uint32_t src = instr.src;
|
const uint32_t src = instr.src % RegistersCount;
|
||||||
|
|
||||||
*(uint32_t*)(p + pos) = 0x00C08B49 + (src << 16);
|
*(uint32_t*)(p + pos) = 0x00C08B49 + (src << 16);
|
||||||
const int rotate = (static_cast<int>(instr.getImm32() & 63) - 2) & 63;
|
const int rotate = (static_cast<int>(instr.getImm32() & 63) - 2) & 63;
|
||||||
@@ -1351,7 +1343,7 @@ namespace randomx {
|
|||||||
uint32_t pos = codePos;
|
uint32_t pos = codePos;
|
||||||
prevCFROUND = pos;
|
prevCFROUND = pos;
|
||||||
|
|
||||||
const uint64_t src = instr.src;
|
const uint64_t src = instr.src % RegistersCount;
|
||||||
|
|
||||||
const uint64_t rotate = (static_cast<int>(instr.getImm32() & 63) - 2) & 63;
|
const uint64_t rotate = (static_cast<int>(instr.getImm32() & 63) - 2) & 63;
|
||||||
*(uint64_t*)(p + pos) = 0xC0F0FBC3C4ULL | (src << 32) | (rotate << 40);
|
*(uint64_t*)(p + pos) = 0xC0F0FBC3C4ULL | (src << 32) | (rotate << 40);
|
||||||
@@ -1375,7 +1367,7 @@ namespace randomx {
|
|||||||
uint8_t* const p = code;
|
uint8_t* const p = code;
|
||||||
uint32_t pos = codePos;
|
uint32_t pos = codePos;
|
||||||
|
|
||||||
const int reg = instr.dst;
|
const int reg = instr.dst % RegistersCount;
|
||||||
int32_t jmp_offset = registerUsage[reg];
|
int32_t jmp_offset = registerUsage[reg];
|
||||||
|
|
||||||
// if it jumps over the previous FP instruction that uses rounding, treat it as if FP instruction happened now
|
// if it jumps over the previous FP instruction that uses rounding, treat it as if FP instruction happened now
|
||||||
@@ -1434,7 +1426,7 @@ namespace randomx {
|
|||||||
uint32_t pos = codePos;
|
uint32_t pos = codePos;
|
||||||
|
|
||||||
genAddressRegDst(instr, p, pos);
|
genAddressRegDst(instr, p, pos);
|
||||||
emit32(0x0604894c + (static_cast<uint32_t>(instr.src) << 19), p, pos);
|
emit32(0x0604894c + (static_cast<uint32_t>(instr.src % RegistersCount) << 19), p, pos);
|
||||||
|
|
||||||
codePos = pos;
|
codePos = pos;
|
||||||
}
|
}
|
||||||
|
|||||||
@@ -22,7 +22,7 @@
|
|||||||
#define APP_ID "xmrig"
|
#define APP_ID "xmrig"
|
||||||
#define APP_NAME "XMRig"
|
#define APP_NAME "XMRig"
|
||||||
#define APP_DESC "XMRig miner"
|
#define APP_DESC "XMRig miner"
|
||||||
#define APP_VERSION "6.19.3"
|
#define APP_VERSION "6.19.3-dev"
|
||||||
#define APP_DOMAIN "xmrig.com"
|
#define APP_DOMAIN "xmrig.com"
|
||||||
#define APP_SITE "www.xmrig.com"
|
#define APP_SITE "www.xmrig.com"
|
||||||
#define APP_COPYRIGHT "Copyright (C) 2016-2023 xmrig.com"
|
#define APP_COPYRIGHT "Copyright (C) 2016-2023 xmrig.com"
|
||||||
|
|||||||
Reference in New Issue
Block a user