v6.2.1

Fixed NiceHash disconnects for KawPow

.github/ISSUE_TEMPLATE/bug_report.md

@@ -0,0 +1,26 @@
+---
+name: Bug report
+about: Create a report to help us improve
+title: ''
+labels: ''
+assignees: ''
+
+---
+
+**Describe the bug**
+A clear and concise description of what the bug is.
+
+**To Reproduce**
+Steps to reproduce the behavior.
+
+**Expected behavior**
+A clear and concise description of what you expected to happen.
+
+**Required data**
+ - Miner log as text or screenshot
+ - Config file or command line (without wallets)
+ - OS: [e.g. Windows]
+ - For GPU related issues: information about GPUs and driver version.
+
+**Additional context**
+Add any other context about the problem here.

.gitignore

@@ -1,2 +1,4 @@
 /build
 /CMakeLists.txt.user
+/.idea
+/src/backend/opencl/cl/cn/cryptonight_gen.cl

CHANGELOG.md

@@ -1,128 +1,193 @@
-# v2.5.0
-- [#434](https://github.com/xmrig/xmrig/issues/434) **Added support for Monero v7 PoW, scheduled on March 28.**
-- Added full IPv6 support.
-- Added protocol extension, when use the miner with xmrig-proxy 2.5+ no more need manually specify `nicehash` option.
-- [#123](https://github.com/xmrig/xmrig-proxy/issues/123) Fixed regression (all versions since 2.4 affected) fragmented responses from pool/proxy was parsed incorrectly.
-- [#428](https://github.com/xmrig/xmrig/issues/428) Fixed regression (version 2.4.5 affected) with CPU cache size detection.
+# v6.2.1
+- [#1728](https://github.com/xmrig/xmrig/issues/1728) Fixed, 32 bit Windows builds was crash on start.
+- [#1729](https://github.com/xmrig/xmrig/pull/1729) Fixed KawPow crash on old CPUs.
+- [#1730](https://github.com/xmrig/xmrig/pull/1730) Improved displaying information for compute errors on GPUs.
+- [#1732](https://github.com/xmrig/xmrig/pull/1732) Fixed NiceHash disconnects for KawPow.
+- Fixed AMD GPU health (temperatures/power/clocks/fans) readings on Linux.
 
-# v2.4.5
-- [#324](https://github.com/xmrig/xmrig/pull/324) Fixed build without libmicrohttpd (CMake cache issue).
-- [#341](https://github.com/xmrig/xmrig/issues/341) Fixed wrong exit code and added command line option `--dry-run`.
-- [#385](https://github.com/xmrig/xmrig/pull/385) Up to 20% performance increase for non-AES CPU and fixed Intel Core 2 cache detection.
+# v6.2.0-beta
+- [#1717](https://github.com/xmrig/xmrig/pull/1717) Added new algorithm `cn/ccx` for Conceal.
+- [#1718](https://github.com/xmrig/xmrig/pull/1718) Fixed, linker on Linux was marking entire executable as having an executable stack.
+- [#1720](https://github.com/xmrig/xmrig/pull/1720) Fixed broken CryptoNight algorithms family with gcc 10.1.
 
-# v2.4.4
- - Added libmicrohttpd version to --version output.
- - Fixed bug in singal handler, in some cases miner wasn't shutdown properly.
- - Fixed recent MSVC 2017 version detection.
- - [#279](https://github.com/xmrig/xmrig/pull/279) Fixed build on some macOS versions.
+# v6.0.1-beta
+- [#1708](https://github.com/xmrig/xmrig/issues/1708) Added `title` option.
+- [#1711](https://github.com/xmrig/xmrig/pull/1711) [cuda] Print errors from KawPow DAG initialization.
+- [#1713](https://github.com/xmrig/xmrig/pull/1713) [cuda] Reduced memory usage for KawPow, minimum CUDA plugin version now is 6.1.0.
 
-# v2.4.3
- - [#94](https://github.com/xmrig/xmrig/issues/94#issuecomment-342019257) [#216](https://github.com/xmrig/xmrig/issues/216) Added **ARMv8** and **ARMv7** support. Hardware AES supported, thanks [Imran Yusuff](https://github.com/imranyusuff).
- - [#157](https://github.com/xmrig/xmrig/issues/157) [#196](https://github.com/xmrig/xmrig/issues/196) Fixed Linux compile issues.
- - [#184](https://github.com/xmrig/xmrig/issues/184) Fixed cache size detection for CPUs with disabled Hyper-Threading.
- - [#200](https://github.com/xmrig/xmrig/issues/200) In some cases miner was doesn't write log to stdout.
+# v6.0.0-beta
+- [#1694](https://github.com/xmrig/xmrig/pull/1694) Added support for KawPow algorithm (Ravencoin) on AMD/NVIDIA.
+- Removed previously deprecated `cn/gpu` algorithm.
+- Default donation level reduced to 1% but you still can increase it if you like.
 
-# v2.4.2
- - [#60](https://github.com/xmrig/xmrig/issues/60) Added FreeBSD support, thanks [vcambur](https://github.com/vcambur).
- - [#153](https://github.com/xmrig/xmrig/issues/153) Fixed issues with dwarfpool.com.
+# v5.11.3
+- [#1718](https://github.com/xmrig/xmrig/pull/1718) Fixed, linker on Linux was marking entire executable as having an executable stack.
+- [#1720](https://github.com/xmrig/xmrig/pull/1720) Fixed broken CryptoNight algorithms family with gcc 10.1.
 
-# v2.4.1
-  - [#147](https://github.com/xmrig/xmrig/issues/147) Fixed comparability with monero-stratum.
+# v5.11.2
+- [#1664](https://github.com/xmrig/xmrig/pull/1664) Improved JSON config error reporting.
+- [#1668](https://github.com/xmrig/xmrig/pull/1668) Optimized RandomX dataset initialization.
+- [#1675](https://github.com/xmrig/xmrig/pull/1675) Fixed cross-compiling on Linux.
+- Fixed memory leak in HTTP client.
+- Build [dependencies](https://github.com/xmrig/xmrig-deps/releases/tag/v4.1) updated to recent versions.
+- Compiler for Windows gcc builds updated to v10.1.
 
-# v2.4.0
- - Added [HTTP API](https://github.com/xmrig/xmrig/wiki/API).
- - Added comments support in config file.
- - libjansson replaced to rapidjson.
- - [#98](https://github.com/xmrig/xmrig/issues/98) Ignore `keepalive` option with minergate.com and nicehash.com.
- - [#101](https://github.com/xmrig/xmrig/issues/101) Fixed MSVC 2017 (15.3) compile time version detection.
- - [#108](https://github.com/xmrig/xmrig/issues/108) Silently ignore invalid values for `donate-level` option.
- - [#111](https://github.com/xmrig/xmrig/issues/111) Fixed build without AEON support.
+# v5.11.1
+- [#1652](https://github.com/xmrig/xmrig/pull/1652) Up to 1% RandomX perfomance improvement on recent AMD CPUs.
+- [#1306](https://github.com/xmrig/xmrig/issues/1306) Fixed possible double connection to a pool.
+- [#1654](https://github.com/xmrig/xmrig/issues/1654) Fixed build with LibreSSL.
 
-# v2.3.1
-- [#68](https://github.com/xmrig/xmrig/issues/68) Fixed compatibility with Docker containers, was nothing print on console.
+# v5.11.0
+- **[#1632](https://github.com/xmrig/xmrig/pull/1632) Added AstroBWT CUDA support ([CUDA plugin](https://github.com/xmrig/xmrig-cuda) v3.0.0 or newer required).**
+- [#1605](https://github.com/xmrig/xmrig/pull/1605) Fixed AstroBWT OpenCL for NVIDIA GPUs.
+- [#1635](https://github.com/xmrig/xmrig/pull/1635) Added pooled memory allocation of RandomX VMs (+0.5% speedup on Zen2).
+- [#1641](https://github.com/xmrig/xmrig/pull/1641) RandomX JIT refactoring, smaller memory footprint and a bit faster overall.
+- [#1643](https://github.com/xmrig/xmrig/issues/1643) Fixed build on CentOS 7.
 
-# v2.3.0
-- Added `--cpu-priority` option (0 idle, 2 normal to 5 highest).
-- Added `--user-agent` option, to set custom user-agent string for pool. For example `cpuminer-multi/0.1`.
-- Added `--no-huge-pages` option, to disable huge pages support.
-- [#62](https://github.com/xmrig/xmrig/issues/62) Don't send the login to the dev pool.
-- Force reconnect if pool block miner IP address. helps switch to backup pool.
-- Fixed: failed open default config file if path contains non English characters.
-- Fixed: error occurred if try use unavailable stdin or stdout, regression since version 2.2.0.
-- Fixed: message about huge pages support successfully enabled on Windows was not shown in release builds.
+# v5.10.0
+- [#1602](https://github.com/xmrig/xmrig/pull/1602) Added AMD GPUs support for AstroBWT algorithm.
+- [#1590](https://github.com/xmrig/xmrig/pull/1590) MSR mod automatically deactivated after switching from RandomX algorithms.
+- [#1592](https://github.com/xmrig/xmrig/pull/1592) Added AVX2 optimized code for AstroBWT algorithm.
+  - Added new config option `astrobwt-avx2` in `cpu` object and command line option `--astrobwt-avx2`.
+- [#1596](https://github.com/xmrig/xmrig/issues/1596) Major TLS (Transport Layer Security) subsystem update.
+  - Added new TLS options, please check [xmrig-proxy documentation](https://xmrig.com/docs/proxy/tls) for details.
+- `cn/gpu` algorithm now disabled by default and will be removed in next major (v6.x.x) release, no ETA for it right now.
+- Added command line option `--data-dir`.
 
-# v2.2.1
-- Fixed [terminal issues](https://github.com/xmrig/xmrig-proxy/issues/2#issuecomment-319914085) after exit on Linux and OS X.
+# v5.9.0
+- [#1578](https://github.com/xmrig/xmrig/pull/1578) Added new RandomKEVA algorithm for upcoming Kevacoin fork, as `"algo": "rx/keva"` or `"coin": "keva"`.
+- [#1584](https://github.com/xmrig/xmrig/pull/1584) Fixed invalid AstroBWT hashes after algorithm switching.
+- [#1585](https://github.com/xmrig/xmrig/issues/1585) Fixed build without HTTP support.
+- Added command line option `--astrobwt-max-size`.
 
-# v2.2.0
-- [#46](https://github.com/xmrig/xmrig/issues/46) Restored config file support. Now possible use multiple config files and combine with command line options also added support for default config.
-- Improved colors support on Windows, now used uv_tty, legacy code removed.
-- QuickEdit Mode now disabled on Windows.
-- Added interactive commands in console window:: **h**ashrate, **p**ause, **r**esume.
-- Fixed autoconf mode for AMD FX CPUs.
+# v5.8.2
+- [#1580](https://github.com/xmrig/xmrig/pull/1580) AstroBWT algorithm 20-50% speedup.
+  - Added new option `astrobwt-max-size`.
+- [#1581](https://github.com/xmrig/xmrig/issues/1581) Fixed macOS build.
 
-# v2.1.0
-- [#40](https://github.com/xmrig/xmrig/issues/40)
-Improved miner shutdown, fixed crash on exit for Linux and OS X.
-- Fixed, login request was contain malformed JSON if username or password has some special characters for example `\`. 
-- [#220](https://github.com/fireice-uk/xmr-stak-cpu/pull/220) Better support for Round Robin DNS, IP address now always chosen randomly instead of stuck on first one.
-- Changed donation address, new [xmrig-proxy](https://github.com/xmrig/xmrig-proxy) is coming soon.
+# v5.8.1
+- [#1575](https://github.com/xmrig/xmrig/pull/1575) Fixed new block detection for DERO solo mining.
 
-# v2.0.2
-- Better deal with possible duplicate jobs from pool, show warning and ignore duplicates.
-- For Windows builds libuv updated to version 1.13.1 and gcc to 7.1.0.
+# v5.8.0
+- [#1573](https://github.com/xmrig/xmrig/pull/1573) Added new AstroBWT algorithm for upcoming DERO fork, as `"algo": "astrobwt"` or `"coin": "dero"`.
 
-# v2.0.1
- - [#27](https://github.com/xmrig/xmrig/issues/27) Fixed possibility crash on 32bit systems.
+# v5.7.0
+- **Added SOCKS5 proxies support for Tor https://xmrig.com/docs/miner/tor.**
+- [#377](https://github.com/xmrig/xmrig-proxy/issues/377) Fixed duplicate jobs in daemon (solo) mining client.
+- [#1560](https://github.com/xmrig/xmrig/pull/1560) RandomX 0.3-0.4% speedup depending on CPU.
+- Fixed possible crashes in HTTP client.
 
-# v2.0.0
- - Option `--backup-url` removed, instead now possibility specify multiple pools for example: `-o example1.com:3333 -u user1 -p password1 -k -o example2.com:5555 -u user2 -o example3.com:4444 -u user3`
- - [#15](https://github.com/xmrig/xmrig/issues/15) Added option `-l, --log-file=FILE` to write log to file.
- - [#15](https://github.com/xmrig/xmrig/issues/15) Added option `-S, --syslog` to use syslog for logging, Linux only.
- - [#18](https://github.com/xmrig/xmrig/issues/18) Added nice messages for accepted/rejected shares with diff and network latency.
- - [#20](https://github.com/xmrig/xmrig/issues/20) Fixed `--cpu-affinity` for more than 32 threads.
- - Fixed Windows XP support.
- - Fixed regression, option `--no-color` was not fully disable colored output.
- - Show resolved pool IP address in miner output.
+# v5.6.0
+- [#1536](https://github.com/xmrig/xmrig/pull/1536) Added workaround for new AMD GPU drivers.
+- [#1546](https://github.com/xmrig/xmrig/pull/1546) Fixed generic OpenCL code for AMD Navi GPUs.
+- [#1551](https://github.com/xmrig/xmrig/pull/1551) Added RandomX JIT for AMD Navi  GPUs.
+- Added health information for AMD GPUs (clocks/power/fan/temperature) via ADL (Windows) and sysfs (Linux).
+- Fixed possible nicehash nonce overflow in some conditions.
+- Fixed wrong OpenCL platform on macOS, option `platform` now ignored on this OS.
 
-# v1.0.1
-- Fix broken software AES implementation, app has crashed if CPU not support AES-NI, only version 1.0.0 affected.
+# v5.5.3
+- [#1529](https://github.com/xmrig/xmrig/pull/1529) Fixed crash on Bulldozer CPUs.
 
-# v1.0.0
-- Miner complete rewritten in C++ with libuv.
-- This version should be fully compatible (except config file) with previos versions, many new nice features will come in next versions.
-- This is still beta. If you found regression, stability or perfomance issues or have an idea for new feature please fell free to open new [issue](https://github.com/xmrig/xmrig/issues/new).
-- Added new option `--print-time=N`, print hashrate report every N seconds.
-- New hashrate reports, by default every 60 secons.
-- Added Microsoft Visual C++ 2015 and 2017 support.
-- Removed dependency on libcurl.
-- To compile this version from source please switch to [dev](https://github.com/xmrig/xmrig/tree/dev) branch.
+# v5.5.2
+- [#1500](https://github.com/xmrig/xmrig/pull/1500) Removed unnecessary code from RandomX JIT compiler.
+- [#1502](https://github.com/xmrig/xmrig/pull/1502) Optimizations for AMD Bulldozer.
+- [#1508](https://github.com/xmrig/xmrig/pull/1508) Added support for BMI2 instructions.
+- [#1510](https://github.com/xmrig/xmrig/pull/1510) Optimized `CFROUND` instruction for RandomX.
+- [#1520](https://github.com/xmrig/xmrig/pull/1520) Fixed thread affinity.
 
-# v0.8.2
-- Fixed L2 cache size detection for AMD CPUs (Bulldozer/Piledriver/Steamroller/Excavator architecture).
+# v5.5.1
+- [#1469](https://github.com/xmrig/xmrig/issues/1469) Fixed build with gcc 4.8.
+- [#1473](https://github.com/xmrig/xmrig/pull/1473) Added RandomX auto-config for mobile Ryzen APUs.
+- [#1477](https://github.com/xmrig/xmrig/pull/1477) Fixed build with Clang.
+- [#1489](https://github.com/xmrig/xmrig/pull/1489) RandomX JIT compiler tweaks.
+- [#1493](https://github.com/xmrig/xmrig/pull/1493) Default value for Intel MSR preset changed to `15`.
+- Fixed unwanted resume after RandomX dataset change.
 
-# v0.8.2
-- Fixed L2 cache size detection for AMD CPUs (Bulldozer/Piledriver/Steamroller/Excavator architecture).
-- Fixed gcc 7.1 support.
+# v5.5.0
+- [#179](https://github.com/xmrig/xmrig/issues/179) Added support for [environment variables](https://xmrig.com/docs/miner/environment-variables) in config file.
+- [#1445](https://github.com/xmrig/xmrig/pull/1445) Removed `rx/v` algorithm.
+- [#1453](https://github.com/xmrig/xmrig/issues/1453) Fixed crash on 32bit systems.
+- [#1459](https://github.com/xmrig/xmrig/issues/1459) Fixed crash on very low memory systems.
+- [#1465](https://github.com/xmrig/xmrig/pull/1465) Added fix for 1st-gen Ryzen crashes.
+- [#1466](https://github.com/xmrig/xmrig/pull/1466) Added `cn-pico/tlo` algorithm.
+- Added `--randomx-no-rdmsr` command line option.
+- Added console title for Windows with miner name and version.
+- On Windows `priority` option now also change base priority.
 
-# v0.8.1
-- Added nicehash support, detects automaticaly by pool URL, for example `cryptonight.eu.nicehash.com:3355` or manually via option `--nicehash`.
+# v5.4.0
+- [#1434](https://github.com/xmrig/xmrig/pull/1434) Added RandomSFX (`rx/sfx`) algorithm for Safex Cash.
+- [#1445](https://github.com/xmrig/xmrig/pull/1445) Added RandomV (`rx/v`) algorithm for *new* MoneroV.
+- [#1419](https://github.com/xmrig/xmrig/issues/1419) Added reverting MSR changes on miner exit, use `"rdmsr": false,` in `"randomx"` object to disable this feature.
+- [#1423](https://github.com/xmrig/xmrig/issues/1423) Fixed conflicts with exists WinRing0 driver service.
+- [#1425](https://github.com/xmrig/xmrig/issues/1425) Fixed crash on first generation Zen CPUs (MSR mod accidentally enable Opcache), additionally now you can disable Opcache and enable MSR mod via config `"wrmsr": ["0xc0011020:0x0", "0xc0011021:0x60", "0xc0011022:0x510000", "0xc001102b:0x1808cc16"],`.
+- Added advanced usage for `wrmsr` option, for example: `"wrmsr": ["0x1a4:0x6"],` (Intel) and `"wrmsr": ["0xc0011020:0x0", "0xc0011021:0x40:0xffffffffffffffdf", "0xc0011022:0x510000", "0xc001102b:0x1808cc16"],` (Ryzen).
+- Added new config option `"verbose"` and command line option `--verbose`.
 
-# v0.8.0
-- Added double hash mode, also known as lower power mode. `--av=2` and `--av=4`.
-- Added smart automatic CPU configuration. Default threads count now depends on size of the L3 cache of CPU.
-- Added CryptoNight-Lite support for AEON `-a cryptonight-lite`.
-- Added `--max-cpu-usage` option for auto CPU configuration mode.
-- Added `--safe` option for adjust threads and algorithm variations to current CPU.
-- No more manual steps to enable huge pages on Windows. XMRig will do it automatically.
-- Removed BMI2 algorithm variation.
-- Removed default pool URL.
+# v5.3.0
+- [#1414](https://github.com/xmrig/xmrig/pull/1414) Added native MSR support for Windows, by using signed **WinRing0 driver** (© 2007-2009 OpenLibSys.org).
+- Added new [MSR documentation](https://xmrig.com/docs/miner/randomx-optimization-guide/msr).
+- [#1418](https://github.com/xmrig/xmrig/pull/1418) Increased stratum send buffer size.
 
-# v0.6.0
-- Added automatic cryptonight self test.
-- New software AES algorithm variation. Will be automatically selected if cpu not support AES-NI.
-- Added 32 bit builds.
-- Documented [algorithm variations](https://github.com/xmrig/xmrig#algorithm-variations).
+# v5.2.1
+- [#1408](https://github.com/xmrig/xmrig/pull/1408) Added RandomX boost script for Linux (if you don't like run miner with root privileges).
+- Added support for [AMD Ryzen MSR registers](https://www.reddit.com/r/MoneroMining/comments/e962fu/9526_hs_on_ryzen_7_3700x_xmrig_520_1gb_pages_msr/) (Linux only).
+- Fixed command line option `--randomx-wrmsr` option without parameters.
 
-# v0.5.0
-- Initial public release.
+# v5.2.0
+- **[#1388](https://github.com/xmrig/xmrig/pull/1388) Added [1GB huge pages support](https://xmrig.com/docs/miner/hugepages#onegb-huge-pages) for Linux.**
+  - Added new option `1gb-pages` in `randomx` object with command line equivalent `--randomx-1gb-pages`.
+  - Added automatic huge pages configuration on Linux if use the miner with root privileges.
+- **Added [automatic Intel prefetchers configuration](https://xmrig.com/docs/miner/randomx-optimization-guide#intel-specific-optimizations) on Linux.**
+   - Added new option `wrmsr` in `randomx` object with command line equivalent `--randomx-wrmsr=6`.
+- [#1396](https://github.com/xmrig/xmrig/pull/1396) [#1401](https://github.com/xmrig/xmrig/pull/1401) New performance optimizations for Ryzen CPUs. 
+- [#1385](https://github.com/xmrig/xmrig/issues/1385) Added `max-threads-hint` option support for RandomX dataset initialization threads.  
+- [#1386](https://github.com/xmrig/xmrig/issues/1386) Added `priority` option support for RandomX dataset initialization threads. 
+- For official builds all dependencies (libuv, hwloc, openssl) updated to recent versions.
+- Windows `msvc` builds now use Visual Studio 2019 instead of 2017.
+
+# v5.1.1
+- [#1365](https://github.com/xmrig/xmrig/issues/1365) Fixed various system response/stability issues.
+  - Added new CPU option `yield` and command line equivalent `--cpu-no-yield`.
+- [#1363](https://github.com/xmrig/xmrig/issues/1363) Fixed wrong priority of main miner thread.
+
+# v5.1.0
+- [#1351](https://github.com/xmrig/xmrig/pull/1351) RandomX optimizations and fixes.
+  - Improved RandomX performance (up to +6-7% on Intel CPUs, +2-3% on Ryzen CPUs)
+  - Added workaround for Intel JCC erratum bug see https://www.phoronix.com/scan.php?page=article&item=intel-jcc-microcode&num=1 for details.
+  - Note! Always disable "Hardware prefetcher" and "Adjacent cacheline prefetch" in BIOS for Intel CPUs to get the optimal RandomX performance.
+- [#1307](https://github.com/xmrig/xmrig/issues/1307) Fixed mining resume after donation round for pools with `self-select` feature.
+- [#1318](https://github.com/xmrig/xmrig/issues/1318#issuecomment-559676080) Added option `"mode"` (or `--randomx-mode`) for RandomX.
+  - Added memory information on miner startup.
+  - Added `resources` field to summary API with memory information and load average.
+
+# v5.0.1
+- [#1234](https://github.com/xmrig/xmrig/issues/1234) Fixed compatibility with some AMD GPUs.
+- [#1284](https://github.com/xmrig/xmrig/issues/1284) Fixed build without RandomX.
+- [#1285](https://github.com/xmrig/xmrig/issues/1285) Added command line options `--cuda-bfactor-hint` and `--cuda-bsleep-hint`.
+- [#1290](https://github.com/xmrig/xmrig/pull/1290) Fixed 32-bit ARM compilation.
+
+# v5.0.0
+This version is first stable unified 3 in 1 GPU+CPU release, OpenCL support built in in miner and not require additional external dependencies on compile time, NVIDIA CUDA available as external [CUDA plugin](https://github.com/xmrig/xmrig-cuda), for convenient, 3 in 1 downloads with recent CUDA version also provided.
+
+This release based on 4.x.x series and include all features from v4.6.2-beta, changelog below include only the most important changes, [full changelog](doc/CHANGELOG_OLD.md) available separately.
+
+- [#1272](https://github.com/xmrig/xmrig/pull/1272) Optimized hashrate calculation.
+- [#1263](https://github.com/xmrig/xmrig/pull/1263) Added new option `dataset_host` for NVIDIA GPUs with less than 4 GB memory (RandomX only).
+- [#1068](https://github.com/xmrig/xmrig/pull/1068) Added support for `self-select` stratum protocol extension.
+- [#1227](https://github.com/xmrig/xmrig/pull/1227) Added new algorithm `rx/arq`, RandomX variant for upcoming ArQmA fork.
+- [#808](https://github.com/xmrig/xmrig/issues/808#issuecomment-539297156) Added experimental support for persistent memory for CPU mining threads.
+- [#1221](https://github.com/xmrig/xmrig/issues/1221) Improved RandomX dataset memory usage and initialization speed for NUMA machines.
+- [#1175](https://github.com/xmrig/xmrig/issues/1175) Fixed support for systems where total count of NUMA nodes not equal usable nodes count.
+- Added config option `cpu/max-threads-hint` and command line option `--cpu-max-threads-hint`.
+- [#1185](https://github.com/xmrig/xmrig/pull/1185) Added JIT compiler for RandomX on ARMv8.
+- Improved API endpoint `GET /2/backends` and added support for this endpoint to [workers.xmrig.info](http://workers.xmrig.info).
+- Added command line option `--no-cpu` to disable CPU backend.
+- Added OpenCL specific command line options: `--opencl`, `--opencl-devices`, `--opencl-platform`, `--opencl-loader` and `--opencl-no-cache`.
+- Added CUDA specific command line options: `--cuda`, `--cuda-loader` and `--no-nvml`.
+- Removed command line option `--http-enabled`, HTTP API enabled automatically if any other `--http-*` option provided.
+- [#1172](https://github.com/xmrig/xmrig/issues/1172) **Added OpenCL mining backend.**
+  - [#268](https://github.com/xmrig/xmrig-amd/pull/268) [#270](https://github.com/xmrig/xmrig-amd/pull/270) [#271](https://github.com/xmrig/xmrig-amd/pull/271) [#273](https://github.com/xmrig/xmrig-amd/pull/273) [#274](https://github.com/xmrig/xmrig-amd/pull/274) [#1171](https://github.com/xmrig/xmrig/pull/1171) Added RandomX support for OpenCL, thanks [@SChernykh](https://github.com/SChernykh).
+- Algorithm `cn/wow` removed, as no longer alive. 
+
+# Previous versions
+[doc/CHANGELOG_OLD.md](doc/CHANGELOG_OLD.md)

CMakeLists.txt

@@ -1,205 +1,195 @@
 cmake_minimum_required(VERSION 2.8)
 project(xmrig)
 
-option(WITH_LIBCPUID "Use Libcpuid" ON)
-option(WITH_AEON     "CryptoNight-Lite support" ON)
-option(WITH_HTTPD    "HTTP REST API" ON)
-option(BUILD_STATIC  "Build static binary" OFF)
+option(WITH_LIBCPUID        "Enable libcpuid support" ON)
+option(WITH_HWLOC           "Enable hwloc support" ON)
+option(WITH_CN_LITE         "Enable CryptoNight-Lite algorithms family" ON)
+option(WITH_CN_HEAVY        "Enable CryptoNight-Heavy algorithms family" ON)
+option(WITH_CN_PICO         "Enable CryptoNight-Pico algorithm" ON)
+option(WITH_RANDOMX         "Enable RandomX algorithms family" ON)
+option(WITH_ARGON2          "Enable Argon2 algorithms family" ON)
+option(WITH_ASTROBWT        "Enable AstroBWT algorithms family" ON)
+option(WITH_KAWPOW          "Enable KawPow algorithms family" ON)
+option(WITH_HTTP            "Enable HTTP protocol support (client/server)" ON)
+option(WITH_DEBUG_LOG       "Enable debug log output" OFF)
+option(WITH_TLS             "Enable OpenSSL support" ON)
+option(WITH_ASM             "Enable ASM PoW implementations" ON)
+option(WITH_MSR             "Enable MSR mod & 1st-gen Ryzen fix" ON)
+option(WITH_ENV_VARS        "Enable environment variables support in config file" ON)
+option(WITH_EMBEDDED_CONFIG "Enable internal embedded JSON config" OFF)
+option(WITH_OPENCL          "Enable OpenCL backend" ON)
+option(WITH_CUDA            "Enable CUDA backend" ON)
+option(WITH_NVML            "Enable NVML (NVIDIA Management Library) support (only if CUDA backend enabled)" ON)
+option(WITH_ADL             "Enable ADL (AMD Display Library) or sysfs support (only if OpenCL backend enabled)" ON)
+option(WITH_STRICT_CACHE    "Enable strict checks for OpenCL cache" ON)
+option(WITH_INTERLEAVE_DEBUG_LOG "Enable debug log for threads interleave" OFF)
+
+option(BUILD_STATIC         "Build static binary" OFF)
+option(ARM_TARGET           "Force use specific ARM target 8 or 7" 0)
+option(HWLOC_DEBUG          "Enable hwloc debug helpers and log" OFF)
+
+
+set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} "${CMAKE_SOURCE_DIR}/cmake")
+
 
 include (CheckIncludeFile)
 include (cmake/cpu.cmake)
+include (cmake/os.cmake)
+include (src/base/base.cmake)
+include (src/backend/backend.cmake)
 
 
 set(HEADERS
-    src/api/Api.h
-    src/api/ApiState.h
-    src/api/NetworkState.h
+    "${HEADERS_BASE}"
+    "${HEADERS_BASE_HTTP}"
+    "${HEADERS_BACKEND}"
     src/App.h
-    src/Console.h
-    src/Cpu.h
-    src/interfaces/IClientListener.h
-    src/interfaces/IConsoleListener.h
-    src/interfaces/IJobResultListener.h
-    src/interfaces/ILogBackend.h
-    src/interfaces/IStrategy.h
-    src/interfaces/IStrategyListener.h
-    src/interfaces/IWorker.h
-    src/log/ConsoleLog.h
-    src/log/FileLog.h
-    src/log/Log.h
-    src/Mem.h
-    src/net/Client.h
-    src/net/Id.h
-    src/net/Job.h
+    src/core/config/Config_default.h
+    src/core/config/Config_platform.h
+    src/core/config/Config.h
+    src/core/config/ConfigTransform.h
+    src/core/config/usage.h
+    src/core/Controller.h
+    src/core/Miner.h
+    src/net/interfaces/IJobResultListener.h
     src/net/JobResult.h
+    src/net/JobResults.h
     src/net/Network.h
     src/net/strategies/DonateStrategy.h
-    src/net/strategies/FailoverStrategy.h
-    src/net/strategies/SinglePoolStrategy.h
-    src/net/SubmitResult.h
-    src/net/Url.h
-    src/Options.h
-    src/Platform.h
     src/Summary.h
     src/version.h
-    src/workers/DoubleWorker.h
-    src/workers/Handle.h
-    src/workers/Hashrate.h
-    src/workers/SingleWorker.h
-    src/workers/Worker.h
-    src/workers/Workers.h
-    src/xmrig.h
    )
 
 set(HEADERS_CRYPTO
-    src/crypto/c_blake256.h
-    src/crypto/c_groestl.h
-    src/crypto/c_jh.h
-    src/crypto/c_keccak.h
-    src/crypto/c_skein.h
-    src/crypto/CryptoNight.h
-    src/crypto/CryptoNight_monero.h
-    src/crypto/CryptoNight_test.h
-    src/crypto/groestl_tables.h
-    src/crypto/hash.h
-    src/crypto/skein_port.h
-    src/crypto/soft_aes.h
+    src/backend/common/interfaces/IMemoryPool.h
+    src/crypto/cn/asm/CryptonightR_template.h
+    src/crypto/cn/c_blake256.h
+    src/crypto/cn/c_groestl.h
+    src/crypto/cn/c_jh.h
+    src/crypto/cn/c_skein.h
+    src/crypto/cn/CnAlgo.h
+    src/crypto/cn/CnCtx.h
+    src/crypto/cn/CnHash.h
+    src/crypto/cn/CryptoNight_monero.h
+    src/crypto/cn/CryptoNight_test.h
+    src/crypto/cn/CryptoNight.h
+    src/crypto/cn/groestl_tables.h
+    src/crypto/cn/hash.h
+    src/crypto/cn/skein_port.h
+    src/crypto/cn/soft_aes.h
+    src/crypto/common/HugePagesInfo.h
+    src/crypto/common/MemoryPool.h
+    src/crypto/common/Nonce.h
+    src/crypto/common/portable/mm_malloc.h
+    src/crypto/common/VirtualMemory.h
    )
 
 if (XMRIG_ARM)
-    set(HEADERS_CRYPTO "${HEADERS_CRYPTO}" src/crypto/CryptoNight_arm.h)
+    set(HEADERS_CRYPTO "${HEADERS_CRYPTO}" src/crypto/cn/CryptoNight_arm.h)
 else()
-    set(HEADERS_CRYPTO "${HEADERS_CRYPTO}" src/crypto/CryptoNight_x86.h)
+    set(HEADERS_CRYPTO "${HEADERS_CRYPTO}" src/crypto/cn/CryptoNight_x86.h)
 endif()
 
 set(SOURCES
-    src/api/Api.cpp
-    src/api/ApiState.cpp
-    src/api/NetworkState.cpp
+    "${SOURCES_BASE}"
+    "${SOURCES_BASE_HTTP}"
+    "${SOURCES_BACKEND}"
     src/App.cpp
-    src/Console.cpp
-    src/log/ConsoleLog.cpp
-    src/log/FileLog.cpp
-    src/log/Log.cpp
-    src/Mem.cpp
-    src/net/Client.cpp
-    src/net/Job.cpp
+    src/core/config/Config.cpp
+    src/core/config/ConfigTransform.cpp
+    src/core/Controller.cpp
+    src/core/Miner.cpp
+    src/net/JobResults.cpp
     src/net/Network.cpp
     src/net/strategies/DonateStrategy.cpp
-    src/net/strategies/FailoverStrategy.cpp
-    src/net/strategies/SinglePoolStrategy.cpp
-    src/net/SubmitResult.cpp
-    src/net/Url.cpp
-    src/Options.cpp
-    src/Platform.cpp
     src/Summary.cpp
-    src/workers/DoubleWorker.cpp
-    src/workers/Handle.cpp
-    src/workers/Hashrate.cpp
-    src/workers/SingleWorker.cpp
-    src/workers/Worker.cpp
-    src/workers/Workers.cpp
     src/xmrig.cpp
    )
 
 set(SOURCES_CRYPTO
-    src/crypto/c_keccak.c
-    src/crypto/c_groestl.c
-    src/crypto/c_blake256.c
-    src/crypto/c_jh.c
-    src/crypto/c_skein.c
-    src/crypto/CryptoNight.cpp
+    src/crypto/cn/c_blake256.c
+    src/crypto/cn/c_groestl.c
+    src/crypto/cn/c_jh.c
+    src/crypto/cn/c_skein.c
+    src/crypto/cn/CnCtx.cpp
+    src/crypto/cn/CnHash.cpp
+    src/crypto/common/HugePagesInfo.cpp
+    src/crypto/common/MemoryPool.cpp
+    src/crypto/common/Nonce.cpp
+    src/crypto/common/VirtualMemory.cpp
    )
 
-if (WIN32)
-    set(SOURCES_OS
+if (WITH_HWLOC)
+    list(APPEND HEADERS_CRYPTO
+        src/crypto/common/NUMAMemoryPool.h
+        )
+
+    list(APPEND SOURCES_CRYPTO
+        src/crypto/common/NUMAMemoryPool.cpp
+        src/crypto/common/VirtualMemory_hwloc.cpp
+        )
+endif()
+
+if (XMRIG_OS_WIN)
+    list(APPEND SOURCES_OS
         res/app.rc
         src/App_win.cpp
-        src/Cpu_win.cpp
-        src/Mem_win.cpp
-        src/Platform_win.cpp
+        src/crypto/common/VirtualMemory_win.cpp
         )
 
-    add_definitions(/DWIN32)
     set(EXTRA_LIBS ws2_32 psapi iphlpapi userenv)
-elseif (APPLE)
-    set(SOURCES_OS
+elseif (XMRIG_OS_APPLE)
+    list(APPEND SOURCES_OS
         src/App_unix.cpp
-        src/Cpu_mac.cpp
-        src/Mem_unix.cpp
-        src/Platform_mac.cpp
+        src/crypto/common/VirtualMemory_unix.cpp
         )
 else()
-    set(SOURCES_OS
+    list(APPEND SOURCES_OS
         src/App_unix.cpp
-        src/Cpu_unix.cpp
-        src/Mem_unix.cpp
-        src/Platform_unix.cpp
+        src/crypto/common/VirtualMemory_unix.cpp
         )
 
-    set(EXTRA_LIBS pthread rt)
-endif()
+    if (XMRIG_OS_ANDROID)
+        set(EXTRA_LIBS pthread rt dl log)
+    elseif (XMRIG_OS_LINUX)
+        list(APPEND SOURCES_OS
+            src/crypto/common/LinuxMemory.h
+            src/crypto/common/LinuxMemory.cpp
+            )
 
-if (CMAKE_SYSTEM_NAME STREQUAL FreeBSD)
-    set(EXTRA_LIBS ${EXTRA_LIBS} kvm)
-endif()
-
-if (CMAKE_SYSTEM_NAME MATCHES "Linux")
-    EXECUTE_PROCESS(COMMAND uname -o COMMAND tr -d '\n' OUTPUT_VARIABLE OPERATING_SYSTEM)
-    if (OPERATING_SYSTEM MATCHES "Android")
-        set(EXTRA_LIBS ${EXTRA_LIBS} log)
+        set(EXTRA_LIBS pthread rt dl)
+    elseif (XMRIG_OS_FREEBSD)
+        set(EXTRA_LIBS kvm pthread)
     endif()
 endif()
 
-add_definitions(/D__STDC_FORMAT_MACROS)
-add_definitions(/DUNICODE)
-#add_definitions(/DAPP_DEBUG)
-
-set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} "${CMAKE_SOURCE_DIR}/cmake")
+add_definitions(-DXMRIG_MINER_PROJECT)
+add_definitions(-D__STDC_FORMAT_MACROS -DUNICODE)
 
 find_package(UV REQUIRED)
 
 include(cmake/flags.cmake)
+include(cmake/randomx.cmake)
+include(cmake/argon2.cmake)
+include(cmake/astrobwt.cmake)
+include(cmake/kawpow.cmake)
+include(cmake/OpenSSL.cmake)
+include(cmake/asm.cmake)
 
-if (WITH_LIBCPUID)
-    add_subdirectory(src/3rdparty/libcpuid)
-
-    include_directories(src/3rdparty/libcpuid)
-    set(CPUID_LIB cpuid)
-    set(SOURCES_CPUID src/Cpu.cpp)
-else()
-    add_definitions(/DXMRIG_NO_LIBCPUID)
-
-    if (XMRIG_ARM)
-        set(SOURCES_CPUID src/Cpu_arm.cpp)
-    else()
-        set(SOURCES_CPUID src/Cpu_stub.cpp)
-    endif()
+if (WITH_CN_LITE)
+    add_definitions(/DXMRIG_ALGO_CN_LITE)
 endif()
 
-CHECK_INCLUDE_FILE (syslog.h HAVE_SYSLOG_H)
-if (HAVE_SYSLOG_H)
-    add_definitions(/DHAVE_SYSLOG_H)
-    set(SOURCES_SYSLOG src/log/SysLog.h src/log/SysLog.cpp)
+if (WITH_CN_HEAVY)
+    add_definitions(/DXMRIG_ALGO_CN_HEAVY)
 endif()
 
-if (NOT WITH_AEON)
-    add_definitions(/DXMRIG_NO_AEON)
+if (WITH_CN_PICO)
+    add_definitions(/DXMRIG_ALGO_CN_PICO)
 endif()
 
-if (WITH_HTTPD)
-    find_package(MHD)
-
-    if (MHD_FOUND)
-        include_directories(${MHD_INCLUDE_DIRS})
-        set(HTTPD_SOURCES src/api/Httpd.h src/api/Httpd.cpp)
-    else()
-        message(FATAL_ERROR "microhttpd NOT found: use `-DWITH_HTTPD=OFF` to build without http deamon support")
-    endif()
-else()
-    set(MHD_LIBRARY "")
-    add_definitions(/DXMRIG_NO_HTTPD)
-    add_definitions(/DXMRIG_NO_API)
+if (WITH_EMBEDDED_CONFIG)
+    add_definitions(/DXMRIG_FEATURE_EMBEDDED_CONFIG)
 endif()
 
 include_directories(src)
@@ -210,5 +200,14 @@ if (BUILD_STATIC)
     set(CMAKE_EXE_LINKER_FLAGS " -static")
 endif()
 
-add_executable(xmrig ${HEADERS} ${SOURCES} ${SOURCES_OS} ${SOURCES_CPUID} ${HEADERS_CRYPTO} ${SOURCES_CRYPTO} ${SOURCES_SYSLOG} ${HTTPD_SOURCES})
-target_link_libraries(xmrig ${UV_LIBRARIES} ${MHD_LIBRARY} ${EXTRA_LIBS} ${CPUID_LIB})
+if (WITH_DEBUG_LOG)
+    add_definitions(/DAPP_DEBUG)
+endif()
+
+add_executable(${CMAKE_PROJECT_NAME} ${HEADERS} ${SOURCES} ${SOURCES_OS} ${SOURCES_CPUID} ${HEADERS_CRYPTO} ${SOURCES_CRYPTO} ${SOURCES_SYSLOG} ${TLS_SOURCES} ${XMRIG_ASM_SOURCES})
+target_link_libraries(${CMAKE_PROJECT_NAME} ${XMRIG_ASM_LIBRARY} ${OPENSSL_LIBRARIES} ${UV_LIBRARIES} ${EXTRA_LIBS} ${CPUID_LIB} ${ARGON2_LIBRARY} ${ETHASH_LIBRARY})
+
+if (WIN32)
+    add_custom_command(TARGET ${CMAKE_PROJECT_NAME} POST_BUILD
+        COMMAND ${CMAKE_COMMAND} -E copy_if_different "${CMAKE_SOURCE_DIR}/bin/WinRing0/WinRing0x64.sys" $<TARGET_FILE_DIR:${CMAKE_PROJECT_NAME}>)
+endif()

README.md

@@ -1,4 +1,5 @@
 # XMRig
+
 [![Github All Releases](https://img.shields.io/github/downloads/xmrig/xmrig/total.svg)](https://github.com/xmrig/xmrig/releases)
 [![GitHub release](https://img.shields.io/github/release/xmrig/xmrig/all.svg)](https://github.com/xmrig/xmrig/releases)
 [![GitHub Release Date](https://img.shields.io/github/release-date-pre/xmrig/xmrig.svg)](https://github.com/xmrig/xmrig/releases)
@@ -6,38 +7,14 @@
 [![GitHub stars](https://img.shields.io/github/stars/xmrig/xmrig.svg)](https://github.com/xmrig/xmrig/stargazers)
 [![GitHub forks](https://img.shields.io/github/forks/xmrig/xmrig.svg)](https://github.com/xmrig/xmrig/network)
 
-XMRig is a high performance Monero (XMR) CPU miner, with official support for Windows.
-Originally based on cpuminer-multi with heavy optimizations/rewrites and removing a lot of legacy code, since version 1.0.0 completely rewritten from scratch on C++.
+XMRig High performance, open source, cross platform RandomX, KawPow, CryptoNight, AstroBWT and Argon2 CPU/GPU miner, with official support for Windows.
 
-* This is the **CPU-mining** version, there is also a [NVIDIA GPU version](https://github.com/xmrig/xmrig-nvidia) and [AMD GPU version]( https://github.com/xmrig/xmrig-amd).
-* [Roadmap](https://github.com/xmrig/xmrig/issues/106) for next releases.
+## Mining backends
+- **CPU** (x64/x86/ARM)
+- **OpenCL** for AMD GPUs.
+- **CUDA** for NVIDIA GPUs via external [CUDA plugin](https://github.com/xmrig/xmrig-cuda).
 
-<img src="http://i.imgur.com/OKZRVDh.png" width="619" >
-
-#### Table of contents
-* [Features](#features)
-* [Download](#download)
-* [Usage](#usage)
-* [Algorithm variations](#algorithm-variations)
-* [Build](https://github.com/xmrig/xmrig/wiki/Build)
-* [Common Issues](#common-issues)
-* [Other information](#other-information)
-* [Donations](#donations)
-* [Release checksums](#release-checksums)
-* [Contacts](#contacts)
-
-## Features
-* High performance.
-* Official Windows support.
-* Small Windows executable, without dependencies.
-* x86/x64 support.
-* Support for backup (failover) mining server.
-* keepalived support.
-* Command line options compatible with cpuminer.
-* CryptoNight-Lite support for AEON.
-* Smart automatic [CPU configuration](https://github.com/xmrig/xmrig/wiki/Threads).
-* Nicehash support
-* It's open source software.
+<img src="doc/screenshot_v5_2_0.png" width="833" >
 
 ## Download
 * Binary releases: https://github.com/xmrig/xmrig/releases
@@ -45,86 +22,112 @@ Originally based on cpuminer-multi with heavy optimizations/rewrites and removin
   * Clone with `git clone https://github.com/xmrig/xmrig.git` :hammer: [Build instructions](https://github.com/xmrig/xmrig/wiki/Build).
 
 ## Usage
-Use [config.xmrig.com](https://config.xmrig.com/xmrig) to generate, edit or share configurations.
+The preferred way to configure the miner is the [JSON config file](src/config.json) as it is more flexible and human friendly. The command line interface does not cover all features, such as mining profiles for different algorithms. Important options can be changed during runtime without miner restart by editing the config file or executing API calls.
 
-### Options
+* **[xmrig.com/wizard](https://xmrig.com/wizard)** helps you create initial configuration for the miner.
+* **[workers.xmrig.info](http://workers.xmrig.info)** helps manage your miners via HTTP API.
+
+### Command line options
 ```
-  -a, --algo=ALGO          cryptonight (default) or cryptonight-lite
-  -o, --url=URL            URL of mining server
-  -O, --userpass=U:P       username:password pair for mining server
-  -u, --user=USERNAME      username for mining server
-  -p, --pass=PASSWORD      password for mining server
-  -t, --threads=N          number of miner threads
-  -v, --av=N               algorithm variation, 0 auto select
-  -k, --keepalive          send keepalived for prevent timeout (need pool support)
-  -r, --retries=N          number of times to retry before switch to backup server (default: 5)
-  -R, --retry-pause=N      time to pause between retries (default: 5)
-      --cpu-affinity       set process affinity to CPU core(s), mask 0x3 for cores 0 and 1
-      --cpu-priority       set process priority (0 idle, 2 normal to 5 highest)
-      --no-huge-pages      disable huge pages support
-      --no-color           disable colored output
-      --donate-level=N     donate level, default 5% (5 minutes in 100 minutes)
-      --user-agent         set custom user-agent string for pool
-  -B, --background         run the miner in the background
-  -c, --config=FILE        load a JSON-format configuration file
-  -l, --log-file=FILE      log all output to a file
-      --max-cpu-usage=N    maximum CPU usage for automatic threads mode (default 75)
-      --safe               safe adjust threads and av settings for current CPU
-      --nicehash           enable nicehash/xmrig-proxy support
-      --print-time=N       print hashrate report every N seconds
-      --api-port=N         port for the miner API
-      --api-access-token=T access token for API
-      --api-worker-id=ID   custom worker-id for API
-  -h, --help               display this help and exit
-  -V, --version            output version information and exit
+Network:
+  -o, --url=URL                 URL of mining server
+  -a, --algo=ALGO               mining algorithm https://xmrig.com/docs/algorithms
+      --coin=COIN               specify coin instead of algorithm
+  -u, --user=USERNAME           username for mining server
+  -p, --pass=PASSWORD           password for mining server
+  -O, --userpass=U:P            username:password pair for mining server
+  -x, --proxy=HOST:PORT         connect through a SOCKS5 proxy
+  -k, --keepalive               send keepalive packet for prevent timeout (needs pool support)
+      --nicehash                enable nicehash.com support
+      --rig-id=ID               rig identifier for pool-side statistics (needs pool support)
+      --tls                     enable SSL/TLS support (needs pool support)
+      --tls-fingerprint=HEX     pool TLS certificate fingerprint for strict certificate pinning
+      --daemon                  use daemon RPC instead of pool for solo mining
+      --daemon-poll-interval=N  daemon poll interval in milliseconds (default: 1000)
+  -r, --retries=N               number of times to retry before switch to backup server (default: 5)
+  -R, --retry-pause=N           time to pause between retries (default: 5)
+      --user-agent              set custom user-agent string for pool
+      --donate-level=N          donate level, default 5%% (5 minutes in 100 minutes)
+      --donate-over-proxy=N     control donate over xmrig-proxy feature
+
+CPU backend:
+      --no-cpu                  disable CPU mining backend
+  -t, --threads=N               number of CPU threads
+  -v, --av=N                    algorithm variation, 0 auto select
+      --cpu-affinity            set process affinity to CPU core(s), mask 0x3 for cores 0 and 1
+      --cpu-priority            set process priority (0 idle, 2 normal to 5 highest)
+      --cpu-max-threads-hint=N  maximum CPU threads count (in percentage) hint for autoconfig
+      --cpu-memory-pool=N       number of 2 MB pages for persistent memory pool, -1 (auto), 0 (disable)
+      --cpu-no-yield            prefer maximum hashrate rather than system response/stability
+      --no-huge-pages           disable huge pages support
+      --asm=ASM                 ASM optimizations, possible values: auto, none, intel, ryzen, bulldozer
+      --randomx-init=N          thread count to initialize RandomX dataset
+      --randomx-no-numa         disable NUMA support for RandomX
+      --randomx-mode=MODE       RandomX mode: auto, fast, light
+      --randomx-1gb-pages       use 1GB hugepages for dataset (Linux only)
+      --randomx-wrmsr=N         write custom value (0-15) to Intel MSR register 0x1a4 or disable MSR mod (-1)
+      --randomx-no-rdmsr        disable reverting initial MSR values on exit
+      --astrobwt-max-size=N     skip hashes with large stage 2 size, default: 550, min: 400, max: 1200
+      --astrobwt-avx2           enable AVX2 optimizations for AstroBWT algorithm
+
+API:
+      --api-worker-id=ID        custom worker-id for API
+      --api-id=ID               custom instance ID for API
+      --http-host=HOST          bind host for HTTP API (default: 127.0.0.1)
+      --http-port=N             bind port for HTTP API
+      --http-access-token=T     access token for HTTP API
+      --http-no-restricted      enable full remote access to HTTP API (only if access token set)
+
+OpenCL backend:
+      --opencl                  enable OpenCL mining backend
+      --opencl-devices=N        comma separated list of OpenCL devices to use
+      --opencl-platform=N       OpenCL platform index or name
+      --opencl-loader=PATH      path to OpenCL-ICD-Loader (OpenCL.dll or libOpenCL.so)
+      --opencl-no-cache         disable OpenCL cache
+      --print-platforms         print available OpenCL platforms and exit
+
+CUDA backend:
+      --cuda                    enable CUDA mining backend
+      --cuda-loader=PATH        path to CUDA plugin (xmrig-cuda.dll or libxmrig-cuda.so)
+      --cuda-devices=N          comma separated list of CUDA devices to use
+      --cuda-bfactor-hint=N     bfactor hint for autoconfig (0-12)
+      --cuda-bsleep-hint=N      bsleep hint for autoconfig
+      --no-nvml                 disable NVML (NVIDIA Management Library) support
+
+TLS:
+      --tls-gen=HOSTNAME        generate TLS certificate for specific hostname
+      --tls-cert=FILE           load TLS certificate chain from a file in the PEM format
+      --tls-cert-key=FILE       load TLS certificate private key from a file in the PEM format
+      --tls-dhparam=FILE        load DH parameters for DHE ciphers from a file in the PEM format
+      --tls-protocols=N         enable specified TLS protocols, example: "TLSv1 TLSv1.1 TLSv1.2 TLSv1.3"
+      --tls-ciphers=S           set list of available ciphers (TLSv1.2 and below)
+      --tls-ciphersuites=S      set list of available TLSv1.3 ciphersuites
+
+Logging:
+  -S, --syslog                  use system log for output messages
+  -l, --log-file=FILE           log all output to a file
+      --print-time=N            print hashrate report every N seconds
+      --health-print-time=N     print health report every N seconds
+      --no-color                disable colored output
+      --verbose                 verbose output
+
+Misc:
+  -c, --config=FILE             load a JSON-format configuration file
+  -B, --background              run the miner in the background
+  -V, --version                 output version information and exit
+  -h, --help                    display this help and exit
+      --dry-run                 test configuration and exit
+      --export-topology         export hwloc topology to a XML file and exit
+      --title                   set custom console window title
+      --no-title                disable setting console window title      
 ```
 
-Also you can use configuration via config file, default **config.json**. You can load multiple config files and combine it with command line options.
-
-## Algorithm variations
-Since version 0.8.0.
-* `--av=1` For CPUs with hardware AES.
-* `--av=2` Lower power mode (double hash) of `1`.
-* `--av=3` Software AES implementation.
-* `--av=4` Lower power mode (double hash) of `3`.
-
-## Common Issues
-### HUGE PAGES unavailable
-* Run XMRig as Administrator.
-* Since version 0.8.0 XMRig automatically enables SeLockMemoryPrivilege for current user, but reboot or sign out still required. [Manual instruction](https://msdn.microsoft.com/en-gb/library/ms190730.aspx).
-
-## Other information
-* No HTTP support, only stratum protocol support.
-* No TLS support.
-* Default donation 5% (5 minutes in 100 minutes) can be reduced to 1% via command line option `--donate-level`.
-
-
-### CPU mining performance
-* **Intel i7-7700** - 307 H/s (4 threads)
-* **AMD Ryzen 7 1700X** - 560 H/s (8 threads)
-
-Please note performance is highly dependent on system load. The numbers above are obtained on an idle system. Tasks heavily using a processor cache, such as video playback, can greatly degrade hashrate. Optimal number of threads depends on the size of the L3 cache of a processor, 1 thread requires 2 MB of cache.
-
-### Maximum performance checklist
-* Idle operating system.
-* Do not exceed optimal thread count.
-* Use modern CPUs with AES-NI instruction set.
-* Try setup optimal cpu affinity.
-* Enable fast memory (Large/Huge pages).
-
 ## Donations
+* Default donation 5% (5 minutes in 100 minutes) can be reduced to 1% via option `donate-level` or disabled in source code.
 * XMR: `48edfHu7V9Z84YzzMa6fUueoELZ9ZRXq9VetWzYGzKt52XU5xvqgzYnDK9URnRoJMk1j8nLwEVsaSWJ4fhdUyZijBGUicoD`
 * BTC: `1P7ujsXeX7GxQwHNnJsRMgAdNkFZmNVqJT`
 
-## Release checksums
-### SHA-256
-```
-232ea929f7219c8de81c7e6fcae7437d40d8128cf55b597a6e1fca0cd77f9f5b xmrig-2.5.0-xenial-amd64.tar.gz/xmrig-2.5.0/xmrig
-6149ffed21e740cac12aa61b2fdd17248cbd3e51bab2289d2766aad1d29df910 xmrig-2.5.0-gcc-win32.zip/xmrig.exe
-9c89f80e21db906439a7a1b333b8215dbe07d8e42f98a63f6c10c954288a7108 xmrig-2.5.0-gcc-win64.zip/xmrig.exe
-b50773c5a74ca9921597a1152e2469ec266cc89eb9765038db7e876f0bcece73 xmrig-2.5.0-msvc-win64.zip/xmrig.exe
-```
-
 ## Contacts
 * support@xmrig.com
 * [reddit](https://www.reddit.com/user/XMRig/)
+* [twitter](https://twitter.com/xmrig_dev)

bin/WinRing0/LICENSE

@@ -0,0 +1,21 @@
+Copyright (c) 2007-2009 OpenLibSys.org. All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
+1. Redistributions of source code must retain the above copyright
+   notice, this list of conditions and the following disclaimer.
+2. Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions and the following disclaimer in the
+   documentation and/or other materials provided with the distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

cmake/FindHWLOC.cmake

@@ -0,0 +1,25 @@
+find_path(
+    HWLOC_INCLUDE_DIR
+    NAMES hwloc.h
+    PATHS "${XMRIG_DEPS}" ENV "XMRIG_DEPS"
+    PATH_SUFFIXES "include"
+    NO_DEFAULT_PATH
+)
+
+find_path(HWLOC_INCLUDE_DIR NAMES hwloc.h)
+
+find_library(
+    HWLOC_LIBRARY
+    NAMES hwloc.a hwloc libhwloc
+    PATHS "${XMRIG_DEPS}" ENV "XMRIG_DEPS"
+    PATH_SUFFIXES "lib"
+    NO_DEFAULT_PATH
+)
+
+find_library(HWLOC_LIBRARY NAMES hwloc.a hwloc libhwloc)
+
+set(HWLOC_LIBRARIES ${HWLOC_LIBRARY})
+set(HWLOC_INCLUDE_DIRS ${HWLOC_INCLUDE_DIR})
+
+include(FindPackageHandleStandardArgs)
+find_package_handle_standard_args(HWLOC DEFAULT_MSG HWLOC_LIBRARY HWLOC_INCLUDE_DIR)

cmake/FindMHD.cmake

@@ -1,49 +0,0 @@
-# - Try to find MHD
-# Once done this will define
-#
-#  MHD_FOUND - system has MHD
-#  MHD_INCLUDE_DIRS - the MHD include directory
-#  MHD_LIBRARY - Link these to use MHD
-
-find_path(
-    MHD_INCLUDE_DIR
-    NAMES microhttpd.h
-    PATHS "${XMRIG_DEPS}" ENV "XMRIG_DEPS"
-    PATH_SUFFIXES "include"
-    DOC "microhttpd include dir"
-    NO_DEFAULT_PATH
-)
-
-find_path(MHD_INCLUDE_DIR NAMES microhttpd.h)
-
-find_library(
-    MHD_LIBRARY
-    NAMES libmicrohttpd.a microhttpd libmicrohttpd
-    PATHS "${XMRIG_DEPS}" ENV "XMRIG_DEPS"
-    PATH_SUFFIXES "lib"
-    DOC "microhttpd library"
-    NO_DEFAULT_PATH
-)
-
-find_library(MHD_LIBRARY NAMES microhttpd libmicrohttpd)
-
-set(MHD_INCLUDE_DIRS ${MHD_INCLUDE_DIR})
-set(MHD_LIBRARIES ${MHD_LIBRARY})
-
-# debug library on windows
-# same naming convention as in qt (appending debug library with d)
-# boost is using the same "hack" as us with "optimized" and "debug"
-# official MHD project actually uses _d suffix
-if (${CMAKE_CXX_COMPILER_ID} STREQUAL MSVC)
-    find_library(
-        MHD_LIBRARY_DEBUG
-        NAMES microhttpd_d microhttpd-10_d libmicrohttpd_d libmicrohttpd-dll_d
-        DOC "mhd debug library"
-    )
-    set(MHD_LIBRARIES optimized ${MHD_LIBRARIES} debug ${MHD_LIBRARY_DEBUG})
-endif()
-
-include(FindPackageHandleStandardArgs)
-find_package_handle_standard_args(MHD DEFAULT_MSG MHD_LIBRARY MHD_INCLUDE_DIR)
-mark_as_advanced(MHD_INCLUDE_DIR MHD_LIBRARY)
-

cmake/OpenSSL.cmake

@@ -0,0 +1,59 @@
+if (WITH_TLS)
+    set(OPENSSL_ROOT_DIR ${XMRIG_DEPS})
+
+    if (WIN32)
+        set(OPENSSL_USE_STATIC_LIBS TRUE)
+        set(OPENSSL_MSVC_STATIC_RT TRUE)
+
+        set(EXTRA_LIBS ${EXTRA_LIBS} crypt32)
+    elseif (APPLE)
+        set(OPENSSL_USE_STATIC_LIBS TRUE)
+    endif()
+
+    find_package(OpenSSL)
+
+    if (OPENSSL_FOUND)
+        set(TLS_SOURCES
+            src/base/net/stratum/Tls.cpp
+            src/base/net/stratum/Tls.h
+            src/base/net/tls/ServerTls.cpp
+            src/base/net/tls/ServerTls.h
+            src/base/net/tls/TlsConfig.cpp
+            src/base/net/tls/TlsConfig.h
+            src/base/net/tls/TlsContext.cpp
+            src/base/net/tls/TlsContext.h
+            src/base/net/tls/TlsGen.cpp
+            src/base/net/tls/TlsGen.h
+            )
+
+        include_directories(${OPENSSL_INCLUDE_DIR})
+
+        if (WITH_HTTP)
+            set(TLS_SOURCES ${TLS_SOURCES}
+                src/base/net/https/HttpsClient.cpp
+                src/base/net/https/HttpsClient.h
+                src/base/net/https/HttpsContext.cpp
+                src/base/net/https/HttpsContext.h
+                src/base/net/https/HttpsServer.cpp
+                src/base/net/https/HttpsServer.h
+                )
+        endif()
+    else()
+        message(FATAL_ERROR "OpenSSL NOT found: use `-DWITH_TLS=OFF` to build without TLS support")
+    endif()
+
+    add_definitions(/DXMRIG_FEATURE_TLS)
+else()
+    set(TLS_SOURCES "")
+    set(OPENSSL_LIBRARIES "")
+    remove_definitions(/DXMRIG_FEATURE_TLS)
+
+    if (WITH_HTTP)
+        set(TLS_SOURCES ${TLS_SOURCES}
+            src/base/net/http/HttpServer.cpp
+            src/base/net/http/HttpServer.h
+            )
+    endif()
+
+    set(CMAKE_PROJECT_NAME "${CMAKE_PROJECT_NAME}-notls")
+endif()

cmake/argon2.cmake

@@ -0,0 +1,18 @@
+if (WITH_ARGON2)
+    add_definitions(/DXMRIG_ALGO_ARGON2)
+
+    list(APPEND HEADERS_CRYPTO
+        src/crypto/argon2/Hash.h
+        src/crypto/argon2/Impl.h
+    )
+
+    list(APPEND SOURCES_CRYPTO
+        src/crypto/argon2/Impl.cpp
+    )
+
+    add_subdirectory(src/3rdparty/argon2)
+    set(ARGON2_LIBRARY argon2)
+else()
+    remove_definitions(/DXMRIG_ALGO_ARGON2)
+    set(ARGON2_LIBRARY "")
+endif()

cmake/asm.cmake

@@ -0,0 +1,52 @@
+if (WITH_ASM AND NOT XMRIG_ARM AND CMAKE_SIZEOF_VOID_P EQUAL 8)
+    set(XMRIG_ASM_LIBRARY "xmrig-asm")
+
+    if (CMAKE_C_COMPILER_ID MATCHES MSVC)
+        enable_language(ASM_MASM)
+
+        if (MSVC_TOOLSET_VERSION GREATER_EQUAL 141)
+            set(XMRIG_ASM_FILES
+                "src/crypto/cn/asm/cn_main_loop.asm"
+                "src/crypto/cn/asm/CryptonightR_template.asm"
+            )
+        else()
+            set(XMRIG_ASM_FILES
+                "src/crypto/cn/asm/win64/cn_main_loop.asm"
+                "src/crypto/cn/asm/win64/CryptonightR_template.asm"
+            )
+        endif()
+
+        set_property(SOURCE ${XMRIG_ASM_FILES} PROPERTY ASM_MASM)
+    else()
+        enable_language(ASM)
+
+        if (WIN32 AND CMAKE_C_COMPILER_ID MATCHES GNU)
+            set(XMRIG_ASM_FILES
+                "src/crypto/cn/asm/win64/cn_main_loop.S"
+                "src/crypto/cn/asm/CryptonightR_template.S"
+            )
+        else()
+            set(XMRIG_ASM_FILES
+                "src/crypto/cn/asm/cn_main_loop.S"
+                "src/crypto/cn/asm/CryptonightR_template.S"
+            )
+        endif()
+
+        set_property(SOURCE ${XMRIG_ASM_FILES} PROPERTY C)
+    endif()
+
+    add_library(${XMRIG_ASM_LIBRARY} STATIC ${XMRIG_ASM_FILES})
+    set(XMRIG_ASM_SOURCES
+        src/crypto/common/Assembly.h
+        src/crypto/common/Assembly.cpp
+        src/crypto/cn/r/CryptonightR_gen.cpp
+        )
+    set_property(TARGET ${XMRIG_ASM_LIBRARY} PROPERTY LINKER_LANGUAGE C)
+
+    add_definitions(/DXMRIG_FEATURE_ASM)
+else()
+    set(XMRIG_ASM_SOURCES "")
+    set(XMRIG_ASM_LIBRARY "")
+
+    remove_definitions(/DXMRIG_FEATURE_ASM)
+endif()

cmake/astrobwt.cmake

@@ -0,0 +1,45 @@
+if (WITH_ASTROBWT)
+    add_definitions(/DXMRIG_ALGO_ASTROBWT)
+
+    list(APPEND HEADERS_CRYPTO
+        src/crypto/astrobwt/AstroBWT.h
+    )
+
+    list(APPEND SOURCES_CRYPTO
+        src/crypto/astrobwt/AstroBWT.cpp
+    )
+
+    if (XMRIG_ARM)
+        list(APPEND HEADERS_CRYPTO
+            src/crypto/astrobwt/salsa20_ref/ecrypt-config.h
+            src/crypto/astrobwt/salsa20_ref/ecrypt-machine.h
+            src/crypto/astrobwt/salsa20_ref/ecrypt-portable.h
+            src/crypto/astrobwt/salsa20_ref/ecrypt-sync.h
+        )
+
+        list(APPEND SOURCES_CRYPTO
+            src/crypto/astrobwt/salsa20_ref/salsa20.c
+        )
+    else()
+        if (CMAKE_SIZEOF_VOID_P EQUAL 8)
+            add_definitions(/DASTROBWT_AVX2)
+            if (CMAKE_C_COMPILER_ID MATCHES MSVC)
+                enable_language(ASM_MASM)
+                list(APPEND SOURCES_CRYPTO src/crypto/astrobwt/sha3_256_avx2.asm)
+            else()
+                enable_language(ASM)
+                list(APPEND SOURCES_CRYPTO src/crypto/astrobwt/sha3_256_avx2.S)
+            endif()
+        endif()
+
+        list(APPEND HEADERS_CRYPTO
+            src/crypto/astrobwt/Salsa20.hpp
+        )
+
+        list(APPEND SOURCES_CRYPTO
+            src/crypto/astrobwt/Salsa20.cpp
+        )
+    endif()
+else()
+    remove_definitions(/DXMRIG_ALGO_ASTROBWT)
+endif()

cmake/cpu.cmake

@@ -7,19 +7,37 @@ if (CMAKE_SYSTEM_PROCESSOR MATCHES "^(x86_64|AMD64)$")
     add_definitions(/DRAPIDJSON_SSE2)
 endif()
 
-
-if (CMAKE_SYSTEM_PROCESSOR MATCHES "^(aarch64)$")
-    set(XMRIG_ARM     ON)
-    set(XMRIG_ARMv8   ON)
-    set(WITH_LIBCPUID OFF)
-
-    add_definitions(/DXMRIG_ARM)
-    add_definitions(/DXMRIG_ARMv8)
-elseif (CMAKE_SYSTEM_PROCESSOR MATCHES "^(armv7|armv7f|armv7s|armv7k|armv7-a|armv7l)$")
-    set(XMRIG_ARM     ON)
-    set(XMRIG_ARMv7   ON)
-    set(WITH_LIBCPUID OFF)
-
-    add_definitions(/DXMRIG_ARM)
-    add_definitions(/DXMRIG_ARMv7)
+if (NOT ARM_TARGET)
+    if (CMAKE_SYSTEM_PROCESSOR MATCHES "^(aarch64|arm64|armv8-a)$")
+        set(ARM_TARGET 8)
+    elseif (CMAKE_SYSTEM_PROCESSOR MATCHES "^(armv7|armv7f|armv7s|armv7k|armv7-a|armv7l)$")
+        set(ARM_TARGET 7)
+    endif()
+endif()
+
+if (ARM_TARGET AND ARM_TARGET GREATER 6)
+    set(XMRIG_ARM     ON)
+    set(WITH_LIBCPUID OFF)
+    add_definitions(/DXMRIG_ARM)
+
+    message(STATUS "Use ARM_TARGET=${ARM_TARGET} (${CMAKE_SYSTEM_PROCESSOR})")
+
+    include(CheckCXXCompilerFlag)
+
+    if (ARM_TARGET EQUAL 8)
+        set(XMRIG_ARMv8 ON)
+        add_definitions(/DXMRIG_ARMv8)
+
+        CHECK_CXX_COMPILER_FLAG(-march=armv8-a+crypto XMRIG_ARM_CRYPTO)
+
+        if (XMRIG_ARM_CRYPTO)
+            add_definitions(/DXMRIG_ARM_CRYPTO)
+            set(ARM8_CXX_FLAGS "-march=armv8-a+crypto")
+        else()
+            set(ARM8_CXX_FLAGS "-march=armv8-a")
+        endif()
+    elseif (ARM_TARGET EQUAL 7)
+        set(XMRIG_ARMv7 ON)
+        add_definitions(/DXMRIG_ARMv7)
+    endif()
 endif()

cmake/flags.cmake

@@ -2,31 +2,45 @@ set(CMAKE_CXX_STANDARD_REQUIRED ON)
 set(CMAKE_CXX_EXTENSIONS OFF)
 set(CMAKE_CXX_STANDARD 11)
 
+set(CMAKE_C_STANDARD 99)
+set(CMAKE_C_STANDARD_REQUIRED ON)
+
 if ("${CMAKE_BUILD_TYPE}" STREQUAL "")
     set(CMAKE_BUILD_TYPE Release)
 endif()
 
+if (CMAKE_BUILD_TYPE STREQUAL "Release")
+    add_definitions(/DNDEBUG)
+endif()
+
+include(CheckSymbolExists)
+
 if (CMAKE_CXX_COMPILER_ID MATCHES GNU)
-
     set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wall -Wno-strict-aliasing")
-    set(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -Ofast -funroll-loops -fvariable-expansion-in-unroller -ftree-loop-if-convert-stores -fmerge-all-constants -fbranch-target-load-optimize2")
+    set(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -Ofast")
 
-    set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wall -fno-exceptions -fno-rtti")
-    set(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} -Ofast -s -funroll-loops -fvariable-expansion-in-unroller -ftree-loop-if-convert-stores -fmerge-all-constants -fbranch-target-load-optimize2")
+    set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wall -fexceptions -fno-rtti -Wno-strict-aliasing -Wno-class-memaccess")
+    set(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} -Ofast -s")
 
     if (XMRIG_ARMv8)
-        set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -march=armv8-a+crypto")
-        set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -march=armv8-a+crypto -flax-vector-conversions")
+        set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${ARM8_CXX_FLAGS}")
+        set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${ARM8_CXX_FLAGS} -flax-vector-conversions")
     elseif (XMRIG_ARMv7)
         set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -mfpu=neon")
         set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -mfpu=neon -flax-vector-conversions")
     else()
         set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -maes")
         set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -maes")
+
+        add_definitions(/DHAVE_ROTR)
     endif()
 
     if (WIN32)
-        set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -static")
+        if (CMAKE_SIZEOF_VOID_P EQUAL 8)
+            set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -static")
+        else()
+            set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -static -Wl,--large-address-aware")
+        endif()
     else()
         set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -static-libgcc -static-libstdc++")
     endif()
@@ -34,36 +48,52 @@ if (CMAKE_CXX_COMPILER_ID MATCHES GNU)
     add_definitions(/D_GNU_SOURCE)
 
     if (${CMAKE_VERSION} VERSION_LESS "3.1.0")
+        set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -std=c99")
         set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -std=c++11")
     endif()
 
     #set(CMAKE_C_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} -gdwarf-2")
 
-elseif (CMAKE_CXX_COMPILER_ID MATCHES MSVC)
+    add_definitions(/DHAVE_BUILTIN_CLEAR_CACHE)
+
+elseif (CMAKE_CXX_COMPILER_ID MATCHES MSVC)
+    set(CMAKE_C_FLAGS_RELEASE "/MT /O2 /Oi /DNDEBUG /GL")
+    set(CMAKE_CXX_FLAGS_RELEASE "/MT /O2 /Oi /DNDEBUG /GL")
 
-    set(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} /Ox /Ot /Oi /MT /GL")
-    set(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} /Ox /Ot /Oi /MT /GL")
     add_definitions(/D_CRT_SECURE_NO_WARNINGS)
     add_definitions(/D_CRT_NONSTDC_NO_WARNINGS)
     add_definitions(/DNOMINMAX)
+    add_definitions(/DHAVE_ROTR)
 
 elseif (CMAKE_CXX_COMPILER_ID MATCHES Clang)
 
     set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wall")
     set(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -Ofast -funroll-loops -fmerge-all-constants")
 
-    set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wall -fno-exceptions -fno-rtti -Wno-missing-braces")
+    set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wall -fexceptions -fno-rtti -Wno-missing-braces")
     set(CMAKE_CXX_FLAGS_RELEASE "${CMAKE_CXX_FLAGS_RELEASE} -Ofast -funroll-loops -fmerge-all-constants")
 
     if (XMRIG_ARMv8)
-        set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -march=armv8-a+crypto")
-        set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -march=armv8-a+crypto")
+        set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${ARM8_CXX_FLAGS}")
+        set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${ARM8_CXX_FLAGS}")
     elseif (XMRIG_ARMv7)
         set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -mfpu=neon -march=${CMAKE_SYSTEM_PROCESSOR}")
         set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -mfpu=neon -march=${CMAKE_SYSTEM_PROCESSOR}")
     else()
         set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -maes")
         set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -maes")
+
+        check_symbol_exists("_rotr" "x86intrin.h" HAVE_ROTR)
+        if (HAVE_ROTR)
+            add_definitions(/DHAVE_ROTR)
+        endif()
     endif()
 
 endif()
+
+if (NOT WIN32)
+    check_symbol_exists("__builtin___clear_cache" "stdlib.h" HAVE_BUILTIN_CLEAR_CACHE)
+    if (HAVE_BUILTIN_CLEAR_CACHE)
+        add_definitions(/DHAVE_BUILTIN_CLEAR_CACHE)
+    endif()
+endif()

cmake/kawpow.cmake

@@ -0,0 +1,19 @@
+if (WITH_KAWPOW)
+    add_definitions(/DXMRIG_ALGO_KAWPOW)
+
+    list(APPEND HEADERS_CRYPTO
+        src/crypto/kawpow/KPCache.h
+        src/crypto/kawpow/KPHash.h
+    )
+
+    list(APPEND SOURCES_CRYPTO
+        src/crypto/kawpow/KPCache.cpp
+        src/crypto/kawpow/KPHash.cpp
+    )
+
+    add_subdirectory(src/3rdparty/libethash)
+    set(ETHASH_LIBRARY ethash)
+else()
+    remove_definitions(/DXMRIG_ALGO_KAWPOW)
+    set(ETHASH_LIBRARY "")
+endif()

cmake/os.cmake

@@ -0,0 +1,45 @@
+if (WIN32)
+    set(XMRIG_OS_WIN ON)
+elseif (APPLE)
+    set(XMRIG_OS_APPLE ON)
+
+    if (IOS OR CMAKE_SYSTEM_NAME STREQUAL iOS)
+        set(XMRIG_OS_IOS ON)
+    else()
+        set(XMRIG_OS_MACOS ON)
+    endif()
+else()
+    set(XMRIG_OS_UNIX ON)
+
+    if (ANDROID OR CMAKE_SYSTEM_NAME MATCHES "Android")
+        set(XMRIG_OS_ANDROID ON)
+    elseif(CMAKE_SYSTEM_NAME MATCHES "Linux")
+        set(XMRIG_OS_LINUX ON)
+    elseif(CMAKE_SYSTEM_NAME STREQUAL FreeBSD)
+        set(XMRIG_OS_FREEBSD ON)
+    endif()
+endif()
+
+
+if (XMRIG_OS_WIN)
+    add_definitions(/DWIN32)
+    add_definitions(/DXMRIG_OS_WIN)
+elseif(XMRIG_OS_APPLE)
+    add_definitions(/DXMRIG_OS_APPLE)
+
+    if (XMRIG_OS_IOS)
+        add_definitions(/DXMRIG_OS_IOS)
+    else()
+        add_definitions(/DXMRIG_OS_MACOS)
+    endif()
+elseif(XMRIG_OS_UNIX)
+    add_definitions(/DXMRIG_OS_UNIX)
+
+    if (XMRIG_OS_ANDROID)
+        add_definitions(/DXMRIG_OS_ANDROID)
+    elseif (XMRIG_OS_LINUX)
+        add_definitions(/DXMRIG_OS_LINUX)
+    elseif (XMRIG_OS_FREEBSD)
+        add_definitions(/DXMRIG_OS_FREEBSD)
+    endif()
+endif()

cmake/randomx.cmake

@@ -0,0 +1,101 @@
+if (WITH_RANDOMX)
+    add_definitions(/DXMRIG_ALGO_RANDOMX)
+    set(WITH_ARGON2 ON)
+
+    list(APPEND HEADERS_CRYPTO
+        src/crypto/rx/Rx.h
+        src/crypto/rx/RxAlgo.h
+        src/crypto/rx/RxBasicStorage.h
+        src/crypto/rx/RxCache.h
+        src/crypto/rx/RxConfig.h
+        src/crypto/rx/RxDataset.h
+        src/crypto/rx/RxQueue.h
+        src/crypto/rx/RxSeed.h
+        src/crypto/rx/RxVm.h
+    )
+
+    list(APPEND SOURCES_CRYPTO
+        src/crypto/randomx/aes_hash.cpp
+        src/crypto/randomx/allocator.cpp
+        src/crypto/randomx/blake2_generator.cpp
+        src/crypto/randomx/blake2/blake2b.c
+        src/crypto/randomx/bytecode_machine.cpp
+        src/crypto/randomx/dataset.cpp
+        src/crypto/randomx/instructions_portable.cpp
+        src/crypto/randomx/randomx.cpp
+        src/crypto/randomx/reciprocal.c
+        src/crypto/randomx/soft_aes.cpp
+        src/crypto/randomx/superscalar.cpp
+        src/crypto/randomx/virtual_machine.cpp
+        src/crypto/randomx/virtual_memory.cpp
+        src/crypto/randomx/vm_compiled_light.cpp
+        src/crypto/randomx/vm_compiled.cpp
+        src/crypto/randomx/vm_interpreted_light.cpp
+        src/crypto/randomx/vm_interpreted.cpp
+        src/crypto/rx/Rx.cpp
+        src/crypto/rx/RxAlgo.cpp
+        src/crypto/rx/RxBasicStorage.cpp
+        src/crypto/rx/RxCache.cpp
+        src/crypto/rx/RxConfig.cpp
+        src/crypto/rx/RxDataset.cpp
+        src/crypto/rx/RxQueue.cpp
+        src/crypto/rx/RxVm.cpp
+    )
+
+    if (CMAKE_C_COMPILER_ID MATCHES MSVC)
+        enable_language(ASM_MASM)
+        list(APPEND SOURCES_CRYPTO
+             src/crypto/randomx/jit_compiler_x86_static.asm
+             src/crypto/randomx/jit_compiler_x86.cpp
+            )
+    elseif (NOT XMRIG_ARM AND CMAKE_SIZEOF_VOID_P EQUAL 8)
+        list(APPEND SOURCES_CRYPTO
+             src/crypto/randomx/jit_compiler_x86_static.S
+             src/crypto/randomx/jit_compiler_x86.cpp
+            )
+        # cheat because cmake and ccache hate each other
+        set_property(SOURCE src/crypto/randomx/jit_compiler_x86_static.S PROPERTY LANGUAGE C)
+    elseif (XMRIG_ARM AND CMAKE_SIZEOF_VOID_P EQUAL 8)
+        list(APPEND SOURCES_CRYPTO
+             src/crypto/randomx/jit_compiler_a64_static.S
+             src/crypto/randomx/jit_compiler_a64.cpp
+            )
+        # cheat because cmake and ccache hate each other
+        set_property(SOURCE src/crypto/randomx/jit_compiler_a64_static.S PROPERTY LANGUAGE C)
+    endif()
+
+    if (CMAKE_CXX_COMPILER_ID MATCHES Clang)
+        set_source_files_properties(src/crypto/randomx/jit_compiler_x86.cpp PROPERTIES COMPILE_FLAGS -Wno-unused-const-variable)
+    endif()
+
+    if (WITH_HWLOC)
+        list(APPEND HEADERS_CRYPTO
+             src/crypto/rx/RxNUMAStorage.h
+            )
+
+        list(APPEND SOURCES_CRYPTO
+             src/crypto/rx/RxNUMAStorage.cpp
+            )
+    endif()
+
+    if (WITH_MSR AND NOT XMRIG_ARM AND CMAKE_SIZEOF_VOID_P EQUAL 8 AND (XMRIG_OS_WIN OR XMRIG_OS_LINUX))
+        add_definitions(/DXMRIG_FEATURE_MSR)
+        add_definitions(/DXMRIG_FIX_RYZEN)
+        message("-- WITH_MSR=ON")
+
+        if (XMRIG_OS_WIN)
+            list(APPEND SOURCES_CRYPTO src/crypto/rx/Rx_win.cpp)
+        elseif (XMRIG_OS_LINUX)
+            list(APPEND SOURCES_CRYPTO src/crypto/rx/Rx_linux.cpp)
+        endif()
+
+        list(APPEND HEADERS_CRYPTO src/crypto/rx/msr/MsrItem.h)
+        list(APPEND SOURCES_CRYPTO src/crypto/rx/msr/MsrItem.cpp)
+    else()
+        remove_definitions(/DXMRIG_FEATURE_MSR)
+        remove_definitions(/DXMRIG_FIX_RYZEN)
+        message("-- WITH_MSR=OFF")
+    endif()
+else()
+    remove_definitions(/DXMRIG_ALGO_RANDOMX)
+endif()

doc/ALGORITHMS.md

@@ -0,0 +1,60 @@
+# Algorithms
+
+Algorithm can be defined in 3 ways:
+
+1. By pool, using algorithm negotiation, in this case no need specify algorithm on miner side.
+2. Per pool `coin` option, currently only usable values for this option is `monero` and `arqma`.
+3. Per pool `algo` option.
+
+Option `coin` useful for pools without [algorithm negotiation](https://xmrig.com/docs/extensions/algorithm-negotiation) support or daemon to allow automatically switch algorithm in next hard fork. If you use xmrig-proxy don't need specify algorithm on miner side.
+
+## Algorithm names
+
+| Name | Memory | Version | Description | Notes |
+|------|--------|---------|-------------|-------|
+| `kawpow` | - | 6.0.0+ | KawPow (Ravencoin) | GPU only |
+| `rx/keva` | 1 MB | 5.9.0+ | RandomKEVA (RandomX variant for Keva). |  |
+| `astrobwt` | 20 MB | 5.8.0+ | AstroBWT (Dero). |  |
+| `cn-pico/tlo` | 256 KB | 5.5.0+ | CryptoNight-Pico (Talleo). |  |
+| `rx/sfx` | 2 MB | 5.4.0+ | RandomSFX (RandomX variant for Safex). |  |
+| `rx/arq` | 256 KB | 4.3.0+ | RandomARQ (RandomX variant for ArQmA). |  |
+| `rx/0` | 2 MB | 3.2.0+ | RandomX (Monero). |  |
+| `argon2/chukwa` | 512 KB | 3.1.0+ | Argon2id (Chukwa). | CPU only |
+| `argon2/wrkz` | 256 KB | 3.1.0+ | Argon2id (WRKZ) | CPU only |
+| `rx/wow` | 1 MB | 3.0.0+ | RandomWOW (RandomX variant for Wownero). |  |
+| `rx/loki` | 2 MB | 3.0.0+ | RandomXL (RandomX variant for Loki). |  |
+| `cn/fast` | 2 MB | 3.0.0+ | CryptoNight variant 1 with half iterations. |  |
+| `cn/rwz` | 2 MB | 2.14.0+ | CryptoNight variant 2 with 3/4 iterations and reversed shuffle operation. |  |
+| `cn/zls` | 2 MB | 2.14.0+ | CryptoNight variant 2 with 3/4 iterations. |  |
+| `cn/double` | 2 MB | 2.14.0+ | CryptoNight variant 2 with double iterations. |  |
+| `cn/r` | 2 MB | 2.13.0+ | CryptoNightR (Monero's variant 4). |  |
+| `cn-pico` | 256 KB | 2.10.0+ | CryptoNight-Pico. |  |
+| `cn/half` | 2 MB | 2.9.0+ | CryptoNight variant 2 with half iterations. |  |
+| `cn/2` | 2 MB | 2.8.0+ | CryptoNight variant 2. |  |
+| `cn/xao` | 2 MB | 2.6.4+ | CryptoNight variant 0 (modified). |  |
+| `cn/rto` | 2 MB | 2.6.4+ | CryptoNight variant 1 (modified). |  |
+| `cn-heavy/tube` | 4 MB | 2.6.4+ | CryptoNight-Heavy (modified). |  |
+| `cn-heavy/xhv` | 4 MB | 2.6.3+ | CryptoNight-Heavy (modified). |  |
+| `cn-heavy/0` | 4 MB | 2.6.0+ | CryptoNight-Heavy. |  |
+| `cn/1` | 2 MB | 2.5.0+ | CryptoNight variant 1. |  |
+| `cn-lite/1` | 1 MB | 2.5.0+ | CryptoNight-Lite variant 1. |  |
+| `cn-lite/0` | 1 MB | 0.8.0+ | CryptoNight-Lite variant 0. |  |
+| `cn/0` | 2 MB | 0.5.0+ | CryptoNight (original). |  |
+
+## Migration to v3
+Since version 3 mining [algorithm](#algorithm-names) should specified for each pool separately (`algo` option), earlier versions was use one global `algo` option and per pool `variant` option (this option was removed in v3). If your pool support [mining algorithm negotiation](https://github.com/xmrig/xmrig-proxy/issues/168) you may not specify this option at all.
+ 
+#### Example
+```json
+{
+  "pools": [
+    {
+      "url": "...",
+      "algo": "cn/r",
+      "coin": null
+      ...
+    }
+ ],
+ ...
+}
+```

doc/API.md

@@ -0,0 +1,66 @@
+# HTTP API
+
+If you want use HTTP API you need enable it (`"enabled": true,`) then choice `port` and optionaly `host`. API not available if miner built without HTTP support (`-DWITH_HTTP=OFF`).
+
+Offical HTTP client for API: http://workers.xmrig.info/
+
+Example configuration:
+
+```json
+"api": {
+	"id": null,
+	"worker-id": null,
+},
+"http": {
+	"enabled": false,
+	"host": "127.0.0.1",
+	"port": 0,
+	"access-token": null,
+	"restricted": true
+}
+```
+
+#### Global API options
+* **id** Miner ID, if not set created automatically.
+* **worker-id** Optional worker name, if not set will be detected automatically.
+
+#### HTTP API options,
+* **enabled** Enable (`true`) or disable (`false`) HTTP API.
+* **host** Host for incoming connections `http://<host>:<port>`, to allow connections from all interfaces use `0.0.0.0` (IPv4) or `::` (IPv4+IPv6).
+* **port** Port for incoming connections `http://<host>:<port>`, zero port is valid option and means random port.
+* **access-token** [Bearer](https://gist.github.com/xmrig/c75fdd1f8e0f3bac05500be2ab718f8e#file-api-html-L54) access token to secure access to API. Miner support this token only via `Authorization` header.
+* **restricted** Use `false` to allow remote configuration.
+
+If you prefer use command line options instead of config file, you can use options: `--api-id`, `--api-worker-id`, `--http-enabled`, `--http-host`, `--http-access-token`, `--http-port`, `--http-no-restricted`.
+
+Versions before 2.15 was use another options for API https://github.com/xmrig/xmrig/issues/1007
+
+## Endpoints
+
+### GET /1/summary
+
+Get miner summary information. [Example](api/1/summary.json).
+
+### GET /1/threads
+
+Get detailed information about miner threads. [Example](api/1/threads.json).
+
+
+## Restricted endpoints
+
+All API endpoints below allow access to sensitive information and remote configure miner. You should set `access-token` and allow unrestricted access (`"restricted": false`).
+
+### GET /1/config
+
+Get current miner configuration. [Example](api/1/config.json).
+
+
+### PUT /1/config
+
+Update current miner configuration. Common use case, get current configuration, make changes, and upload it to miner.
+
+Curl example:
+
+```
+curl -v --data-binary @config.json -X PUT -H "Content-Type: application/json" -H "Authorization: Bearer SECRET" http://127.0.0.1:44444/1/config
+```

doc/CHANGELOG_OLD.md

@@ -0,0 +1,462 @@
+# v4.6.2-beta
+- [#1274](https://github.com/xmrig/xmrig/issues/1274) Added `--cuda-devices` command line option.
+- [#1277](https://github.com/xmrig/xmrig/pull/1277) Fixed function names for clang on Apple.
+
+# v4.6.1-beta
+- [#1272](https://github.com/xmrig/xmrig/pull/1272) Optimized hashrate calculation.
+- [#1273](https://github.com/xmrig/xmrig/issues/1273) Fixed crash when use `GET /2/backends` API endpoint with disabled CUDA.
+
+# v4.6.0-beta
+- [#1263](https://github.com/xmrig/xmrig/pull/1263) Added new option `dataset_host` for NVIDIA GPUs with less than 4 GB memory (RandomX only).
+
+# v4.5.0-beta
+- Added NVIDIA CUDA support via external [CUDA plugun](https://github.com/xmrig/xmrig-cuda). XMRig now is unified 3 in 1 miner.
+
+# v4.4.0-beta
+- [#1068](https://github.com/xmrig/xmrig/pull/1068) Added support for `self-select` stratum protocol extension.
+- [#1240](https://github.com/xmrig/xmrig/pull/1240) Sync with the latest RandomX code.
+- [#1241](https://github.com/xmrig/xmrig/issues/1241) Fixed regression with colors on old Windows systems.
+- [#1243](https://github.com/xmrig/xmrig/pull/1243) Fixed incorrect OpenCL memory size detection in some cases.
+- [#1247](https://github.com/xmrig/xmrig/pull/1247) Fixed ARM64 RandomX code alignment.
+- [#1248](https://github.com/xmrig/xmrig/pull/1248) Fixed RandomX code cache cleanup on iOS/Darwin.
+
+# v4.3.1-beta
+- Fixed regression in v4.3.0, miner didn't create `cn` mining profile with default config example.
+
+# v4.3.0-beta
+- [#1227](https://github.com/xmrig/xmrig/pull/1227) Added new algorithm `rx/arq`, RandomX variant for upcoming ArQmA fork.
+- [#808](https://github.com/xmrig/xmrig/issues/808#issuecomment-539297156) Added experimental support for persistent memory for CPU mining threads.
+- [#1221](https://github.com/xmrig/xmrig/issues/1221) Improved RandomX dataset memory usage and initialization speed for NUMA machines.
+
+# v4.2.1-beta
+- [#1150](https://github.com/xmrig/xmrig/issues/1150) Fixed build on FreeBSD.
+- [#1175](https://github.com/xmrig/xmrig/issues/1175) Fixed support for systems where total count of NUMA nodes not equal usable nodes count.
+- [#1199](https://github.com/xmrig/xmrig/issues/1199) Fixed excessive memory allocation for OpenCL threads with low intensity.
+- [#1212](https://github.com/xmrig/xmrig/issues/1212) Fixed low RandomX performance after fast algorithm switching.
+
+# v4.2.0-beta
+- [#1202](https://github.com/xmrig/xmrig/issues/1202) Fixed algorithm verification in donate strategy.
+- Added per pool option `coin` with single possible value `monero` for pools without algorithm negotiation, for upcoming Monero fork.
+- Added config option `cpu/max-threads-hint` and command line option `--cpu-max-threads-hint`.
+
+# v4.1.0-beta
+- **OpenCL backend disabled by default.**.
+- [#1183](https://github.com/xmrig/xmrig/issues/1183) Fixed compatibility with systemd.
+- [#1185](https://github.com/xmrig/xmrig/pull/1185) Added JIT compiler for RandomX on ARMv8.
+- Improved API endpoint `GET /2/backends` and added support for this endpoint to [workers.xmrig.info](http://workers.xmrig.info).
+- Added command line option `--no-cpu` to disable CPU backend.
+- Added OpenCL specific command line options: `--opencl`, `--opencl-devices`, `--opencl-platform`, `--opencl-loader` and `--opencl-no-cache`.
+- Removed command line option `--http-enabled`, HTTP API enabled automatically if any other `--http-*` option provided.
+
+# v4.0.1-beta
+- [#1177](https://github.com/xmrig/xmrig/issues/1177) Fixed compatibility with old AMD drivers.
+- [#1180](https://github.com/xmrig/xmrig/issues/1180) Fixed possible duplicated shares after algorithm switching.
+- Added support for case if not all backend threads successfully started.
+- Fixed wrong config file permissions after write (only gcc builds on recent Windows 10 affected).
+
+# v4.0.0-beta
+- [#1172](https://github.com/xmrig/xmrig/issues/1172) **Added OpenCL mining backend.**
+  - [#268](https://github.com/xmrig/xmrig-amd/pull/268) [#270](https://github.com/xmrig/xmrig-amd/pull/270) [#271](https://github.com/xmrig/xmrig-amd/pull/271) [#273](https://github.com/xmrig/xmrig-amd/pull/273) [#274](https://github.com/xmrig/xmrig-amd/pull/274) [#1171](https://github.com/xmrig/xmrig/pull/1171) Added RandomX support for OpenCL, thanks [@SChernykh](https://github.com/SChernykh).
+- Algorithm `cn/wow` removed, as no longer alive. 
+
+# v3.2.0
+- Added per pool option `coin` with single possible value `monero` for pools without algorithm negotiation, for upcoming Monero fork.
+- [#1183](https://github.com/xmrig/xmrig/issues/1183) Fixed compatibility with systemd.
+
+# v3.1.3
+- [#1180](https://github.com/xmrig/xmrig/issues/1180) Fixed possible duplicated shares after algorithm switching.
+- Fixed wrong config file permissions after write (only gcc builds on recent Windows 10 affected).
+
+# v3.1.2
+- Many RandomX optimizations and fixes.
+  - [#1132](https://github.com/xmrig/xmrig/issues/1132) Fixed build on CentOS 7.
+  - [#1163](https://github.com/xmrig/xmrig/pull/1163) Optimized soft AES code, up to +30% hashrate on CPU without AES support and other optimizations.
+  - [#1166](https://github.com/xmrig/xmrig/pull/1166) Fixed crash when initialize dataset with big threads count (eg 272).
+  - [#1168](https://github.com/xmrig/xmrig/pull/1168) Optimized loading from scratchpad.
+- [#1128](https://github.com/xmrig/xmrig/issues/1128) Fixed CMake 2.8 compatibility.
+
+# v3.1.1
+- [#1133](https://github.com/xmrig/xmrig/issues/1133) Fixed syslog regression.
+- [#1138](https://github.com/xmrig/xmrig/issues/1138) Fixed multiple network bugs.
+- [#1141](https://github.com/xmrig/xmrig/issues/1141) Fixed log in background mode.
+- [#1142](https://github.com/xmrig/xmrig/pull/1142) RandomX hashrate improved by 0.5-1.5% depending on variant and CPU.
+- [#1146](https://github.com/xmrig/xmrig/pull/1146) Fixed race condition in RandomX thread init.
+- [#1148](https://github.com/xmrig/xmrig/pull/1148) Fixed, on Linux linker marking entire executable as having an executable stack.
+- Fixed, for Argon2 algorithms command line options like `--threads` was ignored.
+- Fixed command line options for single pool, free order allowed again.
+
+# v3.1.0
+- [#1107](https://github.com/xmrig/xmrig/issues/1107#issuecomment-522235892) Added Argon2 algorithm family: `argon2/chukwa` and `argon2/wrkz`.
+
+# v3.0.0
+- **[#1111](https://github.com/xmrig/xmrig/pull/1111) Added RandomX (`rx/test`) algorithm for testing and benchmarking.**
+- **[#1036](https://github.com/xmrig/xmrig/pull/1036) Added RandomWOW (`rx/wow`) algorithm for [Wownero](http://wownero.org/).**
+- **[#1050](https://github.com/xmrig/xmrig/pull/1050) Added RandomXL (`rx/loki`) algorithm for [Loki](https://loki.network/).**
+- **[#1077](https://github.com/xmrig/xmrig/issues/1077) Added NUMA support via hwloc**.
+- **Added flexible [multi algorithm](doc/CPU.md) configuration.**
+- **Added unlimited switching between incompatible algorithms, all mining options can be changed in runtime.**
+- [#257](https://github.com/xmrig/xmrig-nvidia/pull/257) New logging subsystem, file and syslog now always without colors.
+- [#314](https://github.com/xmrig/xmrig-proxy/issues/314) Added donate over proxy feature.
+- [#1007](https://github.com/xmrig/xmrig/issues/1007) Old HTTP API backend based on libmicrohttpd, replaced to custom HTTP server (libuv + http_parser).
+- [#1010](https://github.com/xmrig/xmrig/pull/1010#issuecomment-482632107) Added daemon support (solo mining).
+- [#1066](https://github.com/xmrig/xmrig/issues/1066#issuecomment-518080529) Added error message if pool not ready for RandomX.
+- [#1105](https://github.com/xmrig/xmrig/issues/1105) Improved auto configuration for `cn-pico` algorithm.
+- Added commands `pause` and `resume` via JSON RPC 2.0 API (`POST /json_rpc`).
+- Added command line option `--export-topology` for export hwloc topology to a XML file.
+- Breaked backward compatibility with previous configs and command line, `variant` option replaced to `algo`, global option `algo` removed, all CPU related settings moved to `cpu` object.
+- Options `av`, `safe` and `max-cpu-usage` removed.
+- Algorithm `cn/msr` renamed to `cn/fast`.
+- Algorithm `cn/xtl` removed.
+- API endpoint `GET /1/threads` replaced to `GET /2/backends`.
+- Added global uptime and extended connection information in API.
+- API now return current algorithm.
+
+# v2.99.6-beta
+- Added commands `pause` and `resume` via JSON RPC 2.0 API (`POST /json_rpc`).
+- Fixed autoconfig regression (since 2.99.5), mostly `rx/wow` was affected by this bug.
+- Fixed user job recovery after donation round.
+- Information about AVX2 CPU feature how hidden in miner summary.
+
+# v2.99.5-beta
+- [#1066](https://github.com/xmrig/xmrig/issues/1066#issuecomment-518080529) Fixed crash and added error message if pool not ready for RandomX.
+- [#1092](https://github.com/xmrig/xmrig/issues/1092) Fixed crash if wrong CPU affinity used.
+- [#1103](https://github.com/xmrig/xmrig/issues/1103) Improved auto configuration for RandomX for CPUs where L2 cache is limiting factor.
+- [#1105](https://github.com/xmrig/xmrig/issues/1105) Improved auto configuration for `cn-pico` algorithm.
+- [#1106](https://github.com/xmrig/xmrig/issues/1106) Fixed `hugepages` field in summary API. 
+- Added alternative short format for CPU threads.
+- Changed format for CPU threads with intensity above 1.
+- Name for reference RandomX configuration changed to `rx/test` to avoid potential conflicts in future.
+
+# v2.99.4-beta
+- [#1062](https://github.com/xmrig/xmrig/issues/1062) Fixed 32 bit support. **32 bit is slow and deprecated**.
+- [#1088](https://github.com/xmrig/xmrig/pull/1088) Fixed macOS compilation.
+- [#1095](https://github.com/xmrig/xmrig/pull/1095) Fixed compatibility with hwloc 1.10.x.
+- Optimized RandomX initialization and switching, fixed rare crash when re-initialize dataset.
+- Fixed ARM build with hwloc.
+
+# v2.99.3-beta
+- [#1082](https://github.com/xmrig/xmrig/issues/1082) Fixed hwloc auto configuration on AMD FX CPUs.
+- Added command line option `--export-topology` for export hwloc topology to a XML file.
+
+# v2.99.2-beta
+- [#1077](https://github.com/xmrig/xmrig/issues/1077) Added NUMA support via **hwloc**.
+- Fixed miner freeze when switch between RandomX variants.
+- Fixed dataset initialization speed on Linux if thread affinity was used.
+
+# v2.99.1-beta
+- [#1072](https://github.com/xmrig/xmrig/issues/1072) Fixed RandomX `seed_hash` re-initialization.
+
+# v2.99.0-beta
+- [#1050](https://github.com/xmrig/xmrig/pull/1050) Added RandomXL algorithm for [Loki](https://loki.network/), algorithm name used by miner is `randomx/loki` or `rx/loki`.
+- Added [flexible](https://github.com/xmrig/xmrig/blob/evo/doc/CPU.md) multi algorithm configuration.
+- Added unlimited switching between incompatible algorithms, all mining options can be changed in runtime.
+- Breaked backward compatibility with previous configs and command line, `variant` option replaced to `algo`, global option `algo` removed, all CPU related settings moved to `cpu` object.
+- Options `av`, `safe` and `max-cpu-usage` removed.
+- Algorithm `cn/msr` renamed to `cn/fast`.
+- Algorithm `cn/xtl` removed.
+- API endpoint `GET /1/threads` replaced to `GET /2/backends`.
+
+# v2.16.0-beta
+- [#1036](https://github.com/xmrig/xmrig/pull/1036) Added RandomWOW (RandomX with different preferences) algorithm support for [Wownero](http://wownero.org/).
+  - Algorithm name used by miner is `randomx/wow` or `rx/wow`.
+  - Currently runtime algorithm switching NOT supported with other algorithms.
+
+# v2.15.4-beta
+- Added global uptime and extended connection information in API.
+- API now return current algorithm instead of global algorithm specified in config.
+- This version also include all changes from stable version v2.14.4.
+
+# v2.15.3-beta
+- [#1014](https://github.com/xmrig/xmrig/issues/1014) Fixed regression, default value for `algo` option was not applied.
+
+# v2.15.2-beta
+- [#1010](https://github.com/xmrig/xmrig/pull/1010#issuecomment-482632107) Added daemon support (solo mining).
+- [#1012](https://github.com/xmrig/xmrig/pull/1012) Fixed compatibility with clang 9.
+- Config subsystem was rewritten, internally JSON is primary format now.
+- Fixed regression, big HTTP responses was truncated.
+
+# v2.15.1-beta
+- [#1007](https://github.com/xmrig/xmrig/issues/1007) Old HTTP API backend based on libmicrohttpd, replaced to custom HTTP server (libuv + http_parser).
+- [#257](https://github.com/xmrig/xmrig-nvidia/pull/257) New logging subsystem, file and syslog now always without colors.
+
+# v2.15.0-beta
+- [#314](https://github.com/xmrig/xmrig-proxy/issues/314) Added donate over proxy feature.
+  - Added new option `donate-over-proxy`.
+  - Added real graceful exit.
+  
+# v2.14.4
+- [#992](https://github.com/xmrig/xmrig/pull/992)  Fixed compilation with Clang 3.5.
+- [#1012](https://github.com/xmrig/xmrig/pull/1012) Fixed compilation with Clang 9.0.
+- In HTTP API for unknown hashrate now used `null` instead of `0.0`.
+- Fixed MSVC 2019 version detection.
+- Removed obsolete automatic variants.
+
+# v2.14.1
+* [#975](https://github.com/xmrig/xmrig/issues/975) Fixed crash on Linux if double thread mode used.
+
+# v2.14.0
+- **[#969](https://github.com/xmrig/xmrig/pull/969) Added new algorithm `cryptonight/rwz`, short alias `cn/rwz` (also known as CryptoNight ReverseWaltz), for upcoming [Graft](https://www.graft.network/) fork.**
+- **[#931](https://github.com/xmrig/xmrig/issues/931) Added new algorithm `cryptonight/zls`, short alias `cn/zls` for [Zelerius Network](https://zelerius.org) fork.**
+- **[#940](https://github.com/xmrig/xmrig/issues/940) Added new algorithm `cryptonight/double`, short alias `cn/double` (also known as CryptoNight HeavyX), for [X-CASH](https://x-cash.org/).**
+- [#951](https://github.com/xmrig/xmrig/issues/951#issuecomment-469581529) Fixed crash if AVX was disabled on OS level.
+- [#952](https://github.com/xmrig/xmrig/issues/952) Fixed compile error on some Linux.
+- [#957](https://github.com/xmrig/xmrig/issues/957#issuecomment-468890667) Added support for embedded config.
+- [#958](https://github.com/xmrig/xmrig/pull/958) Fixed incorrect user agent on ARM platforms.
+- [#968](https://github.com/xmrig/xmrig/pull/968) Optimized `cn/r` algorithm performance.
+
+# v2.13.1
+- [#946](https://github.com/xmrig/xmrig/pull/946) Optimized software AES implementations for CPUs without hardware AES support. `cn/r`, `cn/wow` up to 2.6 times faster, 4-9% improvements for other algorithms.
+
+# v2.13.0
+- **[#938](https://github.com/xmrig/xmrig/issues/938) Added support for new algorithm `cryptonight/r`, short alias `cn/r` (also known as CryptoNightR or CryptoNight variant 4), for upcoming [Monero](https://www.getmonero.org/) fork on March 9, thanks [@SChernykh](https://github.com/SChernykh).**
+- [#939](https://github.com/xmrig/xmrig/issues/939) Added support for dynamic (runtime) pools reload.
+- [#932](https://github.com/xmrig/xmrig/issues/932) Fixed `cn-pico` hashrate drop, regression since v2.11.0.
+
+# v2.12.0
+- [#929](https://github.com/xmrig/xmrig/pull/929) Added support for new algorithm `cryptonight/wow`, short alias `cn/wow` (also known as CryptonightR), for upcoming [Wownero](http://wownero.org) fork on February 14.
+
+# v2.11.0
+- [#928](https://github.com/xmrig/xmrig/issues/928) Added support for new algorithm `cryptonight/gpu`, short alias `cn/gpu` (original name `cryptonight-gpu`), for upcoming [Ryo currency](https://ryo-currency.com) fork on February 14.
+- [#749](https://github.com/xmrig/xmrig/issues/749) Added support for detect hardware AES in runtime on ARMv8 platforms.
+- [#292](https://github.com/xmrig/xmrig/issues/292) Fixed build on ARMv8 platforms if compiler not support hardware AES.
+
+# v2.10.0
+- [#904](https://github.com/xmrig/xmrig/issues/904) Added new algorithm `cn-pico/trtl` (aliases `cryptonight-turtle`, `cn-trtl`) for upcoming TurtleCoin (TRTL) fork.
+- Default value for option `max-cpu-usage` changed to `100` also this option now deprecated.
+
+# v2.9.4
+- [#913](https://github.com/xmrig/xmrig/issues/913) Fixed Masari (MSR) support (this update required for upcoming fork).
+- [#915](https://github.com/xmrig/xmrig/pull/915) Improved security, JIT memory now read-only after patching.
+
+# v2.9.3
+- [#909](https://github.com/xmrig/xmrig/issues/909) Fixed compile errors on FreeBSD.
+- [#912](https://github.com/xmrig/xmrig/pull/912) Fixed, C++ implementation of `cn/half` was produce up to 13% of invalid hashes.
+
+# v2.9.2
+- [#907](https://github.com/xmrig/xmrig/pull/907) Fixed crash on Linux.
+
+# v2.9.1
+- Restored compatibility with https://stellite.hashvault.pro.
+
+# v2.9.0
+- [#899](https://github.com/xmrig/xmrig/issues/899) Added support for new algorithm `cn/half` for Masari and Stellite forks.
+- [#834](https://github.com/xmrig/xmrig/pull/834) Added ASM optimized code for AMD Bulldozer.
+- [#839](https://github.com/xmrig/xmrig/issues/839) Fixed FreeBSD compile.
+- [#857](https://github.com/xmrig/xmrig/pull/857) Fixed impossible to build for macOS without clang.
+
+# v2.8.3
+- [#813](https://github.com/xmrig/xmrig/issues/813) Fixed critical bug with Minergate pool and variant 2.
+
+# v2.8.1
+- [#768](https://github.com/xmrig/xmrig/issues/768) Fixed build with Visual Studio 2015.
+- [#769](https://github.com/xmrig/xmrig/issues/769) Fixed regression, some ANSI escape sequences was in log with disabled colors.
+- [#777](https://github.com/xmrig/xmrig/issues/777) Better report about pool connection issues. 
+- Simplified checks for ASM auto detection, only AES support necessary.
+- Added missing options to `--help` output.
+
+# v2.8.0
+- **[#753](https://github.com/xmrig/xmrig/issues/753) Added new algorithm [CryptoNight variant 2](https://github.com/xmrig/xmrig/issues/753) for Monero fork, thanks [@SChernykh](https://github.com/SChernykh).**
+  - Added global and per thread option `"asm"` and and command line equivalent.
+- **[#758](https://github.com/xmrig/xmrig/issues/758) Added SSL/TLS support for secure connections to pools.**
+  - Added per pool options `"tls"` and `"tls-fingerprint"` and command line equivalents.
+- [#767](https://github.com/xmrig/xmrig/issues/767) Added config autosave feature, same with GPU miners.  
+- [#245](https://github.com/xmrig/xmrig-proxy/issues/245) Fixed API ID collision when run multiple miners on same machine.
+- [#757](https://github.com/xmrig/xmrig/issues/757) Fixed send buffer overflow.
+
+# v2.6.4
+- [#700](https://github.com/xmrig/xmrig/issues/700) `cryptonight-lite/ipbc` replaced to `cryptonight-heavy/tube` for **Bittube (TUBE)**.
+- Added `cryptonight/rto` (cryptonight variant 1 with IPBC/TUBE mod) variant for **Arto (RTO)** coin.
+- Added `cryptonight/xao` (original cryptonight with bigger iteration count) variant for **Alloy (XAO)** coin.
+- Better variant detection for **nicehash.com** and **minergate.com**.
+- [#692](https://github.com/xmrig/xmrig/issues/692) Added support for specify both algorithm and variant via single `algo` option.
+
+# v2.6.3
+- **Added support for new cryptonight-heavy variant xhv** (`cn-heavy/xhv`) for upcoming Haven Protocol fork.
+- **Added support for new cryptonight variant msr** (`cn/msr`) also known as `cryptonight-fast` for upcoming Masari fork.
+- Added new detailed hashrate report.
+- [#446](https://github.com/xmrig/xmrig/issues/446) Likely fixed SIGBUS error on 32 bit ARM CPUs.
+- [#551](https://github.com/xmrig/xmrig/issues/551) Fixed `cn-heavy` algorithm on ARMv8.
+- [#614](https://github.com/xmrig/xmrig/issues/614) Fixed display issue with huge pages percentage when colors disabled.
+- [#615](https://github.com/xmrig/xmrig/issues/615) Fixed build without libcpuid.
+- [#629](https://github.com/xmrig/xmrig/pull/629) Fixed file logging with non-seekable files.
+- [#672](https://github.com/xmrig/xmrig/pull/672) Reverted back `cryptonight-light` and exit if no valid algorithm specified.
+
+# v2.6.2
+ - [#607](https://github.com/xmrig/xmrig/issues/607) Fixed donation bug.
+ - [#610](https://github.com/xmrig/xmrig/issues/610) Fixed ARM build.
+
+# v2.6.1
+ - [#168](https://github.com/xmrig/xmrig-proxy/issues/168) Added support for [mining algorithm negotiation](https://github.com/xmrig/xmrig-proxy/blob/dev/doc/STRATUM_EXT.md#1-mining-algorithm-negotiation).
+ - Added IPBC coin support, base algorithm `cn-lite` variant `ipbc`.
+ - [#581](https://github.com/xmrig/xmrig/issues/581) Added support for upcoming Stellite (XTL) fork, base algorithm `cn` variant `xtl`, variant can set now, no need do it after fork.
+ - Added support for **rig-id** stratum protocol extensions, compatible with xmr-stak.
+ - Changed behavior for option `variant=-1` for `cryptonight`, now variant is `1` by default, if you mine old coins need change `variant` to `0`.
+ - A lot of small fixes and better unification with proxy code.
+
+# v2.6.0-beta3
+- [#563](https://github.com/xmrig/xmrig/issues/563) **Added [advanced threads mode](https://github.com/xmrig/xmrig/issues/563), now possible configure each thread individually.**
+- [#255](https://github.com/xmrig/xmrig/issues/563) Low power mode extended to **triple**, **quard** and **penta** modes.
+- [#519](https://github.com/xmrig/xmrig/issues/519) Fixed high donation levels, improved donation start time randomization.
+- [#554](https://github.com/xmrig/xmrig/issues/554) Fixed regression with `print-time` option.
+
+# v2.6.0-beta2
+- Improved performance for `cryptonight v7` especially in double hash mode.
+- [#499](https://github.com/xmrig/xmrig/issues/499) IPv6 disabled for internal HTTP API by default, was causing issues on some systems.
+- Added short aliases for algorithm names: `cn`, `cn-lite` and `cn-heavy`.
+- Fixed regressions (v2.6.0-beta1 affected)
+  - [#494](https://github.com/xmrig/xmrig/issues/494) Command line option `--donate-level` was broken.
+  - [#502](https://github.com/xmrig/xmrig/issues/502) Build without libmicrohttpd was broken.
+  - Fixed nonce calculation for `--av 4` (software AES, double hash) was causing reduction of effective hashrate and rejected shares on nicehash.
+
+# v2.6.0-beta1
+ - [#476](https://github.com/xmrig/xmrig/issues/476) **Added Cryptonight-Heavy support for Sumokoin ASIC resistance fork.**
+ - HTTP server now runs in main loop, it make possible easy extend API without worry about thread synchronization.
+ - Added initial graceful reload support, miner will reload configuration if config file changed, disabled by default until it will be fully implemented and tested.
+ - Added API endpoint `PUT /1/config` to update current config.
+ - Added API endpoint `GET /1/config` to get current active config.
+ - Added API endpoint `GET /1/threads` to get current active threads configuration.
+ - API endpoint `GET /` now deprecated, use `GET /1/summary` instead.
+ - Added `--api-no-ipv6` and similar config option to disable IPv6 support for HTTP API.
+ - Added `--api-no-restricted` to enable full access to api, this option has no effect if `--api-access-token` not specified.
+
+# v2.5.3
+- Fixed critical bug, in some cases miner was can't recovery connection and switch to failover pool, version 2.5.2 affected. If you use v2.6.0-beta3 this issue doesn't concern you.
+- [#499](https://github.com/xmrig/xmrig/issues/499) IPv6 support disabled for internal HTTP API.
+- Added workaround for nicehash.com if you use `cryptonightv7.<region>.nicehash.com` option `variant=1` will be set automatically.
+
+# v2.5.2
+- [#448](https://github.com/xmrig/xmrig/issues/478) Fixed broken reconnect.
+
+# v2.5.1
+- [#454](https://github.com/xmrig/xmrig/issues/454) Fixed build with libmicrohttpd version below v0.9.35.
+- [#456](https://github.com/xmrig/xmrig/issues/459) Verbose errors related to donation pool was not fully silenced.
+- [#459](https://github.com/xmrig/xmrig/issues/459) Fixed regression (version 2.5.0 affected) with connection to **xmr.f2pool.com**.
+
+# v2.5.0
+- [#434](https://github.com/xmrig/xmrig/issues/434) **Added support for Monero v7 PoW, scheduled on April 6.**
+- Added full IPv6 support.
+- Added protocol extension, when use the miner with xmrig-proxy 2.5+ no more need manually specify `nicehash` option.
+- [#123](https://github.com/xmrig/xmrig-proxy/issues/123) Fixed regression (all versions since 2.4 affected) fragmented responses from pool/proxy was parsed incorrectly.
+- [#428](https://github.com/xmrig/xmrig/issues/428) Fixed regression (version 2.4.5 affected) with CPU cache size detection.
+
+# v2.4.5
+- [#324](https://github.com/xmrig/xmrig/pull/324) Fixed build without libmicrohttpd (CMake cache issue).
+- [#341](https://github.com/xmrig/xmrig/issues/341) Fixed wrong exit code and added command line option `--dry-run`.
+- [#385](https://github.com/xmrig/xmrig/pull/385) Up to 20% performance increase for non-AES CPU and fixed Intel Core 2 cache detection.
+
+# v2.4.4
+ - Added libmicrohttpd version to --version output.
+ - Fixed bug in singal handler, in some cases miner wasn't shutdown properly.
+ - Fixed recent MSVC 2017 version detection.
+ - [#279](https://github.com/xmrig/xmrig/pull/279) Fixed build on some macOS versions.
+
+# v2.4.3
+ - [#94](https://github.com/xmrig/xmrig/issues/94#issuecomment-342019257) [#216](https://github.com/xmrig/xmrig/issues/216) Added **ARMv8** and **ARMv7** support. Hardware AES supported, thanks [Imran Yusuff](https://github.com/imranyusuff).
+ - [#157](https://github.com/xmrig/xmrig/issues/157) [#196](https://github.com/xmrig/xmrig/issues/196) Fixed Linux compile issues.
+ - [#184](https://github.com/xmrig/xmrig/issues/184) Fixed cache size detection for CPUs with disabled Hyper-Threading.
+ - [#200](https://github.com/xmrig/xmrig/issues/200) In some cases miner was doesn't write log to stdout.
+
+# v2.4.2
+ - [#60](https://github.com/xmrig/xmrig/issues/60) Added FreeBSD support, thanks [vcambur](https://github.com/vcambur).
+ - [#153](https://github.com/xmrig/xmrig/issues/153) Fixed issues with dwarfpool.com.
+ 
+# v2.4.1
+  - [#147](https://github.com/xmrig/xmrig/issues/147) Fixed comparability with monero-stratum.
+
+# v2.4.0
+ - Added [HTTP API](https://github.com/xmrig/xmrig/wiki/API).
+ - Added comments support in config file.
+ - libjansson replaced to rapidjson.
+ - [#98](https://github.com/xmrig/xmrig/issues/98) Ignore `keepalive` option with minergate.com and nicehash.com.
+ - [#101](https://github.com/xmrig/xmrig/issues/101) Fixed MSVC 2017 (15.3) compile time version detection.
+ - [#108](https://github.com/xmrig/xmrig/issues/108) Silently ignore invalid values for `donate-level` option.
+ - [#111](https://github.com/xmrig/xmrig/issues/111) Fixed build without AEON support.
+ 
+# v2.3.1
+- [#68](https://github.com/xmrig/xmrig/issues/68) Fixed compatibility with Docker containers, was nothing print on console.
+
+# v2.3.0
+- Added `--cpu-priority` option (0 idle, 2 normal to 5 highest).
+- Added `--user-agent` option, to set custom user-agent string for pool. For example `cpuminer-multi/0.1`.
+- Added `--no-huge-pages` option, to disable huge pages support.
+- [#62](https://github.com/xmrig/xmrig/issues/62) Don't send the login to the dev pool.
+- Force reconnect if pool block miner IP address. helps switch to backup pool.
+- Fixed: failed open default config file if path contains non English characters.
+- Fixed: error occurred if try use unavailable stdin or stdout, regression since version 2.2.0.
+- Fixed: message about huge pages support successfully enabled on Windows was not shown in release builds.
+
+# v2.2.1
+- Fixed [terminal issues](https://github.com/xmrig/xmrig-proxy/issues/2#issuecomment-319914085) after exit on Linux and OS X.
+
+# v2.2.0
+- [#46](https://github.com/xmrig/xmrig/issues/46) Restored config file support. Now possible use multiple config files and combine with command line options also added support for default config.
+- Improved colors support on Windows, now used uv_tty, legacy code removed.
+- QuickEdit Mode now disabled on Windows.
+- Added interactive commands in console window:: **h**ashrate, **p**ause, **r**esume.
+- Fixed autoconf mode for AMD FX CPUs.
+
+# v2.1.0
+- [#40](https://github.com/xmrig/xmrig/issues/40)
+Improved miner shutdown, fixed crash on exit for Linux and OS X.
+- Fixed, login request was contain malformed JSON if username or password has some special characters for example `\`. 
+- [#220](https://github.com/fireice-uk/xmr-stak-cpu/pull/220) Better support for Round Robin DNS, IP address now always chosen randomly instead of stuck on first one.
+- Changed donation address, new [xmrig-proxy](https://github.com/xmrig/xmrig-proxy) is coming soon.
+
+# v2.0.2
+- Better deal with possible duplicate jobs from pool, show warning and ignore duplicates.
+- For Windows builds libuv updated to version 1.13.1 and gcc to 7.1.0.
+
+# v2.0.1
+ - [#27](https://github.com/xmrig/xmrig/issues/27) Fixed possibility crash on 32bit systems.
+
+# v2.0.0
+ - Option `--backup-url` removed, instead now possibility specify multiple pools for example: `-o example1.com:3333 -u user1 -p password1 -k -o example2.com:5555 -u user2 -o example3.com:4444 -u user3`
+ - [#15](https://github.com/xmrig/xmrig/issues/15) Added option `-l, --log-file=FILE` to write log to file.
+ - [#15](https://github.com/xmrig/xmrig/issues/15) Added option `-S, --syslog` to use syslog for logging, Linux only.
+ - [#18](https://github.com/xmrig/xmrig/issues/18) Added nice messages for accepted/rejected shares with diff and network latency.
+ - [#20](https://github.com/xmrig/xmrig/issues/20) Fixed `--cpu-affinity` for more than 32 threads.
+ - Fixed Windows XP support.
+ - Fixed regression, option `--no-color` was not fully disable colored output.
+ - Show resolved pool IP address in miner output.
+ 
+# v1.0.1
+- Fix broken software AES implementation, app has crashed if CPU not support AES-NI, only version 1.0.0 affected.
+
+# v1.0.0
+- Miner complete rewritten in C++ with libuv.
+- This version should be fully compatible (except config file) with previos versions, many new nice features will come in next versions.
+- This is still beta. If you found regression, stability or perfomance issues or have an idea for new feature please fell free to open new [issue](https://github.com/xmrig/xmrig/issues/new).
+- Added new option `--print-time=N`, print hashrate report every N seconds.
+- New hashrate reports, by default every 60 secons.
+- Added Microsoft Visual C++ 2015 and 2017 support.
+- Removed dependency on libcurl.
+- To compile this version from source please switch to [dev](https://github.com/xmrig/xmrig/tree/dev) branch.
+
+# v0.8.2
+- Fixed L2 cache size detection for AMD CPUs (Bulldozer/Piledriver/Steamroller/Excavator architecture).
+
+# v0.8.2
+- Fixed L2 cache size detection for AMD CPUs (Bulldozer/Piledriver/Steamroller/Excavator architecture).
+- Fixed gcc 7.1 support.
+
+# v0.8.1
+- Added nicehash support, detects automaticaly by pool URL, for example `cryptonight.eu.nicehash.com:3355` or manually via option `--nicehash`.
+
+# v0.8.0
+- Added double hash mode, also known as lower power mode. `--av=2` and `--av=4`.
+- Added smart automatic CPU configuration. Default threads count now depends on size of the L3 cache of CPU.
+- Added CryptoNight-Lite support for AEON `-a cryptonight-lite`.
+- Added `--max-cpu-usage` option for auto CPU configuration mode.
+- Added `--safe` option for adjust threads and algorithm variations to current CPU.
+- No more manual steps to enable huge pages on Windows. XMRig will do it automatically.
+- Removed BMI2 algorithm variation.
+- Removed default pool URL.
+
+# v0.6.0
+- Added automatic cryptonight self test.
+- New software AES algorithm variation. Will be automatically selected if cpu not support AES-NI.
+- Added 32 bit builds.
+- Documented [algorithm variations](https://github.com/xmrig/xmrig#algorithm-variations).
+
+# v0.5.0
+- Initial public release.

doc/CPU.md

@@ -0,0 +1,105 @@
+# CPU backend
+
+All CPU related settings contains in one `cpu` object in config file, CPU backend allow specify multiple profiles and allow switch between them without restrictions by pool request or config change. Default auto-configuration create reasonable minimum of profiles which cover all supported algorithms.
+
+### Example
+
+Example below demonstrate all primary ideas of flexible profiles configuration:
+
+* `"rx/wow"` Exact match to algorithm `rx/wow`, defined 4 threads without CPU affinity.
+* `"cn"` Default failback profile for all `cn/*` algorithms, defined 2 threads with CPU affinity, another failback profiles is `cn-lite`, `cn-heavy` and `rx`.
+* `"cn-lite"` Default failback profile for all `cn-lite/*` algorithms, defined 2 double threads with CPU affinity.
+* `"cn-pico"` Alternative short object format.
+* `"custom-profile"` Custom user defined profile.
+* `"*"` Failback profile for all unhandled by other profiles algorithms.
+* `"cn/r"` Exact match, alias to profile `custom-profile`.
+* `"cn/0"` Exact match, disabled algorithm.
+
+```json
+{
+    "cpu": {
+        "enabled": true,
+        "huge-pages": true,
+        "hw-aes": null,
+        "priority": null,
+        "asm": true,
+        "rx/wow": [-1, -1, -1, -1],
+        "cn": [
+            [1, 0],
+            [1, 2]
+        ],
+        "cn-lite": [
+            [2, 0],
+            [2, 2]
+        ],
+        "cn-pico": {
+            "intensity": 2,
+            "threads": 8,
+            "affinity": -1
+        },
+        "custom-profile": [0, 2],
+        "*": [-1],
+        "cn/r": "custom-profile",
+        "cn/0": false
+    }
+}
+```
+
+## Threads definition
+Threads can be defined in 3 formats.
+
+#### Array format
+```json
+[
+    [1, 0],
+    [1, 2],
+    [1, -1],
+    [2, -1]
+]
+```
+Each line represent one thread, first element is intensity, this option was known as `low_power_mode`, possible values is range from 1 to 5, second element is CPU affinity, special value `-1` means no affinity.
+
+#### Short array format
+```json
+[-1, -1, -1, -1]
+```
+Each number represent one thread and means CPU affinity, this is default format for algorithm with maximum intensity 1, currently it all RandomX variants and cryptonight-gpu.
+
+#### Short object format
+```json
+{
+    "intensity": 2,
+    "threads": 8,
+    "affinity": -1
+}
+```
+Internal format, but can be user defined.
+
+## Shared options
+
+#### `enabled`
+Enable (`true`) or disable (`false`) CPU backend, by default `true`.
+
+#### `huge-pages`
+Enable (`true`) or disable (`false`) huge pages support, by default `true`.
+
+#### `hw-aes`
+Force enable (`true`) or disable (`false`) hardware AES support. Default value `null` means miner autodetect this feature. Usually don't need change this option, this option useful for some rare cases when miner can't detect hardware AES, but it available. If you force enable this option, but your hardware not support it, miner will crash.
+
+#### `priority`
+Mining threads priority, value from `1` (lowest priority) to `5` (highest possible priority). Default value `null` means miner don't change threads priority at all.
+
+#### `asm`
+Enable/configure or disable ASM optimizations. Possible values: `true`, `false`, `"intel"`, `"ryzen"`, `"bulldozer"`.
+
+#### `argon2-impl` (since v3.1.0)
+Allow override automatically detected Argon2 implementation, this option added mostly for debug purposes, default value `null` means autodetect. Other possible values: `"x86_64"`, `"SSE2"`, `"SSSE3"`, `"XOP"`, `"AVX2"`, `"AVX-512F"`. Manual selection has no safe guards, if you CPU not support required instuctions, miner will crash.
+
+#### `max-threads-hint` (since v4.2.0)
+Maximum CPU threads count (in percentage) hint for autoconfig. [CPU_MAX_USAGE.md](CPU_MAX_USAGE.md)
+
+#### `memory-pool` (since v4.3.0)
+Use continuous, persistent memory block for mining threads, useful for preserve huge pages allocation while algorithm swithing. Possible values `false` (feature disabled, by default) or `true` or specific count of 2 MB huge pages.
+
+#### `yield` (since v5.1.1)
+Prefer system better system response/stability `true` (default value) or maximum hashrate `false`.

doc/CPU_MAX_USAGE.md

@@ -0,0 +1,26 @@
+# Maximum CPU usage
+
+Please read this document carefully, `max-threads-hint` (was known as `max-cpu-usage`) option is most confusing option in the miner with many myth and legends.
+This option is just hint for automatic configuration and can't precise define CPU usage.
+
+### Option definition
+#### Config file:
+```json
+{
+    ...
+    "cpu": {
+        "max-threads-hint": 100,
+        ...
+    },
+    ...
+}
+```
+
+#### Command line
+`--cpu-max-threads-hint 100`
+
+### Known issues and usage
+
+* This option has no effect if miner already generated CPU configuration, to prevent config generation use `"autosave":false,`.
+* Only threads count can be changed, for 1 core CPU this option has no effect, for 2 core CPU only 2 values possible 50% and 100%, for 4 cores: 25%, 50%, 75%, 100%. etc. 
+* You CPU may limited by other factors, eg cache.

doc/PERSISTENT_OPTIONS.md

@@ -0,0 +1,9 @@
+# Persistent options
+
+Options in list below can't changed in runtime by watching config file or via API.
+
+* `background`
+* `donate-level`
+* `cpu/argon2-impl`
+* `opencl/loader`
+* `opencl/platform`

doc/api/1/config.json

@@ -0,0 +1,63 @@
+{
+    "algo": "cryptonight",
+    "api": {
+        "port": 44444,
+        "access-token": "TOKEN",
+        "worker-id": null,
+        "ipv6": false,
+        "restricted": false
+    },
+    "av": 1,
+    "background": false,
+    "colors": true,
+    "cpu-affinity": null,
+    "cpu-priority": null,
+    "donate-level": 5,
+    "huge-pages": true,
+    "hw-aes": null,
+    "log-file": null,
+    "max-cpu-usage": 75,
+    "pools": [
+        {
+            "url": "pool.monero.hashvault.pro:3333",
+            "user": "48edfHu7V9Z84YzzMa6fUueoELZ9ZRXq9VetWzYGzKt52XU5xvqgzYnDK9URnRoJMk1j8nLwEVsaSWJ4fhdUyZijBGUicoD",
+            "pass": "x",
+            "keepalive": false,
+            "nicehash": false,
+            "variant": -1
+        },
+        {
+            "url": "pool.supportxmr.com:3333",
+            "user": "48edfHu7V9Z84YzzMa6fUueoELZ9ZRXq9VetWzYGzKt52XU5xvqgzYnDK9URnRoJMk1j8nLwEVsaSWJ4fhdUyZijBGUicoD",
+            "pass": "x",
+            "keepalive": false,
+            "nicehash": false,
+            "variant": -1
+        }
+    ],
+    "print-time": 60,
+    "retries": 5,
+    "retry-pause": 5,
+    "safe": false,
+    "threads": [
+        {
+            "low_power_mode": 1,
+            "affine_to_cpu": 0
+        },
+        {
+            "low_power_mode": 1,
+            "affine_to_cpu": 1
+        },
+        {
+            "low_power_mode": 1,
+            "affine_to_cpu": 2
+        },
+        {
+            "low_power_mode": 1,
+            "affine_to_cpu": 3
+        }
+    ],
+    "user-agent": null,
+    "syslog": false,
+    "watch": false
+}

doc/api/1/summary.json

@@ -0,0 +1,73 @@
+{
+    "id": "92f3104f9a2ee78c",
+    "worker_id": "Ubuntu-1604-xenial-64-minimal",
+    "version": "2.6.0-beta3",
+    "kind": "cpu",
+    "ua": "XMRig/2.6.0-beta3 (Linux x86_64) libuv/1.8.0 gcc/5.4.0",
+    "cpu": {
+        "brand": "Intel(R) Core(TM) i7-4770 CPU @ 3.40GHz",
+        "aes": true,
+        "x64": true,
+        "sockets": 1
+    },
+    "algo": "cryptonight",
+    "hugepages": true,
+    "donate_level": 5,
+    "hashrate": {
+        "total": [
+            296.24,
+            296.23,
+            295.97
+        ],
+        "highest": 296.5,
+        "threads": [
+            [
+                73.39,
+                73.39,
+                73.28
+            ],
+            [
+                74.72,
+                74.72,
+                74.71
+            ],
+            [
+                74.72,
+                74.72,
+                74.71
+            ],
+            [
+                73.39,
+                73.39,
+                73.27
+            ]
+        ]
+    },
+    "results": {
+        "diff_current": 9990,
+        "shares_good": 30,
+        "shares_total": 30,
+        "avg_time": 31,
+        "hashes_total": 311833,
+        "best": [
+            278199,
+            181923,
+            103717,
+            96632,
+            56154,
+            51580,
+            45667,
+            33159,
+            29581,
+            29514
+        ],
+        "error_log": []
+    },
+    "connection": {
+        "pool": "pool.monero.hashvault.pro:3333",
+        "uptime": 953,
+        "ping": 35,
+        "failures": 0,
+        "error_log": []
+    }
+}

doc/api/1/threads.json

@@ -0,0 +1,65 @@
+{
+    "hugepages": [
+        4,
+        4
+    ],
+    "memory": 8388608,
+    "threads": [
+        {
+            "type": "cpu",
+            "algo": "cryptonight",
+            "av": 1,
+            "low_power_mode": 1,
+            "affine_to_cpu": 0,
+            "priority": -1,
+            "soft_aes": false,
+            "hashrate": [
+                73.39,
+                73.4,
+                73.28
+            ]
+        },
+        {
+            "type": "cpu",
+            "algo": "cryptonight",
+            "av": 1,
+            "low_power_mode": 1,
+            "affine_to_cpu": 1,
+            "priority": -1,
+            "soft_aes": false,
+            "hashrate": [
+                74.72,
+                74.72,
+                74.7
+            ]
+        },
+        {
+            "type": "cpu",
+            "algo": "cryptonight",
+            "av": 1,
+            "low_power_mode": 1,
+            "affine_to_cpu": 2,
+            "priority": -1,
+            "soft_aes": false,
+            "hashrate": [
+                74.71,
+                74.72,
+                74.7
+            ]
+        },
+        {
+            "type": "cpu",
+            "algo": "cryptonight",
+            "av": 1,
+            "low_power_mode": 1,
+            "affine_to_cpu": 3,
+            "priority": -1,
+            "soft_aes": false,
+            "hashrate": [
+                73.39,
+                73.4,
+                73.28
+            ]
+        }
+    ]
+}

doc/build/CMAKE_OPTIONS.md

@@ -0,0 +1,40 @@
+# CMake options
+**Recent version of this document: https://xmrig.com/docs/miner/cmake-options**
+
+## Algorithms
+
+* **`-DWITH_CN_LITE=OFF`** disable all CryptoNight-Lite algorithms (`cn-lite/0`, `cn-lite/1`).
+* **`-DWITH_CN_HEAVY=OFF`** disable all CryptoNight-Heavy algorithms (`cn-heavy/0`, `cn-heavy/xhv`, `cn-heavy/tube`).
+* **`-DWITH_CN_PICO=OFF`** disable CryptoNight-Pico algorithm (`cn-pico`).
+* **`-DWITH_RANDOMX=OFF`** disable RandomX algorithms (`rx/loki`, `rx/wow`).
+* **`-DWITH_ARGON2=OFF`** disable Argon2 algorithms (`argon2/chukwa`, `argon2/wrkz`).
+
+## Features
+
+* **`-DWITH_HWLOC=OFF`**
+disable [hwloc](https://github.com/xmrig/xmrig/issues/1077) support.
+Disabling this feature is not recommended in most cases.
+This feature add external dependency to libhwloc (1.10.0+) (except MSVC builds).
+* **`-DWITH_LIBCPUID=OFF`** disable built in libcpuid support, this feature always disabled if hwloc enabled, if both hwloc and libcpuid disabled auto configuration for CPU will very limited.
+* **`-DWITH_HTTP=OFF`** disable built in HTTP support, this feature used for HTTP API and daemon (solo mining) support.
+* **`-DWITH_TLS=OFF`** disable SSL/TLS support (secure connections to pool). This feature add external dependency to OpenSSL.
+* **`-DWITH_ASM=OFF`** disable assembly optimizations for modern CryptoNight algorithms.
+* **`-DWITH_EMBEDDED_CONFIG=ON`** Enable [embedded](https://github.com/xmrig/xmrig/issues/957) config support.
+* **`-DWITH_OPENCL=OFF`** Disable OpenCL backend.
+* **`-DWITH_CUDA=OFF`** Disable CUDA backend.
+
+## Debug options
+
+* **`-DWITH_DEBUG_LOG=ON`** enable debug log (mostly network requests).
+* **`-DHWLOC_DEBUG=ON`** enable some debug log for hwloc.
+* **`-DCMAKE_BUILD_TYPE=Debug`** enable debug build, only useful for investigate crashes, this option slow down miner.
+
+## Special build options
+
+* **`-DXMRIG_DEPS=<path>`** path to precompiled dependencies https://github.com/xmrig/xmrig-deps
+* **`-DARM_TARGET=<number>`** override ARM target, possible values `7` (ARMv7) and `8` (ARMv8).
+* **`-DUV_INCLUDE_DIR=<path>`** custom path to libuv headers.
+* **`-DUV_LIBRARY=<path>`** custom path to libuv library.
+* **`-DHWLOC_INCLUDE_DIR=<path>`** custom path to hwloc headers.
+* **`-DHWLOC_LIBRARY=<path>`** custom path to hwloc library.
+* **`-DOPENSSL_ROOT_DIR=<path>`** custom path to OpenSSL.

doc/gpg_keys/xmrig.asc

@@ -0,0 +1,30 @@
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+t7ldSBzkuDTlM2V59Iq2hXoSC6dT
+=cIG9
+-----END PGP PUBLIC KEY BLOCK-----

doc/releases/5_0_1/SHA256SUMS

@@ -0,0 +1,5 @@
+6bb1a2e3a0fbca5195be6022f2a9fbff8a353c37c7542e7ab89420cb45b64505  xmrig-5.0.1-gcc-win32.zip
+24dba9ec281acfb2ea2c401ebd0e4e2d1f1ee5fd557da5ff3c7049020c1f78b6  xmrig-5.0.1-gcc-win64.zip
+86d65c6693ec9e35cd7547329580638b85c9eb0cf8383892a1c15199de5b556f  xmrig-5.0.1-msvc-cuda10_1-win64.zip
+0fbfe518b1c4b6993b0f66ff01302626375b15620ccf8f64d6fb97845068ffca  xmrig-5.0.1-msvc-win64.zip
+aa34890738a3494de2fa0e44db346937fea7339852f5f10b5d4655f95e2d8f1f  xmrig-5.0.1-xenial-x64.tar.gz

doc/releases/5_0_1/SHA256SUMS.sig

@@ -0,0 +1,11 @@
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doc/topology/AMD_FX_8320_windows_2_0_4.xml

@@ -0,0 +1,86 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE topology SYSTEM "hwloc2.dtd">
+<topology version="2.0">
+  <object type="Machine" os_index="0" cpuset="0x000000ff" complete_cpuset="0x000000ff" allowed_cpuset="0x000000ff" nodeset="0x00000001" complete_nodeset="0x00000001" allowed_nodeset="0x00000001" gp_index="1">
+    <info name="Backend" value="Windows"/>
+    <info name="hwlocVersion" value="2.0.4"/>
+    <info name="ProcessName" value="lstopo.exe"/>
+    <object type="Package" cpuset="0x000000ff" complete_cpuset="0x000000ff" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="2">
+      <info name="CPUVendor" value="AuthenticAMD"/>
+      <info name="CPUFamilyNumber" value="21"/>
+      <info name="CPUModelNumber" value="2"/>
+      <info name="CPUModel" value="AMD FX(tm)-8320 Eight-Core Processor           "/>
+      <info name="CPUStepping" value="0"/>
+      <object type="NUMANode" os_index="0" cpuset="0x000000ff" complete_cpuset="0x000000ff" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="24" local_memory="7033581568">
+        <page_type size="4096" count="0"/>
+      </object>
+      <object type="L3Cache" cpuset="0x000000ff" complete_cpuset="0x000000ff" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="7" cache_size="8388608" depth="3" cache_linesize="64" cache_associativity="64" cache_type="0">
+        <info name="Inclusive" value="0"/>
+        <object type="L2Cache" cpuset="0x00000003" complete_cpuset="0x00000003" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="6" cache_size="2097152" depth="2" cache_linesize="64" cache_associativity="16" cache_type="0">
+          <info name="Inclusive" value="0"/>
+          <object type="L1iCache" cpuset="0x00000003" complete_cpuset="0x00000003" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="5" cache_size="65536" depth="1" cache_linesize="64" cache_associativity="2" cache_type="2">
+            <info name="Inclusive" value="0"/>
+            <object type="Core" cpuset="0x00000003" complete_cpuset="0x00000003" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="3">
+              <object type="L1Cache" cpuset="0x00000001" complete_cpuset="0x00000001" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="4" cache_size="16384" depth="1" cache_linesize="64" cache_associativity="4" cache_type="1">
+                <info name="Inclusive" value="0"/>
+                <object type="PU" os_index="0" cpuset="0x00000001" complete_cpuset="0x00000001" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="26"/>
+              </object>
+              <object type="L1Cache" cpuset="0x00000002" complete_cpuset="0x00000002" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="8" cache_size="16384" depth="1" cache_linesize="64" cache_associativity="4" cache_type="1">
+                <info name="Inclusive" value="0"/>
+                <object type="PU" os_index="1" cpuset="0x00000002" complete_cpuset="0x00000002" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="27"/>
+              </object>
+            </object>
+          </object>
+        </object>
+        <object type="L2Cache" cpuset="0x0000000c" complete_cpuset="0x0000000c" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="12" cache_size="2097152" depth="2" cache_linesize="64" cache_associativity="16" cache_type="0">
+          <info name="Inclusive" value="0"/>
+          <object type="L1iCache" cpuset="0x0000000c" complete_cpuset="0x0000000c" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="11" cache_size="65536" depth="1" cache_linesize="64" cache_associativity="2" cache_type="2">
+            <info name="Inclusive" value="0"/>
+            <object type="Core" cpuset="0x0000000c" complete_cpuset="0x0000000c" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="9">
+              <object type="L1Cache" cpuset="0x00000004" complete_cpuset="0x00000004" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="10" cache_size="16384" depth="1" cache_linesize="64" cache_associativity="4" cache_type="1">
+                <info name="Inclusive" value="0"/>
+                <object type="PU" os_index="2" cpuset="0x00000004" complete_cpuset="0x00000004" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="28"/>
+              </object>
+              <object type="L1Cache" cpuset="0x00000008" complete_cpuset="0x00000008" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="13" cache_size="16384" depth="1" cache_linesize="64" cache_associativity="4" cache_type="1">
+                <info name="Inclusive" value="0"/>
+                <object type="PU" os_index="3" cpuset="0x00000008" complete_cpuset="0x00000008" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="29"/>
+              </object>
+            </object>
+          </object>
+        </object>
+        <object type="L2Cache" cpuset="0x00000030" complete_cpuset="0x00000030" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="17" cache_size="2097152" depth="2" cache_linesize="64" cache_associativity="16" cache_type="0">
+          <info name="Inclusive" value="0"/>
+          <object type="L1iCache" cpuset="0x00000030" complete_cpuset="0x00000030" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="16" cache_size="65536" depth="1" cache_linesize="64" cache_associativity="2" cache_type="2">
+            <info name="Inclusive" value="0"/>
+            <object type="Core" cpuset="0x00000030" complete_cpuset="0x00000030" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="14">
+              <object type="L1Cache" cpuset="0x00000010" complete_cpuset="0x00000010" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="15" cache_size="16384" depth="1" cache_linesize="64" cache_associativity="4" cache_type="1">
+                <info name="Inclusive" value="0"/>
+                <object type="PU" os_index="4" cpuset="0x00000010" complete_cpuset="0x00000010" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="30"/>
+              </object>
+              <object type="L1Cache" cpuset="0x00000020" complete_cpuset="0x00000020" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="18" cache_size="16384" depth="1" cache_linesize="64" cache_associativity="4" cache_type="1">
+                <info name="Inclusive" value="0"/>
+                <object type="PU" os_index="5" cpuset="0x00000020" complete_cpuset="0x00000020" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="31"/>
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+  </object>
+</topology>

doc/topology/AMD_Opteron_6272_x4_N8_linux_2_0_4_LXC.xml

@@ -0,0 +1,234 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE topology SYSTEM "hwloc2.dtd">
+<topology version="2.0">
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+    <info name="DMIProductName" value="H8QG6"/>
+    <info name="DMIProductVersion" value="1234567890"/>
+    <info name="DMIProductSerial" value="1234567890"/>
+    <info name="DMIProductUUID" value="47513848-0036-2500-9058-002590582E10"/>
+    <info name="DMIBoardVendor" value="Supermicro"/>
+    <info name="DMIBoardName" value="H8QG6"/>
+    <info name="DMIBoardVersion" value="1234567890"/>
+    <info name="DMIBoardSerial" value="WM1AS70308"/>
+    <info name="DMIBoardAssetTag" value="1234567890"/>
+    <info name="DMIChassisVendor" value="Supermicro"/>
+    <info name="DMIChassisType" value="17"/>
+    <info name="DMIChassisVersion" value="1234567890"/>
+    <info name="DMIChassisSerial" value="1234567890."/>
+    <info name="DMIChassisAssetTag" value="1234567890"/>
+    <info name="DMIBIOSVendor" value="American Megatrends Inc."/>
+    <info name="DMIBIOSVersion" value="3.5       "/>
+    <info name="DMIBIOSDate" value="12/16/2013"/>
+    <info name="DMISysVendor" value="Supermicro"/>
+    <info name="Backend" value="Linux"/>
+    <info name="LinuxCgroup" value="/"/>
+    <info name="OSName" value="Linux"/>
+    <info name="OSRelease" value="4.15.18-17-pve"/>
+    <info name="OSVersion" value="#1 SMP PVE 4.15.18-43 (Tue, 25 Jun 2019 17:59:49 +0200)"/>
+    <info name="HostName" value="host"/>
+    <info name="Architecture" value="x86_64"/>
+    <info name="hwlocVersion" value="2.0.4"/>
+    <info name="ProcessName" value="xmrig"/>
+    <object type="Package" os_index="0" cpuset="0x0000ffff" complete_cpuset="0x0000ffff" nodeset="0x00000003" complete_nodeset="0x00000003" gp_index="2">
+      <info name="CPUVendor" value="AuthenticAMD"/>
+      <info name="CPUFamilyNumber" value="21"/>
+      <info name="CPUModelNumber" value="1"/>
+      <info name="CPUModel" value="AMD Opteron(TM) Processor 6272                 "/>
+      <info name="CPUStepping" value="2"/>
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doc/topology/AMD_Opteron_6278_x2_UMA_windows_2_0_4.xml

@@ -0,0 +1,294 @@
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+</topology>

doc/topology/AMD_Opteron_6344_x2_N4_win7_2_0_4_bug.xml

@@ -0,0 +1,262 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE topology SYSTEM "hwloc2.dtd">
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+</topology>

doc/topology/AMD_Opteron_6348_x4_N8_linux_1_11_2.xml

@@ -0,0 +1,550 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE topology SYSTEM "hwloc.dtd">
+<topology>
+  <object type="Machine" os_index="0" cpuset="0x0000ffff,0xffffffff" complete_cpuset="0x0000ffff,0xffffffff" online_cpuset="0x0000ffff,0xffffffff" allowed_cpuset="0x0000ffff,0xffffffff" nodeset="0x000000ff" complete_nodeset="0x000000ff" allowed_nodeset="0x000000ff">
+    <page_type size="4096" count="0"/>
+    <page_type size="2097152" count="0"/>
+    <page_type size="1073741824" count="0"/>
+    <info name="DMIProductName" value="PowerEdge R815"/>
+    <info name="DMIProductVersion" value=""/>
+    <info name="DMIBoardVendor" value="Dell Inc."/>
+    <info name="DMIBoardName" value="0W13NR"/>
+    <info name="DMIBoardVersion" value="A00"/>
+    <info name="DMIBoardAssetTag" value=""/>
+    <info name="DMIChassisVendor" value="Dell Inc."/>
+    <info name="DMIChassisType" value="23"/>
+    <info name="DMIChassisVersion" value=""/>
+    <info name="DMIChassisAssetTag" value="2452806   "/>
+    <info name="DMIBIOSVendor" value="Dell Inc."/>
+    <info name="DMIBIOSVersion" value="3.2.2"/>
+    <info name="DMIBIOSDate" value="09/15/2014"/>
+    <info name="DMISysVendor" value="Dell Inc."/>
+    <info name="Backend" value="Linux"/>
+    <info name="LinuxCgroup" value="/"/>
+    <info name="OSName" value="Linux"/>
+    <info name="OSRelease" value="4.15.0-55-generic"/>
+    <info name="OSVersion" value="#60~16.04.2-Ubuntu SMP Thu Jul 4 09:03:09 UTC 2019"/>
+    <info name="HostName" value="host"/>
+    <info name="Architecture" value="x86_64"/>
+    <info name="hwlocVersion" value="1.11.2"/>
+    <info name="ProcessName" value="xmrig"/>
+    <distances nbobjs="8" relative_depth="2" latency_base="10.000000">
+      <latency value="1.000000"/>
+      <latency value="1.600000"/>
+      <latency value="1.600000"/>
+      <latency value="2.200000"/>
+      <latency value="1.600000"/>
+      <latency value="2.200000"/>
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+      <latency value="2.200000"/>
+      <latency value="1.600000"/>
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+      <latency value="2.200000"/>
+      <latency value="1.600000"/>
+      <latency value="2.200000"/>
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+      <latency value="1.600000"/>
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+      <latency value="1.600000"/>
+      <latency value="2.200000"/>
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+      <latency value="2.200000"/>
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+      <info name="CPUVendor" value="AuthenticAMD"/>
+      <info name="CPUFamilyNumber" value="21"/>
+      <info name="CPUModelNumber" value="2"/>
+      <info name="CPUModel" value="AMD Opteron(tm) Processor 6348"/>
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+      </object>
+    </object>
+  </object>
+</topology>

doc/topology/AMD_Opteron_6348_x4_N8_linux_2_0_4.xml

@@ -0,0 +1,399 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE topology SYSTEM "hwloc2.dtd">
+<topology version="2.0">
+  <object type="Machine" os_index="0" cpuset="0xffffffff" complete_cpuset="0xffffffff" allowed_cpuset="0xffffffff" nodeset="0x00000066" complete_nodeset="0x000000ff" allowed_nodeset="0x00000066" gp_index="1">
+    <info name="DMIProductName" value="H8QG6"/>
+    <info name="DMIProductVersion" value="1234567890"/>
+    <info name="DMIProductSerial" value="1234567890"/>
+    <info name="DMIProductUUID" value="0"/>
+    <info name="DMIBoardVendor" value="Supermicro"/>
+    <info name="DMIBoardName" value="H8QG6"/>
+    <info name="DMIBoardVersion" value="1234567890"/>
+    <info name="DMIBoardSerial" value="0"/>
+    <info name="DMIBoardAssetTag" value="1234567890"/>
+    <info name="DMIChassisVendor" value="Supermicro"/>
+    <info name="DMIChassisType" value="3"/>
+    <info name="DMIChassisVersion" value="1234567890"/>
+    <info name="DMIChassisSerial" value="1234567890."/>
+    <info name="DMIChassisAssetTag" value="1234567890"/>
+    <info name="DMIBIOSVendor" value="American Megatrends Inc."/>
+    <info name="DMIBIOSVersion" value="080016 "/>
+    <info name="DMIBIOSDate" value="10/11/2010"/>
+    <info name="DMISysVendor" value="Supermicro"/>
+    <info name="Backend" value="Linux"/>
+    <info name="LinuxCgroup" value="/"/>
+    <info name="OSName" value="Linux"/>
+    <info name="OSRelease" value="4.15.0-20-generic"/>
+    <info name="OSVersion" value="#21-Ubuntu SMP Tue Apr 24 06:16:15 UTC 2018"/>
+    <info name="HostName" value="host"/>
+    <info name="Architecture" value="x86_64"/>
+    <info name="hwlocVersion" value="2.0.4"/>
+    <info name="ProcessName" value="xmrig"/>
+    <object type="Package" os_index="0" cpuset="0x000000ff" complete_cpuset="0x000000ff" nodeset="0x00000002" complete_nodeset="0x00000003" gp_index="2">
+      <info name="CPUVendor" value="AuthenticAMD"/>
+      <info name="CPUFamilyNumber" value="16"/>
+      <info name="CPUModelNumber" value="9"/>
+      <info name="CPUModel" value="AMD Opteron(tm) Processor 6128"/>
+      <info name="CPUStepping" value="1"/>
+      <object type="L3Cache" cpuset="0x0000000f" complete_cpuset="0x0000000f" nodeset="0x0" complete_nodeset="0x00000001" gp_index="7" cache_size="5240832" depth="3" cache_linesize="64" cache_associativity="48" cache_type="0">
+        <info name="Inclusive" value="0"/>
+        <object type="L2Cache" cpuset="0x00000001" complete_cpuset="0x00000001" nodeset="0x0" complete_nodeset="0x00000001" gp_index="6" cache_size="524288" depth="2" cache_linesize="64" cache_associativity="16" cache_type="0">
+          <info name="Inclusive" value="0"/>
+          <object type="L1Cache" cpuset="0x00000001" complete_cpuset="0x00000001" nodeset="0x0" complete_nodeset="0x00000001" gp_index="5" cache_size="65536" depth="1" cache_linesize="64" cache_associativity="2" cache_type="1">
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+            <object type="Core" os_index="0" cpuset="0x00000001" complete_cpuset="0x00000001" nodeset="0x0" complete_nodeset="0x00000001" gp_index="3">
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+        <object type="L2Cache" cpuset="0x00000002" complete_cpuset="0x00000002" nodeset="0x0" complete_nodeset="0x00000001" gp_index="11" cache_size="524288" depth="2" cache_linesize="64" cache_associativity="16" cache_type="0">
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+            <object type="Core" os_index="1" cpuset="0x00000002" complete_cpuset="0x00000002" nodeset="0x0" complete_nodeset="0x00000001" gp_index="8">
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+        <object type="L2Cache" cpuset="0x00000004" complete_cpuset="0x00000004" nodeset="0x0" complete_nodeset="0x00000001" gp_index="15" cache_size="524288" depth="2" cache_linesize="64" cache_associativity="16" cache_type="0">
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+      </object>
+    </object>
+  </object>
+  <distances2 type="NUMANode" nbobjs="4" kind="5" indexing="os">
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+    <u64values length="18">10 22 22 16 22 10 </u64values>
+  </distances2>
+</topology>
+

doc/topology/AMD_Opteron_6380_x4_N8_linux_1_11_5.xml

@@ -0,0 +1,670 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE topology SYSTEM "hwloc.dtd">
+<topology>
+  <object type="Machine" os_index="0" cpuset="0xffffffff,0xffffffff" complete_cpuset="0xffffffff,0xffffffff" online_cpuset="0xffffffff,0xffffffff" allowed_cpuset="0xffffffff,0xffffffff" nodeset="0x00000055" complete_nodeset="0x000000ff" allowed_nodeset="0x00000055">
+    <page_type size="4096" count="0"/>
+    <page_type size="2097152" count="0"/>
+    <page_type size="1073741824" count="0"/>
+    <info name="DMIProductName" value="PowerEdge C6145 "/>
+    <info name="DMIProductVersion" value="        "/>
+    <info name="DMIProductSerial" value="BYSBHS1               "/>
+    <info name="DMIProductUUID" value="4C4C4544-0059-5310-8042-C2C04F485331"/>
+    <info name="DMIBoardVendor" value="Dell Inc.                       "/>
+    <info name="DMIBoardName" value="0VKT0M"/>
+    <info name="DMIBoardVersion" value="A00                   "/>
+    <info name="DMIBoardSerial" value=".BYSBHS1.CN747511CV0156."/>
+    <info name="DMIBoardAssetTag" value=".2                       "/>
+    <info name="DMIChassisVendor" value="Dell Inc.                       "/>
+    <info name="DMIChassisType" value="23"/>
+    <info name="DMIChassisVersion" value="   "/>
+    <info name="DMIChassisSerial" value="BYSBHS1               "/>
+    <info name="DMIChassisAssetTag" value="        "/>
+    <info name="DMIBIOSVendor" value="Dell Inc."/>
+    <info name="DMIBIOSVersion" value="3.5.0"/>
+    <info name="DMIBIOSDate" value="10/28/2014"/>
+    <info name="DMISysVendor" value="Dell Inc.                       "/>
+    <info name="Backend" value="Linux"/>
+    <info name="LinuxCgroup" value="/"/>
+    <info name="OSName" value="Linux"/>
+    <info name="OSRelease" value="4.9.0-6-amd64"/>
+    <info name="OSVersion" value="#1 SMP Debian 4.9.82-1+deb9u3 (2018-03-02)"/>
+    <info name="HostName" value="host"/>
+    <info name="Architecture" value="x86_64"/>
+    <info name="hwlocVersion" value="1.11.5"/>
+    <info name="ProcessName" value="x"/>
+    <distances nbobjs="8" relative_depth="2" latency_base="10.000000">
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+      <latency value="1.600000"/>
+      <latency value="1.600000"/>
+      <latency value="2.200000"/>
+      <latency value="1.600000"/>
+      <latency value="2.200000"/>
+      <latency value="1.600000"/>
+      <latency value="2.200000"/>
+      <latency value="1.600000"/>
+      <latency value="1.000000"/>
+      <latency value="2.200000"/>
+      <latency value="1.600000"/>
+      <latency value="1.600000"/>
+      <latency value="2.200000"/>
+      <latency value="2.200000"/>
+      <latency value="1.600000"/>
+      <latency value="1.600000"/>
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+      <latency value="1.600000"/>
+      <latency value="1.600000"/>
+      <latency value="1.600000"/>
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+      <latency value="1.600000"/>
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+      <latency value="1.600000"/>
+      <latency value="1.600000"/>
+      <latency value="2.200000"/>
+      <latency value="2.200000"/>
+      <latency value="1.600000"/>
+      <latency value="1.600000"/>
+      <latency value="1.600000"/>
+      <latency value="1.600000"/>
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+      <latency value="1.600000"/>
+      <latency value="1.600000"/>
+      <latency value="2.200000"/>
+      <latency value="2.200000"/>
+      <latency value="2.200000"/>
+      <latency value="1.600000"/>
+      <latency value="1.600000"/>
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+      <latency value="1.600000"/>
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+      <latency value="2.200000"/>
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+      <latency value="1.600000"/>
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+      <latency value="2.200000"/>
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+      <latency value="1.000000"/>
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+      <info name="CPUVendor" value="AuthenticAMD"/>
+      <info name="CPUFamilyNumber" value="21"/>
+      <info name="CPUModelNumber" value="2"/>
+      <info name="CPUModel" value="AMD Opteron(tm) Processor 6380"/>
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+            <object type="Cache" cpuset="0x80000000,0x0" complete_cpuset="0x80000000,0x0" online_cpuset="0x80000000,0x0" allowed_cpuset="0x80000000,0x0" nodeset="0x0" complete_nodeset="0x00000080" allowed_nodeset="0x0" cache_size="16384" depth="1" cache_linesize="64" cache_associativity="4" cache_type="1">
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+              <object type="Core" os_index="7" cpuset="0x80000000,0x0" complete_cpuset="0x80000000,0x0" online_cpuset="0x80000000,0x0" allowed_cpuset="0x80000000,0x0" nodeset="0x0" complete_nodeset="0x00000080" allowed_nodeset="0x0">
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+</topology>

doc/topology/AMD_Ryzen_7_2700X_windows_2_0_4.xml

@@ -0,0 +1,105 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE topology SYSTEM "hwloc2.dtd">
+<topology version="2.0">
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+    <info name="Backend" value="Windows"/>
+    <info name="hwlocVersion" value="2.0.4"/>
+    <info name="ProcessName" value="xmrig.exe"/>
+    <object type="Package" cpuset="0x0000ffff" complete_cpuset="0x0000ffff" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="2">
+      <info name="CPUVendor" value="AuthenticAMD"/>
+      <info name="CPUFamilyNumber" value="23"/>
+      <info name="CPUModelNumber" value="8"/>
+      <info name="CPUModel" value="AMD Ryzen 7 2700X Eight-Core Processor         "/>
+      <info name="CPUStepping" value="2"/>
+      <object type="NUMANode" os_index="0" cpuset="0x0000ffff" complete_cpuset="0x0000ffff" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="29" local_memory="25515728896">
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+      <object type="L3Cache" cpuset="0x000000ff" complete_cpuset="0x000000ff" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="6" cache_size="8388608" depth="3" cache_linesize="64" cache_associativity="16" cache_type="0">
+        <info name="Inclusive" value="0"/>
+        <object type="L2Cache" cpuset="0x00000003" complete_cpuset="0x00000003" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="5" cache_size="524288" depth="2" cache_linesize="64" cache_associativity="8" cache_type="0">
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+          <object type="L1Cache" cpuset="0x00000003" complete_cpuset="0x00000003" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="4" cache_size="32768" depth="1" cache_linesize="64" cache_associativity="8" cache_type="1">
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+            <object type="Core" cpuset="0x00000003" complete_cpuset="0x00000003" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="3">
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+        <object type="L2Cache" cpuset="0x0000000c" complete_cpuset="0x0000000c" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="9" cache_size="524288" depth="2" cache_linesize="64" cache_associativity="8" cache_type="0">
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+        <object type="L2Cache" cpuset="0x00000030" complete_cpuset="0x00000030" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="12" cache_size="524288" depth="2" cache_linesize="64" cache_associativity="8" cache_type="0">
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+          <object type="L1Cache" cpuset="0x00000030" complete_cpuset="0x00000030" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="11" cache_size="32768" depth="1" cache_linesize="64" cache_associativity="8" cache_type="1">
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+            <object type="Core" cpuset="0x00000030" complete_cpuset="0x00000030" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="10">
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+        <object type="L2Cache" cpuset="0x000000c0" complete_cpuset="0x000000c0" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="15" cache_size="524288" depth="2" cache_linesize="64" cache_associativity="8" cache_type="0">
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+          <object type="L1Cache" cpuset="0x000000c0" complete_cpuset="0x000000c0" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="14" cache_size="32768" depth="1" cache_linesize="64" cache_associativity="8" cache_type="1">
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+            <object type="Core" cpuset="0x000000c0" complete_cpuset="0x000000c0" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="13">
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+        <object type="L2Cache" cpuset="0x00000300" complete_cpuset="0x00000300" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="18" cache_size="524288" depth="2" cache_linesize="64" cache_associativity="8" cache_type="0">
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+            <object type="Core" cpuset="0x00000c00" complete_cpuset="0x00000c00" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="20">
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+        <object type="L2Cache" cpuset="0x00003000" complete_cpuset="0x00003000" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="25" cache_size="524288" depth="2" cache_linesize="64" cache_associativity="8" cache_type="0">
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+          <object type="L1Cache" cpuset="0x00003000" complete_cpuset="0x00003000" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="24" cache_size="32768" depth="1" cache_linesize="64" cache_associativity="8" cache_type="1">
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+            <object type="Core" cpuset="0x00003000" complete_cpuset="0x00003000" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="23">
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+        <object type="L2Cache" cpuset="0x0000c000" complete_cpuset="0x0000c000" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="28" cache_size="524288" depth="2" cache_linesize="64" cache_associativity="8" cache_type="0">
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+          <object type="L1Cache" cpuset="0x0000c000" complete_cpuset="0x0000c000" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="27" cache_size="32768" depth="1" cache_linesize="64" cache_associativity="8" cache_type="1">
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+            <object type="Core" cpuset="0x0000c000" complete_cpuset="0x0000c000" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="26">
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+        </object>
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+  </object>
+</topology>

doc/topology/AMD_Ryzen_7_3700X_windows_2_0_4.xml

@@ -0,0 +1,104 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE topology SYSTEM "hwloc2.dtd">
+<topology version="2.0">
+  <object type="Machine" os_index="0" cpuset="0x0000ffff" complete_cpuset="0x0000ffff" allowed_cpuset="0x0000ffff" nodeset="0x00000001" complete_nodeset="0x00000001" allowed_nodeset="0x00000001" gp_index="1">
+    <info name="Backend" value="Windows"/>
+    <info name="hwlocVersion" value="2.0.4"/>
+    <object type="Package" cpuset="0x0000ffff" complete_cpuset="0x0000ffff" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="2">
+      <info name="CPUVendor" value="AuthenticAMD"/>
+      <info name="CPUFamilyNumber" value="23"/>
+      <info name="CPUModelNumber" value="113"/>
+      <info name="CPUModel" value="AMD Ryzen 7 3700X 8-Core Processor             "/>
+      <info name="CPUStepping" value="0"/>
+      <object type="NUMANode" os_index="0" cpuset="0x0000ffff" complete_cpuset="0x0000ffff" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="29" local_memory="15508537344">
+        <page_type size="4096" count="0"/>
+      </object>
+      <object type="L3Cache" cpuset="0x000000ff" complete_cpuset="0x000000ff" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="6" cache_size="16777216" depth="3" cache_linesize="64" cache_associativity="16" cache_type="0">
+        <info name="Inclusive" value="0"/>
+        <object type="L2Cache" cpuset="0x00000003" complete_cpuset="0x00000003" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="5" cache_size="524288" depth="2" cache_linesize="64" cache_associativity="8" cache_type="0">
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+          <object type="L1Cache" cpuset="0x00000003" complete_cpuset="0x00000003" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="4" cache_size="32768" depth="1" cache_linesize="64" cache_associativity="8" cache_type="1">
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+            <object type="Core" cpuset="0x00000003" complete_cpuset="0x00000003" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="3">
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doc/topology/AMD_Ryzen_Threadripper_2950X_N2_linux_2_0_4.xml

@@ -0,0 +1,226 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE topology SYSTEM "hwloc2.dtd">
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doc/topology/AMD_Ryzen_Threadripper_2950X_UMA_linux_1_11_9.xml

@@ -0,0 +1,328 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE topology SYSTEM "hwloc.dtd">
+<topology>
+  <object type="Machine" os_index="0" cpuset="0xffffffff" complete_cpuset="0xffffffff" online_cpuset="0xffffffff" allowed_cpuset="0xffffffff" local_memory="135131918336">
+    <page_type size="4096" count="32991191"/>
+    <page_type size="2097152" count="0"/>
+    <page_type size="1073741824" count="0"/>
+    <info name="DMIProductName" value="MS-7B09"/>
+    <info name="DMIProductVersion" value="2.0"/>
+    <info name="DMIProductSerial" value="To be filled by O.E.M."/>
+    <info name="DMIProductUUID" value="00000000-0000-0000-0000-00D8610EB83E"/>
+    <info name="DMIBoardVendor" value="Micro-Star International Co., Ltd."/>
+    <info name="DMIBoardName" value="X399 HZ"/>
+    <info name="DMIBoardVersion" value="2.0"/>
+    <info name="DMIBoardSerial" value="I916583383"/>
+    <info name="DMIBoardAssetTag" value="To be filled by O.E.M."/>
+    <info name="DMIChassisVendor" value="Micro-Star International Co., Ltd."/>
+    <info name="DMIChassisType" value="3"/>
+    <info name="DMIChassisVersion" value="2.0"/>
+    <info name="DMIChassisSerial" value="To be filled by O.E.M."/>
+    <info name="DMIChassisAssetTag" value="To be filled by O.E.M."/>
+    <info name="DMIBIOSVendor" value="American Megatrends Inc."/>
+    <info name="DMIBIOSVersion" value="A.E4"/>
+    <info name="DMIBIOSDate" value="01/21/2019"/>
+    <info name="DMISysVendor" value="Micro-Star International Co., Ltd."/>
+    <info name="Backend" value="Linux"/>
+    <info name="LinuxCgroup" value="/"/>
+    <info name="OSName" value="Linux"/>
+    <info name="OSRelease" value="4.15.0-52-generic"/>
+    <info name="OSVersion" value="#56-Ubuntu SMP Tue Jun 4 22:49:08 UTC 2019"/>
+    <info name="HostName" value="host"/>
+    <info name="Architecture" value="x86_64"/>
+    <info name="hwlocVersion" value="1.11.9"/>
+    <info name="ProcessName" value="lstopo"/>
+    <object type="Package" os_index="0" cpuset="0xffffffff" complete_cpuset="0xffffffff" online_cpuset="0xffffffff" allowed_cpuset="0xffffffff">
+      <info name="CPUVendor" value="AuthenticAMD"/>
+      <info name="CPUFamilyNumber" value="23"/>
+      <info name="CPUModelNumber" value="8"/>
+      <info name="CPUModel" value="AMD Ryzen Threadripper 2950X 16-Core Processor"/>
+      <info name="CPUStepping" value="2"/>
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+        <object type="Cache" cpuset="0x00010001" complete_cpuset="0x00010001" online_cpuset="0x00010001" allowed_cpuset="0x00010001" cache_size="524288" depth="2" cache_linesize="64" cache_associativity="8" cache_type="0">
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+            <object type="Cache" cpuset="0x20002000" complete_cpuset="0x20002000" online_cpuset="0x20002000" allowed_cpuset="0x20002000" cache_size="65536" depth="1" cache_linesize="64" cache_associativity="4" cache_type="2">
+              <info name="Inclusive" value="0"/>
+              <object type="Core" os_index="5" cpuset="0x20002000" complete_cpuset="0x20002000" online_cpuset="0x20002000" allowed_cpuset="0x20002000">
+                <object type="PU" os_index="13" cpuset="0x00002000" complete_cpuset="0x00002000" online_cpuset="0x00002000" allowed_cpuset="0x00002000"/>
+                <object type="PU" os_index="29" cpuset="0x20000000" complete_cpuset="0x20000000" online_cpuset="0x20000000" allowed_cpuset="0x20000000"/>
+              </object>
+            </object>
+          </object>
+        </object>
+        <object type="Cache" cpuset="0x40004000" complete_cpuset="0x40004000" online_cpuset="0x40004000" allowed_cpuset="0x40004000" cache_size="524288" depth="2" cache_linesize="64" cache_associativity="8" cache_type="0">
+          <info name="Inclusive" value="1"/>
+          <object type="Cache" cpuset="0x40004000" complete_cpuset="0x40004000" online_cpuset="0x40004000" allowed_cpuset="0x40004000" cache_size="32768" depth="1" cache_linesize="64" cache_associativity="8" cache_type="1">
+            <info name="Inclusive" value="0"/>
+            <object type="Cache" cpuset="0x40004000" complete_cpuset="0x40004000" online_cpuset="0x40004000" allowed_cpuset="0x40004000" cache_size="65536" depth="1" cache_linesize="64" cache_associativity="4" cache_type="2">
+              <info name="Inclusive" value="0"/>
+              <object type="Core" os_index="6" cpuset="0x40004000" complete_cpuset="0x40004000" online_cpuset="0x40004000" allowed_cpuset="0x40004000">
+                <object type="PU" os_index="14" cpuset="0x00004000" complete_cpuset="0x00004000" online_cpuset="0x00004000" allowed_cpuset="0x00004000"/>
+                <object type="PU" os_index="30" cpuset="0x40000000" complete_cpuset="0x40000000" online_cpuset="0x40000000" allowed_cpuset="0x40000000"/>
+              </object>
+            </object>
+          </object>
+        </object>
+        <object type="Cache" cpuset="0x80008000" complete_cpuset="0x80008000" online_cpuset="0x80008000" allowed_cpuset="0x80008000" cache_size="524288" depth="2" cache_linesize="64" cache_associativity="8" cache_type="0">
+          <info name="Inclusive" value="1"/>
+          <object type="Cache" cpuset="0x80008000" complete_cpuset="0x80008000" online_cpuset="0x80008000" allowed_cpuset="0x80008000" cache_size="32768" depth="1" cache_linesize="64" cache_associativity="8" cache_type="1">
+            <info name="Inclusive" value="0"/>
+            <object type="Cache" cpuset="0x80008000" complete_cpuset="0x80008000" online_cpuset="0x80008000" allowed_cpuset="0x80008000" cache_size="65536" depth="1" cache_linesize="64" cache_associativity="4" cache_type="2">
+              <info name="Inclusive" value="0"/>
+              <object type="Core" os_index="7" cpuset="0x80008000" complete_cpuset="0x80008000" online_cpuset="0x80008000" allowed_cpuset="0x80008000">
+                <object type="PU" os_index="15" cpuset="0x00008000" complete_cpuset="0x00008000" online_cpuset="0x00008000" allowed_cpuset="0x00008000"/>
+                <object type="PU" os_index="31" cpuset="0x80000000" complete_cpuset="0x80000000" online_cpuset="0x80000000" allowed_cpuset="0x80000000"/>
+              </object>
+            </object>
+          </object>
+        </object>
+      </object>
+    </object>
+    <object type="Bridge" os_index="0" bridge_type="0-1" depth="0" bridge_pci="0000:[00-0b]">
+      <object type="Bridge" os_index="17" name="Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) PCIe GPP Bridge" bridge_type="1-1" depth="1" bridge_pci="0000:[01-09]" pci_busid="0000:00:01.1" pci_type="0604 [1022:1453] [0000:0000] 00" pci_link_speed="3.938462">
+        <info name="PCIVendor" value="Advanced Micro Devices, Inc. [AMD]"/>
+        <info name="PCIDevice" value="Family 17h (Models 00h-0fh) PCIe GPP Bridge"/>
+        <object type="PCIDev" os_index="4097" name="Advanced Micro Devices, Inc. [AMD] X399 Series Chipset SATA Controller" pci_busid="0000:01:00.1" pci_type="0106 [1022:43b6] [1b21:1062] 02" pci_link_speed="3.938462">
+          <info name="PCIVendor" value="Advanced Micro Devices, Inc. [AMD]"/>
+          <info name="PCIDevice" value="X399 Series Chipset SATA Controller"/>
+          <object type="OSDev" name="sda" osdev_type="0">
+            <info name="LinuxDeviceID" value="8:0"/>
+            <info name="Model" value="INTEL_SSDSC2KB480G8"/>
+            <info name="Revision" value="XCV10110"/>
+            <info name="SerialNumber" value="PHYF8513029B480BGN"/>
+            <info name="Type" value="Disk"/>
+          </object>
+          <object type="OSDev" name="sdb" osdev_type="0">
+            <info name="LinuxDeviceID" value="8:16"/>
+            <info name="Model" value="INTEL_SSDSC2KB480G8"/>
+            <info name="Revision" value="XCV10110"/>
+            <info name="SerialNumber" value="PHYF8513033G480BGN"/>
+            <info name="Type" value="Disk"/>
+          </object>
+        </object>
+        <object type="Bridge" os_index="4098" name="Advanced Micro Devices, Inc. [AMD] X399 Series Chipset PCIe Bridge" bridge_type="1-1" depth="2" bridge_pci="0000:[02-09]" pci_busid="0000:01:00.2" pci_type="0604 [1022:43b1] [0000:0000] 02" pci_link_speed="3.938462">
+          <info name="PCIVendor" value="Advanced Micro Devices, Inc. [AMD]"/>
+          <info name="PCIDevice" value="X399 Series Chipset PCIe Bridge"/>
+          <object type="Bridge" os_index="8224" name="Advanced Micro Devices, Inc. [AMD] 300 Series Chipset PCIe Port" bridge_type="1-1" depth="3" bridge_pci="0000:[04-04]" pci_busid="0000:02:02.0" pci_type="0604 [1022:43b4] [0000:0000] 02" pci_link_speed="0.250000">
+            <info name="PCIVendor" value="Advanced Micro Devices, Inc. [AMD]"/>
+            <info name="PCIDevice" value="300 Series Chipset PCIe Port"/>
+            <object type="PCIDev" os_index="16384" name="Silicon Motion, Inc. SM750" pci_busid="0000:04:00.0" pci_type="0300 [126f:0750] [126f:0750] a1" pci_link_speed="0.250000">
+              <info name="PCIVendor" value="Silicon Motion, Inc."/>
+              <info name="PCIDevice" value="SM750"/>
+            </object>
+          </object>
+          <object type="Bridge" os_index="8288" name="Advanced Micro Devices, Inc. [AMD] 300 Series Chipset PCIe Port" bridge_type="1-1" depth="3" bridge_pci="0000:[08-08]" pci_busid="0000:02:06.0" pci_type="0604 [1022:43b4] [0000:0000] 02" pci_link_speed="0.250000">
+            <info name="PCIVendor" value="Advanced Micro Devices, Inc. [AMD]"/>
+            <info name="PCIDevice" value="300 Series Chipset PCIe Port"/>
+            <object type="PCIDev" os_index="32768" name="Intel Corporation I211 Gigabit Network Connection" pci_busid="0000:08:00.0" pci_type="0200 [8086:1539] [1462:7b09] 03" pci_link_speed="0.250000">
+              <info name="PCIVendor" value="Intel Corporation"/>
+              <info name="PCIDevice" value="I211 Gigabit Network Connection"/>
+              <object type="OSDev" name="enp8s0" osdev_type="2">
+                <info name="Address" value="00:d8:61:0e:b8:3e"/>
+              </object>
+            </object>
+          </object>
+        </object>
+      </object>
+      <object type="Bridge" os_index="129" name="Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Internal PCIe GPP Bridge 0 to Bus B" bridge_type="1-1" depth="1" bridge_pci="0000:[0b-0b]" pci_busid="0000:00:08.1" pci_type="0604 [1022:1454] [0000:0000] 00" pci_link_speed="15.753846">
+        <info name="PCIVendor" value="Advanced Micro Devices, Inc. [AMD]"/>
+        <info name="PCIDevice" value="Family 17h (Models 00h-0fh) Internal PCIe GPP Bridge 0 to Bus B"/>
+        <object type="PCIDev" os_index="45058" name="Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [AHCI mode]" pci_busid="0000:0b:00.2" pci_type="0106 [1022:7901] [1462:7b09] 51" pci_link_speed="15.753846">
+          <info name="PCIVendor" value="Advanced Micro Devices, Inc. [AMD]"/>
+          <info name="PCIDevice" value="FCH SATA Controller [AHCI mode]"/>
+        </object>
+      </object>
+    </object>
+    <object type="Bridge" os_index="1" bridge_type="0-1" depth="0" bridge_pci="0000:[40-42]">
+      <object type="Bridge" os_index="262273" name="Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Internal PCIe GPP Bridge 0 to Bus B" bridge_type="1-1" depth="1" bridge_pci="0000:[42-42]" pci_busid="0000:40:08.1" pci_type="0604 [1022:1454] [0000:0000] 00" pci_link_speed="15.753846">
+        <info name="PCIVendor" value="Advanced Micro Devices, Inc. [AMD]"/>
+        <info name="PCIDevice" value="Family 17h (Models 00h-0fh) Internal PCIe GPP Bridge 0 to Bus B"/>
+        <object type="PCIDev" os_index="270338" name="Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [AHCI mode]" pci_busid="0000:42:00.2" pci_type="0106 [1022:7901] [1462:7b09] 51" pci_link_speed="15.753846">
+          <info name="PCIVendor" value="Advanced Micro Devices, Inc. [AMD]"/>
+          <info name="PCIDevice" value="FCH SATA Controller [AHCI mode]"/>
+        </object>
+      </object>
+    </object>
+  </object>
+</topology>

doc/topology/Intel_Core_i7-3770_linux_2_0_4.xml

@@ -0,0 +1,87 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE topology SYSTEM "hwloc2.dtd">
+<topology version="2.0">
+  <object type="Machine" os_index="0" cpuset="0x000000ff" complete_cpuset="0x000000ff" allowed_cpuset="0x000000ff" nodeset="0x00000001" complete_nodeset="0x00000001" allowed_nodeset="0x00000001" gp_index="1">
+    <info name="DMIProductName" value="System Product Name"/>
+    <info name="DMIProductVersion" value="System Version"/>
+    <info name="DMIProductSerial" value="System Serial Number"/>
+    <info name="DMIProductUUID" value="A052D200-D7E7-11DD-BC6C-50465D9F65F8"/>
+    <info name="DMIBoardVendor" value="ASUSTeK COMPUTER INC."/>
+    <info name="DMIBoardName" value="P8H77-M PRO"/>
+    <info name="DMIBoardVersion" value="Rev X.0x"/>
+    <info name="DMIBoardSerial" value="120902368900135"/>
+    <info name="DMIBoardAssetTag" value="To be filled by O.E.M."/>
+    <info name="DMIChassisVendor" value="Chassis Manufacture"/>
+    <info name="DMIChassisType" value="3"/>
+    <info name="DMIChassisVersion" value="Chassis Version"/>
+    <info name="DMIChassisSerial" value="Chassis Serial Number"/>
+    <info name="DMIChassisAssetTag" value="Asset-1234567890"/>
+    <info name="DMIBIOSVendor" value="American Megatrends Inc."/>
+    <info name="DMIBIOSVersion" value="9002"/>
+    <info name="DMIBIOSDate" value="05/30/2014"/>
+    <info name="DMISysVendor" value="System manufacturer"/>
+    <info name="Backend" value="Linux"/>
+    <info name="LinuxCgroup" value="/"/>
+    <info name="OSName" value="Linux"/>
+    <info name="OSRelease" value="4.15.0-47-generic"/>
+    <info name="OSVersion" value="#50~16.04.1-Ubuntu SMP Fri Mar 15 16:06:21 UTC 2019"/>
+    <info name="HostName" value="host"/>
+    <info name="Architecture" value="x86_64"/>
+    <info name="hwlocVersion" value="2.0.4"/>
+    <info name="ProcessName" value="xmrig"/>
+    <object type="Package" os_index="0" cpuset="0x000000ff" complete_cpuset="0x000000ff" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="2">
+      <info name="CPUVendor" value="GenuineIntel"/>
+      <info name="CPUFamilyNumber" value="6"/>
+      <info name="CPUModelNumber" value="58"/>
+      <info name="CPUModel" value="Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz"/>
+      <info name="CPUStepping" value="9"/>
+      <object type="NUMANode" os_index="0" cpuset="0x000000ff" complete_cpuset="0x000000ff" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="24" local_memory="33405804544">
+        <page_type size="4096" count="7490114"/>
+        <page_type size="2097152" count="1300"/>
+      </object>
+      <object type="L3Cache" cpuset="0x000000ff" complete_cpuset="0x000000ff" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="7" cache_size="8388608" depth="3" cache_linesize="64" cache_associativity="16" cache_type="0">
+        <info name="Inclusive" value="1"/>
+        <object type="L2Cache" cpuset="0x00000011" complete_cpuset="0x00000011" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="6" cache_size="262144" depth="2" cache_linesize="64" cache_associativity="8" cache_type="0">
+          <info name="Inclusive" value="0"/>
+          <object type="L1Cache" cpuset="0x00000011" complete_cpuset="0x00000011" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="5" cache_size="32768" depth="1" cache_linesize="64" cache_associativity="8" cache_type="1">
+            <info name="Inclusive" value="0"/>
+            <object type="Core" os_index="0" cpuset="0x00000011" complete_cpuset="0x00000011" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="3">
+              <object type="PU" os_index="0" cpuset="0x00000001" complete_cpuset="0x00000001" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="4"/>
+              <object type="PU" os_index="4" cpuset="0x00000010" complete_cpuset="0x00000010" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="20"/>
+            </object>
+          </object>
+        </object>
+        <object type="L2Cache" cpuset="0x00000022" complete_cpuset="0x00000022" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="11" cache_size="262144" depth="2" cache_linesize="64" cache_associativity="8" cache_type="0">
+          <info name="Inclusive" value="0"/>
+          <object type="L1Cache" cpuset="0x00000022" complete_cpuset="0x00000022" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="10" cache_size="32768" depth="1" cache_linesize="64" cache_associativity="8" cache_type="1">
+            <info name="Inclusive" value="0"/>
+            <object type="Core" os_index="1" cpuset="0x00000022" complete_cpuset="0x00000022" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="8">
+              <object type="PU" os_index="1" cpuset="0x00000002" complete_cpuset="0x00000002" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="9"/>
+              <object type="PU" os_index="5" cpuset="0x00000020" complete_cpuset="0x00000020" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="21"/>
+            </object>
+          </object>
+        </object>
+        <object type="L2Cache" cpuset="0x00000044" complete_cpuset="0x00000044" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="15" cache_size="262144" depth="2" cache_linesize="64" cache_associativity="8" cache_type="0">
+          <info name="Inclusive" value="0"/>
+          <object type="L1Cache" cpuset="0x00000044" complete_cpuset="0x00000044" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="14" cache_size="32768" depth="1" cache_linesize="64" cache_associativity="8" cache_type="1">
+            <info name="Inclusive" value="0"/>
+            <object type="Core" os_index="2" cpuset="0x00000044" complete_cpuset="0x00000044" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="12">
+              <object type="PU" os_index="2" cpuset="0x00000004" complete_cpuset="0x00000004" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="13"/>
+              <object type="PU" os_index="6" cpuset="0x00000040" complete_cpuset="0x00000040" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="22"/>
+            </object>
+          </object>
+        </object>
+        <object type="L2Cache" cpuset="0x00000088" complete_cpuset="0x00000088" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="19" cache_size="262144" depth="2" cache_linesize="64" cache_associativity="8" cache_type="0">
+          <info name="Inclusive" value="0"/>
+          <object type="L1Cache" cpuset="0x00000088" complete_cpuset="0x00000088" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="18" cache_size="32768" depth="1" cache_linesize="64" cache_associativity="8" cache_type="1">
+            <info name="Inclusive" value="0"/>
+            <object type="Core" os_index="3" cpuset="0x00000088" complete_cpuset="0x00000088" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="16">
+              <object type="PU" os_index="3" cpuset="0x00000008" complete_cpuset="0x00000008" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="17"/>
+              <object type="PU" os_index="7" cpuset="0x00000080" complete_cpuset="0x00000080" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="23"/>
+            </object>
+          </object>
+        </object>
+      </object>
+    </object>
+  </object>
+</topology>

doc/topology/Intel_Core_i7-6700_linux_2_0_4.xml

@@ -0,0 +1,88 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE topology SYSTEM "hwloc2.dtd">
+<topology version="2.0">
+  <object type="Machine" os_index="0" cpuset="0x000000ff" complete_cpuset="0x000000ff" allowed_cpuset="0x000000ff" nodeset="0x00000001" complete_nodeset="0x00000001" allowed_nodeset="0x00000001" gp_index="1">
+    <info name="DMIProductName" value="D3401-H1"/>
+    <info name="DMIProductVersion" value="        "/>
+    <info name="DMIProductSerial" value="        "/>
+    <info name="DMIProductUUID" value="283D9705-B724-F44A-850D-38F54DAC56AD"/>
+    <info name="DMIBoardVendor" value="FUJITSU"/>
+    <info name="DMIBoardName" value="D3401-H1"/>
+    <info name="DMIBoardVersion" value="S26361-D3401-H1            "/>
+    <info name="DMIBoardSerial" value="B2980829"/>
+    <info name="DMIBoardAssetTag" value="        "/>
+    <info name="DMIChassisVendor" value="FUJITSU"/>
+    <info name="DMIChassisType" value="3"/>
+    <info name="DMIChassisVersion" value="        "/>
+    <info name="DMIChassisSerial" value="        "/>
+    <info name="DMIChassisAssetTag" value="        "/>
+    <info name="DMIBIOSVendor" value="FUJITSU // American Megatrends Inc."/>
+    <info name="DMIBIOSVersion" value="V5.0.0.11 R1.14.0 for D3401-H1x                   "/>
+    <info name="DMIBIOSDate" value="06/09/2016"/>
+    <info name="DMISysVendor" value="FUJITSU"/>
+    <info name="Backend" value="Linux"/>
+    <info name="LinuxCgroup" value="/"/>
+    <info name="OSName" value="Linux"/>
+    <info name="OSRelease" value="4.4.0-45-generic"/>
+    <info name="OSVersion" value="#66-Ubuntu SMP Wed Oct 19 14:12:37 UTC 2016"/>
+    <info name="HostName" value="host"/>
+    <info name="Architecture" value="x86_64"/>
+    <info name="hwlocVersion" value="2.0.4"/>
+    <info name="ProcessName" value="xmrig"/>
+    <object type="Package" os_index="0" cpuset="0x000000ff" complete_cpuset="0x000000ff" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="2">
+      <info name="CPUVendor" value="GenuineIntel"/>
+      <info name="CPUFamilyNumber" value="6"/>
+      <info name="CPUModelNumber" value="94"/>
+      <info name="CPUModel" value="Intel(R) Core(TM) i7-6700 CPU @ 3.40GHz"/>
+      <info name="CPUStepping" value="3"/>
+      <object type="NUMANode" os_index="0" cpuset="0x000000ff" complete_cpuset="0x000000ff" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="24" local_memory="33558884352">
+        <page_type size="4096" count="8184895"/>
+        <page_type size="2097152" count="16"/>
+        <page_type size="1073741824" count="0"/>
+      </object>
+      <object type="L3Cache" cpuset="0x000000ff" complete_cpuset="0x000000ff" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="7" cache_size="8388608" depth="3" cache_linesize="64" cache_associativity="16" cache_type="0">
+        <info name="Inclusive" value="1"/>
+        <object type="L2Cache" cpuset="0x00000011" complete_cpuset="0x00000011" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="6" cache_size="262144" depth="2" cache_linesize="64" cache_associativity="4" cache_type="0">
+          <info name="Inclusive" value="0"/>
+          <object type="L1Cache" cpuset="0x00000011" complete_cpuset="0x00000011" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="5" cache_size="32768" depth="1" cache_linesize="64" cache_associativity="8" cache_type="1">
+            <info name="Inclusive" value="0"/>
+            <object type="Core" os_index="0" cpuset="0x00000011" complete_cpuset="0x00000011" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="3">
+              <object type="PU" os_index="0" cpuset="0x00000001" complete_cpuset="0x00000001" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="4"/>
+              <object type="PU" os_index="4" cpuset="0x00000010" complete_cpuset="0x00000010" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="20"/>
+            </object>
+          </object>
+        </object>
+        <object type="L2Cache" cpuset="0x00000022" complete_cpuset="0x00000022" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="11" cache_size="262144" depth="2" cache_linesize="64" cache_associativity="4" cache_type="0">
+          <info name="Inclusive" value="0"/>
+          <object type="L1Cache" cpuset="0x00000022" complete_cpuset="0x00000022" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="10" cache_size="32768" depth="1" cache_linesize="64" cache_associativity="8" cache_type="1">
+            <info name="Inclusive" value="0"/>
+            <object type="Core" os_index="1" cpuset="0x00000022" complete_cpuset="0x00000022" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="8">
+              <object type="PU" os_index="1" cpuset="0x00000002" complete_cpuset="0x00000002" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="9"/>
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+          <object type="L1Cache" cpuset="0x00000044" complete_cpuset="0x00000044" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="14" cache_size="32768" depth="1" cache_linesize="64" cache_associativity="8" cache_type="1">
+            <info name="Inclusive" value="0"/>
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+        <object type="L2Cache" cpuset="0x00000088" complete_cpuset="0x00000088" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="19" cache_size="262144" depth="2" cache_linesize="64" cache_associativity="4" cache_type="0">
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+          <object type="L1Cache" cpuset="0x00000088" complete_cpuset="0x00000088" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="18" cache_size="32768" depth="1" cache_linesize="64" cache_associativity="8" cache_type="1">
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+            <object type="Core" os_index="3" cpuset="0x00000088" complete_cpuset="0x00000088" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="16">
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+  </object>
+</topology>

doc/topology/Intel_Core_i7-6700_windows_2_0_4.xml

@@ -0,0 +1,61 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE topology SYSTEM "hwloc2.dtd">
+<topology version="2.0">
+  <object type="Machine" os_index="0" cpuset="0x000000ff" complete_cpuset="0x000000ff" allowed_cpuset="0x000000ff" nodeset="0x00000001" complete_nodeset="0x00000001" allowed_nodeset="0x00000001" gp_index="1">
+    <info name="Backend" value="Windows"/>
+    <info name="hwlocVersion" value="2.0.4"/>
+    <object type="Package" cpuset="0x000000ff" complete_cpuset="0x000000ff" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="2">
+      <info name="CPUVendor" value="GenuineIntel"/>
+      <info name="CPUFamilyNumber" value="6"/>
+      <info name="CPUModelNumber" value="94"/>
+      <info name="CPUModel" value="Intel(R) Core(TM) i7-6700 CPU @ 3.40GHz"/>
+      <info name="CPUStepping" value="3"/>
+      <object type="NUMANode" os_index="0" cpuset="0x000000ff" complete_cpuset="0x000000ff" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="16" local_memory="16811286528">
+        <page_type size="4096" count="0"/>
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+        <object type="L2Cache" cpuset="0x00000003" complete_cpuset="0x00000003" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="5" cache_size="262144" depth="2" cache_linesize="64" cache_associativity="4" cache_type="0">
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doc/topology/Intel_Core_i7-7660U_windows_2_0_4.xml

@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE topology SYSTEM "hwloc2.dtd">
+<topology version="2.0">
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+    <info name="hwlocVersion" value="2.0.4"/>
+    <object type="Package" cpuset="0x0000000f" complete_cpuset="0x0000000f" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="2">
+      <info name="CPUVendor" value="GenuineIntel"/>
+      <info name="CPUFamilyNumber" value="6"/>
+      <info name="CPUModelNumber" value="142"/>
+      <info name="CPUModel" value="Intel(R) Core(TM) i7-7660U CPU @ 2.50GHz"/>
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+      <object type="NUMANode" os_index="0" cpuset="0x0000000f" complete_cpuset="0x0000000f" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="10" local_memory="12868972544">
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doc/topology/Intel_Xeon_E5-4650_0_x4_N4_windows_2_0_4.xml

@@ -0,0 +1,477 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE topology SYSTEM "hwloc2.dtd">
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+    <object type="Package" cpuset="0x0000ffff" complete_cpuset="0x0000ffff" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="2">
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+      <info name="CPUModel" value="Intel(R) Xeon(R) CPU E5-4650 0 @ 2.70GHz"/>
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+  </object>
+</topology>

doc/topology/Intel_Xeon_E5620_x2_UMA_windows_2_0_4.xml

@@ -0,0 +1,111 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE topology SYSTEM "hwloc2.dtd">
+<topology version="2.0">
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+    <info name="hwlocVersion" value="2.0.4"/>
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+      <info name="CPUVendor" value="GenuineIntel"/>
+      <info name="CPUFamilyNumber" value="6"/>
+      <info name="CPUModelNumber" value="44"/>
+      <info name="CPUModel" value="Intel(R) Xeon(R) CPU           E5620  @ 2.40GHz"/>
+      <info name="CPUStepping" value="2"/>
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+            <object type="Core" cpuset="0x00000003" complete_cpuset="0x00000003" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="3">
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doc/topology/Intel_Xeon_E7-4870_x4_N4_windows_2_0_4.xml

@@ -0,0 +1,541 @@
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doc/topology/Intel_Xeon_Gold_6146_x2_UMA_linux_2_0_4.xml

@@ -0,0 +1,246 @@
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doc/topology/Intel_Xeon_Silver_4114_x2_N2_linux_1_11_9.xml

@@ -0,0 +1,403 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE topology SYSTEM "hwloc.dtd">
+<topology>
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+    <page_type size="4096" count="0"/>
+    <page_type size="2097152" count="0"/>
+    <page_type size="1073741824" count="0"/>
+    <info name="DMIProductName" value="PowerEdge C6420"/>
+    <info name="DMIProductVersion" value=""/>
+    <info name="DMIBoardVendor" value="Dell Inc."/>
+    <info name="DMIBoardName" value="0K2TT6"/>
+    <info name="DMIBoardVersion" value="A07"/>
+    <info name="DMIBoardAssetTag" value=""/>
+    <info name="DMIChassisVendor" value="Dell Inc."/>
+    <info name="DMIChassisType" value="23"/>
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+                </object>
+              </object>
+            </object>
+          </object>
+          <object type="Cache" cpuset="0x00000080,0x00080000" complete_cpuset="0x00000080,0x00080000" online_cpuset="0x00000080,0x00080000" allowed_cpuset="0x00000080,0x00080000" nodeset="0x00000002" complete_nodeset="0x00000002" allowed_nodeset="0x00000002" cache_size="1048576" depth="2" cache_linesize="64" cache_associativity="16" cache_type="0">
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+            <object type="Cache" cpuset="0x00000080,0x00080000" complete_cpuset="0x00000080,0x00080000" online_cpuset="0x00000080,0x00080000" allowed_cpuset="0x00000080,0x00080000" nodeset="0x00000002" complete_nodeset="0x00000002" allowed_nodeset="0x00000002" cache_size="32768" depth="1" cache_linesize="64" cache_associativity="8" cache_type="1">
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+                <info name="Inclusive" value="0"/>
+                <object type="Core" os_index="10" cpuset="0x00000080,0x00080000" complete_cpuset="0x00000080,0x00080000" online_cpuset="0x00000080,0x00080000" allowed_cpuset="0x00000080,0x00080000" nodeset="0x00000002" complete_nodeset="0x00000002" allowed_nodeset="0x00000002">
+                  <object type="PU" os_index="19" cpuset="0x00080000" complete_cpuset="0x00080000" online_cpuset="0x00080000" allowed_cpuset="0x00080000" nodeset="0x00000002" complete_nodeset="0x00000002" allowed_nodeset="0x00000002"/>
+                  <object type="PU" os_index="39" cpuset="0x00000080,0x0" complete_cpuset="0x00000080,0x0" online_cpuset="0x00000080,0x0" allowed_cpuset="0x00000080,0x0" nodeset="0x00000002" complete_nodeset="0x00000002" allowed_nodeset="0x00000002"/>
+                </object>
+              </object>
+            </object>
+          </object>
+        </object>
+      </object>
+      <object type="Bridge" os_index="7" bridge_type="0-1" depth="0" bridge_pci="0000:[d7-db]">
+        <object type="Bridge" os_index="880640" name="Intel Corporation Sky Lake-E PCI Express Root Port A" bridge_type="1-1" depth="1" bridge_pci="0000:[d8-d8]" pci_busid="0000:d7:00.0" pci_type="0604 [8086:2030] [0000:0000] 04" pci_link_speed="0.000000">
+          <info name="PCIVendor" value="Intel Corporation"/>
+          <info name="PCIDevice" value="Sky Lake-E PCI Express Root Port A"/>
+          <object type="PCIDev" os_index="884736" name="Intel Corporation Express Flash NVMe P4500/P4600" pci_busid="0000:d8:00.0" pci_type="0108 [8086:0a54] [1028:1fe1] 00" pci_link_speed="0.000000">
+            <info name="PCIVendor" value="Intel Corporation"/>
+            <info name="PCIDevice" value="Express Flash NVMe P4500/P4600"/>
+            <info name="PCISlot" value="160"/>
+          </object>
+        </object>
+        <object type="Bridge" os_index="880656" name="Intel Corporation Sky Lake-E PCI Express Root Port B" bridge_type="1-1" depth="1" bridge_pci="0000:[d9-d9]" pci_busid="0000:d7:01.0" pci_type="0604 [8086:2031] [0000:0000] 04" pci_link_speed="0.000000">
+          <info name="PCIVendor" value="Intel Corporation"/>
+          <info name="PCIDevice" value="Sky Lake-E PCI Express Root Port B"/>
+          <object type="PCIDev" os_index="888832" name="Intel Corporation Express Flash NVMe P4500/P4600" pci_busid="0000:d9:00.0" pci_type="0108 [8086:0a54] [1028:1fe1] 00" pci_link_speed="0.000000">
+            <info name="PCIVendor" value="Intel Corporation"/>
+            <info name="PCIDevice" value="Express Flash NVMe P4500/P4600"/>
+            <info name="PCISlot" value="161"/>
+          </object>
+        </object>
+      </object>
+    </object>
+  </object>
+</topology>

doc/topology/Intel_Xeon_Silver_4114_x2_N2_linux_2_0_4.xml

@@ -0,0 +1,263 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE topology SYSTEM "hwloc2.dtd">
+<topology version="2.0">
+  <object type="Machine" os_index="0" cpuset="0x000000ff,0xffffffff" complete_cpuset="0x000000ff,0xffffffff" allowed_cpuset="0x000000ff,0xffffffff" nodeset="0x00000003" complete_nodeset="0x00000003" allowed_nodeset="0x00000003" gp_index="1">
+    <info name="DMIProductName" value="PowerEdge C6420"/>
+    <info name="DMIProductVersion" value=""/>
+    <info name="DMIBoardVendor" value="Dell Inc."/>
+    <info name="DMIBoardName" value="0K2TT6"/>
+    <info name="DMIBoardVersion" value="A07"/>
+    <info name="DMIBoardAssetTag" value=""/>
+    <info name="DMIChassisVendor" value="Dell Inc."/>
+    <info name="DMIChassisType" value="23"/>
+    <info name="DMIChassisVersion" value="PowerEdge C6400"/>
+    <info name="DMIChassisAssetTag" value=""/>
+    <info name="DMIBIOSVendor" value="Dell Inc."/>
+    <info name="DMIBIOSVersion" value="1.4.9"/>
+    <info name="DMIBIOSDate" value="05/30/2018"/>
+    <info name="DMISysVendor" value="Dell Inc."/>
+    <info name="Backend" value="Linux"/>
+    <info name="LinuxCgroup" value="/"/>
+    <info name="OSName" value="Linux"/>
+    <info name="OSRelease" value="4.15.0-55-generic"/>
+    <info name="OSVersion" value="#60-Ubuntu SMP Tue Jul 2 18:22:20 UTC 2019"/>
+    <info name="HostName" value="sd-146751"/>
+    <info name="Architecture" value="x86_64"/>
+    <info name="hwlocVersion" value="2.0.4"/>
+    <info name="ProcessName" value="xmrig"/>
+    <object type="Package" os_index="0" cpuset="0x00000055,0x55555555" complete_cpuset="0x00000055,0x55555555" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="2">
+      <info name="CPUVendor" value="GenuineIntel"/>
+      <info name="CPUFamilyNumber" value="6"/>
+      <info name="CPUModelNumber" value="85"/>
+      <info name="CPUModel" value="Intel(R) Xeon(R) Silver 4114 CPU @ 2.20GHz"/>
+      <info name="CPUStepping" value="4"/>
+      <object type="NUMANode" os_index="0" cpuset="0x00000055,0x55555555" complete_cpuset="0x00000055,0x55555555" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="106" local_memory="67245707264">
+        <page_type size="4096" count="15762049"/>
+        <page_type size="2097152" count="1280"/>
+        <page_type size="1073741824" count="0"/>
+      </object>
+      <object type="L3Cache" cpuset="0x00000055,0x55555555" complete_cpuset="0x00000055,0x55555555" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="7" cache_size="14417920" depth="3" cache_linesize="64" cache_associativity="11" cache_type="0">
+        <info name="Inclusive" value="0"/>
+        <object type="L2Cache" cpuset="0x00100001" complete_cpuset="0x00100001" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="6" cache_size="1048576" depth="2" cache_linesize="64" cache_associativity="16" cache_type="0">
+          <info name="Inclusive" value="0"/>
+          <object type="L1Cache" cpuset="0x00100001" complete_cpuset="0x00100001" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="5" cache_size="32768" depth="1" cache_linesize="64" cache_associativity="8" cache_type="1">
+            <info name="Inclusive" value="0"/>
+            <object type="Core" os_index="0" cpuset="0x00100001" complete_cpuset="0x00100001" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="3">
+              <object type="PU" os_index="0" cpuset="0x00000001" complete_cpuset="0x00000001" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="4"/>
+              <object type="PU" os_index="20" cpuset="0x00100000" complete_cpuset="0x00100000" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="86"/>
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+          </object>
+        </object>
+        <object type="L2Cache" cpuset="0x00400004" complete_cpuset="0x00400004" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="17" cache_size="1048576" depth="2" cache_linesize="64" cache_associativity="16" cache_type="0">
+          <info name="Inclusive" value="0"/>
+          <object type="L1Cache" cpuset="0x00400004" complete_cpuset="0x00400004" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="16" cache_size="32768" depth="1" cache_linesize="64" cache_associativity="8" cache_type="1">
+            <info name="Inclusive" value="0"/>
+            <object type="Core" os_index="4" cpuset="0x00400004" complete_cpuset="0x00400004" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="14">
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+        <object type="L2Cache" cpuset="0x01000010" complete_cpuset="0x01000010" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="25" cache_size="1048576" depth="2" cache_linesize="64" cache_associativity="16" cache_type="0">
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+            <info name="Inclusive" value="0"/>
+            <object type="Core" os_index="1" cpuset="0x01000010" complete_cpuset="0x01000010" nodeset="0x00000001" complete_nodeset="0x00000001" gp_index="22">
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+      <info name="CPUFamilyNumber" value="6"/>
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+      <info name="CPUModel" value="Intel(R) Xeon(R) Silver 4114 CPU @ 2.20GHz"/>
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+              <object type="PU" os_index="23" cpuset="0x00800000" complete_cpuset="0x00800000" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="89"/>
+            </object>
+          </object>
+        </object>
+        <object type="L2Cache" cpuset="0x02000020" complete_cpuset="0x02000020" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="29" cache_size="1048576" depth="2" cache_linesize="64" cache_associativity="16" cache_type="0">
+          <info name="Inclusive" value="0"/>
+          <object type="L1Cache" cpuset="0x02000020" complete_cpuset="0x02000020" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="28" cache_size="32768" depth="1" cache_linesize="64" cache_associativity="8" cache_type="1">
+            <info name="Inclusive" value="0"/>
+            <object type="Core" os_index="1" cpuset="0x02000020" complete_cpuset="0x02000020" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="26">
+              <object type="PU" os_index="5" cpuset="0x00000020" complete_cpuset="0x00000020" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="27"/>
+              <object type="PU" os_index="25" cpuset="0x02000000" complete_cpuset="0x02000000" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="91"/>
+            </object>
+          </object>
+        </object>
+        <object type="L2Cache" cpuset="0x08000080" complete_cpuset="0x08000080" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="37" cache_size="1048576" depth="2" cache_linesize="64" cache_associativity="16" cache_type="0">
+          <info name="Inclusive" value="0"/>
+          <object type="L1Cache" cpuset="0x08000080" complete_cpuset="0x08000080" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="36" cache_size="32768" depth="1" cache_linesize="64" cache_associativity="8" cache_type="1">
+            <info name="Inclusive" value="0"/>
+            <object type="Core" os_index="3" cpuset="0x08000080" complete_cpuset="0x08000080" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="34">
+              <object type="PU" os_index="7" cpuset="0x00000080" complete_cpuset="0x00000080" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="35"/>
+              <object type="PU" os_index="27" cpuset="0x08000000" complete_cpuset="0x08000000" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="93"/>
+            </object>
+          </object>
+        </object>
+        <object type="L2Cache" cpuset="0x20000200" complete_cpuset="0x20000200" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="45" cache_size="1048576" depth="2" cache_linesize="64" cache_associativity="16" cache_type="0">
+          <info name="Inclusive" value="0"/>
+          <object type="L1Cache" cpuset="0x20000200" complete_cpuset="0x20000200" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="44" cache_size="32768" depth="1" cache_linesize="64" cache_associativity="8" cache_type="1">
+            <info name="Inclusive" value="0"/>
+            <object type="Core" os_index="2" cpuset="0x20000200" complete_cpuset="0x20000200" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="42">
+              <object type="PU" os_index="9" cpuset="0x00000200" complete_cpuset="0x00000200" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="43"/>
+              <object type="PU" os_index="29" cpuset="0x20000000" complete_cpuset="0x20000000" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="95"/>
+            </object>
+          </object>
+        </object>
+        <object type="L2Cache" cpuset="0x80000800" complete_cpuset="0x80000800" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="53" cache_size="1048576" depth="2" cache_linesize="64" cache_associativity="16" cache_type="0">
+          <info name="Inclusive" value="0"/>
+          <object type="L1Cache" cpuset="0x80000800" complete_cpuset="0x80000800" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="52" cache_size="32768" depth="1" cache_linesize="64" cache_associativity="8" cache_type="1">
+            <info name="Inclusive" value="0"/>
+            <object type="Core" os_index="12" cpuset="0x80000800" complete_cpuset="0x80000800" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="50">
+              <object type="PU" os_index="11" cpuset="0x00000800" complete_cpuset="0x00000800" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="51"/>
+              <object type="PU" os_index="31" cpuset="0x80000000" complete_cpuset="0x80000000" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="97"/>
+            </object>
+          </object>
+        </object>
+        <object type="L2Cache" cpuset="0x00000002,0x00002000" complete_cpuset="0x00000002,0x00002000" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="61" cache_size="1048576" depth="2" cache_linesize="64" cache_associativity="16" cache_type="0">
+          <info name="Inclusive" value="0"/>
+          <object type="L1Cache" cpuset="0x00000002,0x00002000" complete_cpuset="0x00000002,0x00002000" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="60" cache_size="32768" depth="1" cache_linesize="64" cache_associativity="8" cache_type="1">
+            <info name="Inclusive" value="0"/>
+            <object type="Core" os_index="8" cpuset="0x00000002,0x00002000" complete_cpuset="0x00000002,0x00002000" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="58">
+              <object type="PU" os_index="13" cpuset="0x00002000" complete_cpuset="0x00002000" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="59"/>
+              <object type="PU" os_index="33" cpuset="0x00000002,0x0" complete_cpuset="0x00000002,0x0" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="99"/>
+            </object>
+          </object>
+        </object>
+        <object type="L2Cache" cpuset="0x00000008,0x00008000" complete_cpuset="0x00000008,0x00008000" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="69" cache_size="1048576" depth="2" cache_linesize="64" cache_associativity="16" cache_type="0">
+          <info name="Inclusive" value="0"/>
+          <object type="L1Cache" cpuset="0x00000008,0x00008000" complete_cpuset="0x00000008,0x00008000" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="68" cache_size="32768" depth="1" cache_linesize="64" cache_associativity="8" cache_type="1">
+            <info name="Inclusive" value="0"/>
+            <object type="Core" os_index="11" cpuset="0x00000008,0x00008000" complete_cpuset="0x00000008,0x00008000" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="66">
+              <object type="PU" os_index="15" cpuset="0x00008000" complete_cpuset="0x00008000" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="67"/>
+              <object type="PU" os_index="35" cpuset="0x00000008,0x0" complete_cpuset="0x00000008,0x0" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="101"/>
+            </object>
+          </object>
+        </object>
+        <object type="L2Cache" cpuset="0x00000020,0x00020000" complete_cpuset="0x00000020,0x00020000" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="77" cache_size="1048576" depth="2" cache_linesize="64" cache_associativity="16" cache_type="0">
+          <info name="Inclusive" value="0"/>
+          <object type="L1Cache" cpuset="0x00000020,0x00020000" complete_cpuset="0x00000020,0x00020000" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="76" cache_size="32768" depth="1" cache_linesize="64" cache_associativity="8" cache_type="1">
+            <info name="Inclusive" value="0"/>
+            <object type="Core" os_index="9" cpuset="0x00000020,0x00020000" complete_cpuset="0x00000020,0x00020000" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="74">
+              <object type="PU" os_index="17" cpuset="0x00020000" complete_cpuset="0x00020000" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="75"/>
+              <object type="PU" os_index="37" cpuset="0x00000020,0x0" complete_cpuset="0x00000020,0x0" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="103"/>
+            </object>
+          </object>
+        </object>
+        <object type="L2Cache" cpuset="0x00000080,0x00080000" complete_cpuset="0x00000080,0x00080000" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="85" cache_size="1048576" depth="2" cache_linesize="64" cache_associativity="16" cache_type="0">
+          <info name="Inclusive" value="0"/>
+          <object type="L1Cache" cpuset="0x00000080,0x00080000" complete_cpuset="0x00000080,0x00080000" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="84" cache_size="32768" depth="1" cache_linesize="64" cache_associativity="8" cache_type="1">
+            <info name="Inclusive" value="0"/>
+            <object type="Core" os_index="10" cpuset="0x00000080,0x00080000" complete_cpuset="0x00000080,0x00080000" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="82">
+              <object type="PU" os_index="19" cpuset="0x00080000" complete_cpuset="0x00080000" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="83"/>
+              <object type="PU" os_index="39" cpuset="0x00000080,0x0" complete_cpuset="0x00000080,0x0" nodeset="0x00000002" complete_nodeset="0x00000002" gp_index="105"/>
+            </object>
+          </object>
+        </object>
+      </object>
+    </object>
+  </object>
+  <distances2 type="NUMANode" nbobjs="2" kind="5" indexing="os">
+    <indexes length="4">0 1 </indexes>
+    <u64values length="12">10 21 21 10 </u64values>
+  </distances2>
+</topology>

package.json

@@ -0,0 +1,23 @@
+{
+  "name": "xmrig",
+  "version": "3.0.0",
+  "description": "RandomX, CryptoNight and Argon2 miner",
+  "main": "index.js",
+  "directories": {
+    "doc": "doc"
+  },
+  "scripts": {
+    "build": "node scripts/generate_cl.js"
+  },
+  "repository": {
+    "type": "git",
+    "url": "git+https://github.com/xmrig/xmrig.git"
+  },
+  "keywords": [],
+  "author": "",
+  "license": "GPLv3",
+  "bugs": {
+    "url": "https://github.com/xmrig/xmrig/issues"
+  },
+  "homepage": "https://github.com/xmrig/xmrig#readme"
+}

res/app.rc

@@ -1,11 +1,11 @@
 #include <windows.h>
 #include "../src/version.h"
 
-IDI_ICON1    ICON    DISCARDABLE    "app.ico"
+101 ICON "app.ico"
 
 VS_VERSION_INFO VERSIONINFO
-  FILEVERSION APP_VER_MAJOR,APP_VER_MINOR,APP_VER_BUILD,APP_VER_REV
-  PRODUCTVERSION APP_VER_MAJOR,APP_VER_MINOR,APP_VER_BUILD,APP_VER_REV
+  FILEVERSION APP_VER_MAJOR,APP_VER_MINOR,APP_VER_PATCH,0
+  PRODUCTVERSION APP_VER_MAJOR,APP_VER_MINOR,APP_VER_PATCH,0
   FILEFLAGSMASK 0x3fL
 #ifdef _DEBUG
   FILEFLAGS VS_FF_DEBUG

scripts/build.hwloc.sh

@@ -0,0 +1,19 @@
+#!/bin/bash -e
+
+HWLOC_VERSION="2.2.0"
+
+mkdir -p deps
+mkdir -p deps/include
+mkdir -p deps/lib
+
+mkdir -p build && cd build
+
+wget https://download.open-mpi.org/release/hwloc/v2.2/hwloc-${HWLOC_VERSION}.tar.bz2 -O hwloc-${HWLOC_VERSION}.tar.bz2
+tar -xjf hwloc-${HWLOC_VERSION}.tar.bz2
+
+cd hwloc-${HWLOC_VERSION}
+./configure --disable-shared --enable-static --disable-io --disable-libudev --disable-libxml2
+make -j$(nproc)
+cp -fr include/ ../../deps
+cp hwloc/.libs/libhwloc.a ../../deps/lib
+cd ..

scripts/build.libressl.sh

@@ -0,0 +1,20 @@
+#!/bin/bash -e
+
+LIBRESSL_VERSION="3.0.2"
+
+mkdir -p deps
+mkdir -p deps/include
+mkdir -p deps/lib
+
+mkdir -p build && cd build
+
+wget https://ftp.openbsd.org/pub/OpenBSD/LibreSSL/libressl-${LIBRESSL_VERSION}.tar.gz -O libressl-${LIBRESSL_VERSION}.tar.gz
+tar -xzf libressl-${LIBRESSL_VERSION}.tar.gz
+
+cd libressl-${LIBRESSL_VERSION}
+./configure --disable-shared
+make -j$(nproc)
+cp -fr include/ ../../deps
+cp crypto/.libs/libcrypto.a ../../deps/lib
+cp ssl/.libs/libssl.a ../../deps/lib
+cd ..

scripts/build.openssl.sh

@@ -0,0 +1,20 @@
+#!/bin/bash -e
+
+OPENSSL_VERSION="1.1.1g"
+
+mkdir -p deps
+mkdir -p deps/include
+mkdir -p deps/lib
+
+mkdir -p build && cd build
+
+wget https://www.openssl.org/source/openssl-${OPENSSL_VERSION}.tar.gz -O openssl-${OPENSSL_VERSION}.tar.gz
+tar -xzf openssl-${OPENSSL_VERSION}.tar.gz
+
+cd openssl-${OPENSSL_VERSION}
+./config -no-shared -no-asm -no-zlib -no-comp -no-dgram -no-filenames -no-cms
+make -j$(nproc)
+cp -fr include/ ../../deps
+cp libcrypto.a ../../deps/lib
+cp libssl.a ../../deps/lib
+cd ..

scripts/build.uv.sh

@@ -0,0 +1,20 @@
+#!/bin/bash -e
+
+UV_VERSION="1.38.0"
+
+mkdir -p deps
+mkdir -p deps/include
+mkdir -p deps/lib
+
+mkdir -p build && cd build
+
+wget https://github.com/libuv/libuv/archive/v${UV_VERSION}.tar.gz -O v${UV_VERSION}.tar.gz
+tar -xzf v${UV_VERSION}.tar.gz
+
+cd libuv-${UV_VERSION}
+sh autogen.sh
+./configure --disable-shared
+make -j$(nproc)
+cp -fr include/ ../../deps
+cp .libs/libuv.a ../../deps/lib
+cd ..

scripts/build_deps.sh

@@ -0,0 +1,5 @@
+#!/bin/bash -e
+
+./build.uv.sh
+./build.hwloc.sh
+./build.openssl.sh

scripts/enable_1gb_pages.sh

@@ -0,0 +1,12 @@
+#!/bin/bash -e
+
+# https://xmrig.com/docs/miner/hugepages#onegb-huge-pages
+
+sysctl -w vm.nr_hugepages=$(nproc)
+
+for i in $(find /sys/devices/system/node/node* -maxdepth 0 -type d);
+do
+    echo 3 > "$i/hugepages/hugepages-1048576kB/nr_hugepages";
+done
+
+echo "1GB pages successfully enabled"

scripts/generate_cl.js

@@ -0,0 +1,108 @@
+#!/usr/bin/env node
+
+'use strict';
+
+const fs = require('fs');
+const path = require('path');
+const { text2h, text2h_bundle, addIncludes } = require('./js/opencl');
+const { opencl_minify } = require('./js/opencl_minify');
+const cwd = process.cwd();
+
+
+function cn()
+{
+    const cn = opencl_minify(addIncludes('cryptonight.cl', [
+        'algorithm.cl',
+        'wolf-aes.cl',
+        'wolf-skein.cl',
+        'jh.cl',
+        'blake256.cl',
+        'groestl256.cl',
+        'fast_int_math_v2.cl',
+        'fast_div_heavy.cl',
+        'keccak.cl'
+    ]));
+
+    // fs.writeFileSync('cryptonight_gen.cl', cn);
+    fs.writeFileSync('cryptonight_cl.h', text2h(cn, 'xmrig', 'cryptonight_cl'));
+}
+
+
+function cn_r()
+{
+    const items = {};
+
+    items.cryptonight_r_defines_cl = opencl_minify(addIncludes('cryptonight_r_defines.cl', [ 'wolf-aes.cl' ]));
+    items.cryptonight_r_cl         = opencl_minify(fs.readFileSync('cryptonight_r.cl', 'utf8'));
+
+    // for (let key in items) {
+    //      fs.writeFileSync(key + '_gen.cl', items[key]);
+    // }
+
+    fs.writeFileSync('cryptonight_r_cl.h', text2h_bundle('xmrig', items));
+}
+
+
+function rx()
+{
+    let rx = addIncludes('randomx.cl', [
+        '../cn/algorithm.cl',
+        'randomx_constants_monero.h',
+        'randomx_constants_wow.h',
+        'randomx_constants_loki.h',
+        'randomx_constants_arqma.h',
+        'randomx_constants_keva.h',
+        'aes.cl',
+        'blake2b.cl',
+        'randomx_vm.cl',
+        'randomx_jit.cl'
+    ]);
+
+    rx = rx.replace(/(\t| )*#include "fillAes1Rx4.cl"/g, fs.readFileSync('fillAes1Rx4.cl', 'utf8'));
+    rx = rx.replace(/(\t| )*#include "blake2b_double_block.cl"/g, fs.readFileSync('blake2b_double_block.cl', 'utf8'));
+    rx = opencl_minify(rx);
+
+    //fs.writeFileSync('randomx_gen.cl', rx);
+    fs.writeFileSync('randomx_cl.h', text2h(rx, 'xmrig', 'randomx_cl'));
+}
+
+
+function astrobwt()
+{
+    const astrobwt = opencl_minify(addIncludes('astrobwt.cl', [ 'BWT.cl', 'salsa20.cl', 'sha3.cl' ]));
+
+    // fs.writeFileSync('astrobwt_gen.cl', astrobwt);
+    fs.writeFileSync('astrobwt_cl.h', text2h(astrobwt, 'xmrig', 'astrobwt_cl'));
+}
+
+
+function kawpow()
+{
+    const kawpow = opencl_minify(addIncludes('kawpow.cl', [ 'defs.h' ]));
+    const kawpow_dag = opencl_minify(addIncludes('kawpow_dag.cl', [ 'defs.h' ]));
+
+    // fs.writeFileSync('kawpow_gen.cl', kawpow);
+    fs.writeFileSync('kawpow_cl.h', text2h(kawpow, 'xmrig', 'kawpow_cl'));
+    fs.writeFileSync('kawpow_dag_cl.h', text2h(kawpow_dag, 'xmrig', 'kawpow_dag_cl'));
+}
+
+
+process.chdir(path.resolve('src/backend/opencl/cl/cn'));
+
+cn();
+cn_r();
+
+process.chdir(cwd);
+process.chdir(path.resolve('src/backend/opencl/cl/rx'));
+
+rx();
+
+process.chdir(cwd);
+process.chdir(path.resolve('src/backend/opencl/cl/astrobwt'));
+
+astrobwt();
+
+process.chdir(cwd);
+process.chdir(path.resolve('src/backend/opencl/cl/kawpow'));
+
+kawpow();

scripts/js/opencl.js

@@ -0,0 +1,91 @@
+'use strict';
+
+const fs = require('fs');
+
+
+function bin2h(buf, namespace, name)
+{
+    const size = buf.byteLength;
+    let out    = `#pragma once\n\nnamespace ${namespace} {\n\nstatic const unsigned char ${name}[${size}] = {\n    `;
+
+    let b = 32;
+    for (let i = 0; i < size; i++) {
+        out += `0x${buf.readUInt8(i).toString(16).padStart(2, '0')}${size - i > 1 ? ',' : ''}`;
+
+        if (--b === 0) {
+            b = 32;
+            out += '\n    ';
+        }
+    }
+
+    out += `\n};\n\n} // namespace ${namespace}\n`;
+
+    return out;
+}
+
+
+function text2h_internal(text, name)
+{
+    const buf  = Buffer.from(text);
+    const size = buf.byteLength;
+    let out    = `\nstatic const char ${name}[${size + 1}] = {\n    `;
+
+    let b = 32;
+    for (let i = 0; i < size; i++) {
+        out += `0x${buf.readUInt8(i).toString(16).padStart(2, '0')},`;
+
+        if (--b === 0) {
+            b = 32;
+            out += '\n    ';
+        }
+    }
+
+    out += '0x00';
+
+    out += '\n};\n';
+
+    return out;
+}
+
+
+function text2h(text, namespace, name)
+{
+    return `#pragma once\n\nnamespace ${namespace} {\n` + text2h_internal(text, name) + `\n} // namespace ${namespace}\n`;
+}
+
+
+function text2h_bundle(namespace, items)
+{
+    let out = `#pragma once\n\nnamespace ${namespace} {\n`;
+
+    for (let key in items) {
+        out += text2h_internal(items[key], key);
+    }
+
+    return out + `\n} // namespace ${namespace}\n`;
+}
+
+
+function addInclude(input, name)
+{
+    return input.replace(`#include "${name}"`, fs.readFileSync(name, 'utf8'));
+}
+
+
+function addIncludes(inputFileName, names)
+{
+    let data = fs.readFileSync(inputFileName, 'utf8');
+
+    for (let name of names) {
+        data = addInclude(data, name);
+    }
+
+    return data;
+}
+
+
+module.exports.bin2h         = bin2h;
+module.exports.text2h        = text2h;
+module.exports.text2h_bundle = text2h_bundle;
+module.exports.addInclude    = addInclude;
+module.exports.addIncludes   = addIncludes;

scripts/js/opencl_minify.js

@@ -0,0 +1,51 @@
+'use strict';
+
+function opencl_minify(input)
+{
+    let out = input.replace(/\r/g, '');
+    out = out.replace(/\/\*[\s\S]*?\*\/|\/\/.*$/gm, ''); // comments
+    out = out.replace(/^#\s+/gm, '#');        // macros with spaces
+    out = out.replace(/\n{2,}/g, '\n');       // empty lines
+    out = out.replace(/^\s+/gm, '');          // leading whitespace
+    out = out.replace(/ {2,}/g, ' ');         // extra whitespace
+
+    let array = out.split('\n').map(line => {
+        if (line[0] === '#') {
+            return line;
+        }
+
+        line = line.replace(/, /g, ',');
+        line = line.replace(/ \? /g, '?');
+        line = line.replace(/ : /g, ':');
+        line = line.replace(/ = /g, '=');
+        line = line.replace(/ != /g, '!=');
+        line = line.replace(/ >= /g, '>=');
+        line = line.replace(/ <= /g, '<=');
+        line = line.replace(/ == /g, '==');
+        line = line.replace(/ \+= /g, '+=');
+        line = line.replace(/ -= /g, '-=');
+        line = line.replace(/ \|= /g, '|=');
+        line = line.replace(/ \| /g, '|');
+        line = line.replace(/ \|\| /g, '||');
+        line = line.replace(/ & /g, '&');
+        line = line.replace(/ && /g, '&&');
+        line = line.replace(/ > /g, '>');
+        line = line.replace(/ < /g, '<');
+        line = line.replace(/ \+ /g, '+');
+        line = line.replace(/ - /g, '-');
+        line = line.replace(/ \* /g, '*');
+        line = line.replace(/ \^ /g, '^');
+        line = line.replace(/ & /g, '&');
+        line = line.replace(/ \/ /g, '/');
+        line = line.replace(/ << /g, '<<');
+        line = line.replace(/ >> /g, '>>');
+        line = line.replace(/if \(/g, 'if(');
+
+        return line;
+    });
+
+    return array.join('\n');
+}
+
+
+module.exports.opencl_minify = opencl_minify;

scripts/randomx_boost.sh

@@ -0,0 +1,20 @@
+#!/bin/bash
+
+modprobe msr
+
+if cat /proc/cpuinfo | grep "AMD Ryzen" > /dev/null;
+	then
+		echo "Detected Ryzen"
+		wrmsr -a 0xc0011022 0x510000
+		wrmsr -a 0xc001102b 0x1808cc16
+		wrmsr -a 0xc0011020 0
+		wrmsr -a 0xc0011021 0x40
+		echo "MSR register values for Ryzen applied"
+elif cat /proc/cpuinfo | grep "Intel" > /dev/null;
+	then
+		echo "Detected Intel"
+		wrmsr -a 0x1a4 0xf
+		echo "MSR register values for Intel applied"
+else
+	echo "No supported CPU detected"
+fi

src/3rdparty/CL/LICENSE

@@ -0,0 +1,25 @@
+Copyright (c) 2008-2015 The Khronos Group Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining a
+copy of this software and/or associated documentation files (the
+"Materials"), to deal in the Materials without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Materials, and to
+permit persons to whom the Materials are furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice shall be included
+in all copies or substantial portions of the Materials.
+
+MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS
+KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS
+SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT
+   https://www.khronos.org/registry/
+
+THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.

src/3rdparty/CL/README.md

@@ -0,0 +1,50 @@
+# OpenCL<sup>TM</sup> API Headers
+
+This repository contains C language headers for the OpenCL API.
+
+The authoritative public repository for these headers is located at:
+
+https://github.com/KhronosGroup/OpenCL-Headers
+
+Issues, proposed fixes for issues, and other suggested changes should be
+created using Github.
+
+## Branch Structure
+
+The OpenCL API headers in this repository are Unified headers and are designed
+to work with all released OpenCL versions.  This differs from previous OpenCL
+API headers, where version-specific API headers either existed in separate
+branches, or in separate folders in a branch.
+
+## Compiling for a Specific OpenCL Version
+
+By default, the OpenCL API headers in this repository are for the latest
+OpenCL version (currently OpenCL 2.2).  To use these API headers to target
+a different OpenCL version, an application may `#define` the preprocessor
+value `CL_TARGET_OPENCL_VERSION` before including the OpenCL API headers.
+The `CL_TARGET_OPENCL_VERSION` is a three digit decimal value representing
+the OpenCL API version.
+
+For example, to enforce usage of no more than the OpenCL 1.2 APIs, you may
+include the OpenCL API headers as follows:
+
+```
+#define CL_TARGET_OPENCL_VERSION 120
+#include <CL/opencl.h>
+```
+
+## Directory Structure
+
+```
+README.md               This file
+LICENSE                 Source license for the OpenCL API headers
+CL/                     Unified OpenCL API headers tree
+```
+
+## License
+
+See [LICENSE](LICENSE).
+
+---
+
+OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.

src/3rdparty/CL/cl_d3d10.h

@@ -0,0 +1,131 @@
+/**********************************************************************************
+ * Copyright (c) 2008-2015 The Khronos Group Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and/or associated documentation files (the
+ * "Materials"), to deal in the Materials without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Materials, and to
+ * permit persons to whom the Materials are furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Materials.
+ *
+ * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS
+ * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS
+ * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT
+ *    https://www.khronos.org/registry/
+ *
+ * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
+ **********************************************************************************/
+
+/* $Revision: 11708 $ on $Date: 2010-06-13 23:36:24 -0700 (Sun, 13 Jun 2010) $ */
+
+#ifndef __OPENCL_CL_D3D10_H
+#define __OPENCL_CL_D3D10_H
+
+#include <d3d10.h>
+#include <CL/cl.h>
+#include <CL/cl_platform.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/******************************************************************************
+ * cl_khr_d3d10_sharing                                                       */
+#define cl_khr_d3d10_sharing 1
+
+typedef cl_uint cl_d3d10_device_source_khr;
+typedef cl_uint cl_d3d10_device_set_khr;
+
+/******************************************************************************/
+
+/* Error Codes */
+#define CL_INVALID_D3D10_DEVICE_KHR                  -1002
+#define CL_INVALID_D3D10_RESOURCE_KHR                -1003
+#define CL_D3D10_RESOURCE_ALREADY_ACQUIRED_KHR       -1004
+#define CL_D3D10_RESOURCE_NOT_ACQUIRED_KHR           -1005
+
+/* cl_d3d10_device_source_nv */
+#define CL_D3D10_DEVICE_KHR                          0x4010
+#define CL_D3D10_DXGI_ADAPTER_KHR                    0x4011
+
+/* cl_d3d10_device_set_nv */
+#define CL_PREFERRED_DEVICES_FOR_D3D10_KHR           0x4012
+#define CL_ALL_DEVICES_FOR_D3D10_KHR                 0x4013
+
+/* cl_context_info */
+#define CL_CONTEXT_D3D10_DEVICE_KHR                  0x4014
+#define CL_CONTEXT_D3D10_PREFER_SHARED_RESOURCES_KHR 0x402C
+
+/* cl_mem_info */
+#define CL_MEM_D3D10_RESOURCE_KHR                    0x4015
+
+/* cl_image_info */
+#define CL_IMAGE_D3D10_SUBRESOURCE_KHR               0x4016
+
+/* cl_command_type */
+#define CL_COMMAND_ACQUIRE_D3D10_OBJECTS_KHR         0x4017
+#define CL_COMMAND_RELEASE_D3D10_OBJECTS_KHR         0x4018
+
+/******************************************************************************/
+
+typedef CL_API_ENTRY cl_int (CL_API_CALL *clGetDeviceIDsFromD3D10KHR_fn)(
+    cl_platform_id             platform,
+    cl_d3d10_device_source_khr d3d_device_source,
+    void *                     d3d_object,
+    cl_d3d10_device_set_khr    d3d_device_set,
+    cl_uint                    num_entries,
+    cl_device_id *             devices,
+    cl_uint *                  num_devices) CL_API_SUFFIX__VERSION_1_0;
+
+typedef CL_API_ENTRY cl_mem (CL_API_CALL *clCreateFromD3D10BufferKHR_fn)(
+    cl_context     context,
+    cl_mem_flags   flags,
+    ID3D10Buffer * resource,
+    cl_int *       errcode_ret) CL_API_SUFFIX__VERSION_1_0;
+
+typedef CL_API_ENTRY cl_mem (CL_API_CALL *clCreateFromD3D10Texture2DKHR_fn)(
+    cl_context        context,
+    cl_mem_flags      flags,
+    ID3D10Texture2D * resource,
+    UINT              subresource,
+    cl_int *          errcode_ret) CL_API_SUFFIX__VERSION_1_0;
+
+typedef CL_API_ENTRY cl_mem (CL_API_CALL *clCreateFromD3D10Texture3DKHR_fn)(
+    cl_context        context,
+    cl_mem_flags      flags,
+    ID3D10Texture3D * resource,
+    UINT              subresource,
+    cl_int *          errcode_ret) CL_API_SUFFIX__VERSION_1_0;
+
+typedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueAcquireD3D10ObjectsKHR_fn)(
+    cl_command_queue command_queue,
+    cl_uint          num_objects,
+    const cl_mem *   mem_objects,
+    cl_uint          num_events_in_wait_list,
+    const cl_event * event_wait_list,
+    cl_event *       event) CL_API_SUFFIX__VERSION_1_0;
+
+typedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueReleaseD3D10ObjectsKHR_fn)(
+    cl_command_queue command_queue,
+    cl_uint          num_objects,
+    const cl_mem *   mem_objects,
+    cl_uint          num_events_in_wait_list,
+    const cl_event * event_wait_list,
+    cl_event *       event) CL_API_SUFFIX__VERSION_1_0;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __OPENCL_CL_D3D10_H */
+

src/3rdparty/CL/cl_d3d11.h

@@ -0,0 +1,131 @@
+/**********************************************************************************
+ * Copyright (c) 2008-2015 The Khronos Group Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and/or associated documentation files (the
+ * "Materials"), to deal in the Materials without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Materials, and to
+ * permit persons to whom the Materials are furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Materials.
+ *
+ * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS
+ * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS
+ * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT
+ *    https://www.khronos.org/registry/
+ *
+ * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
+ **********************************************************************************/
+
+/* $Revision: 11708 $ on $Date: 2010-06-13 23:36:24 -0700 (Sun, 13 Jun 2010) $ */
+
+#ifndef __OPENCL_CL_D3D11_H
+#define __OPENCL_CL_D3D11_H
+
+#include <d3d11.h>
+#include <CL/cl.h>
+#include <CL/cl_platform.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/******************************************************************************
+ * cl_khr_d3d11_sharing                                                       */
+#define cl_khr_d3d11_sharing 1
+
+typedef cl_uint cl_d3d11_device_source_khr;
+typedef cl_uint cl_d3d11_device_set_khr;
+
+/******************************************************************************/
+
+/* Error Codes */
+#define CL_INVALID_D3D11_DEVICE_KHR                  -1006
+#define CL_INVALID_D3D11_RESOURCE_KHR                -1007
+#define CL_D3D11_RESOURCE_ALREADY_ACQUIRED_KHR       -1008
+#define CL_D3D11_RESOURCE_NOT_ACQUIRED_KHR           -1009
+
+/* cl_d3d11_device_source */
+#define CL_D3D11_DEVICE_KHR                          0x4019
+#define CL_D3D11_DXGI_ADAPTER_KHR                    0x401A
+
+/* cl_d3d11_device_set */
+#define CL_PREFERRED_DEVICES_FOR_D3D11_KHR           0x401B
+#define CL_ALL_DEVICES_FOR_D3D11_KHR                 0x401C
+
+/* cl_context_info */
+#define CL_CONTEXT_D3D11_DEVICE_KHR                  0x401D
+#define CL_CONTEXT_D3D11_PREFER_SHARED_RESOURCES_KHR 0x402D
+
+/* cl_mem_info */
+#define CL_MEM_D3D11_RESOURCE_KHR                    0x401E
+
+/* cl_image_info */
+#define CL_IMAGE_D3D11_SUBRESOURCE_KHR               0x401F
+
+/* cl_command_type */
+#define CL_COMMAND_ACQUIRE_D3D11_OBJECTS_KHR         0x4020
+#define CL_COMMAND_RELEASE_D3D11_OBJECTS_KHR         0x4021
+
+/******************************************************************************/
+
+typedef CL_API_ENTRY cl_int (CL_API_CALL *clGetDeviceIDsFromD3D11KHR_fn)(
+    cl_platform_id             platform,
+    cl_d3d11_device_source_khr d3d_device_source,
+    void *                     d3d_object,
+    cl_d3d11_device_set_khr    d3d_device_set,
+    cl_uint                    num_entries,
+    cl_device_id *             devices,
+    cl_uint *                  num_devices) CL_API_SUFFIX__VERSION_1_2;
+
+typedef CL_API_ENTRY cl_mem (CL_API_CALL *clCreateFromD3D11BufferKHR_fn)(
+    cl_context     context,
+    cl_mem_flags   flags,
+    ID3D11Buffer * resource,
+    cl_int *       errcode_ret) CL_API_SUFFIX__VERSION_1_2;
+
+typedef CL_API_ENTRY cl_mem (CL_API_CALL *clCreateFromD3D11Texture2DKHR_fn)(
+    cl_context        context,
+    cl_mem_flags      flags,
+    ID3D11Texture2D * resource,
+    UINT              subresource,
+    cl_int *          errcode_ret) CL_API_SUFFIX__VERSION_1_2;
+
+typedef CL_API_ENTRY cl_mem (CL_API_CALL *clCreateFromD3D11Texture3DKHR_fn)(
+    cl_context        context,
+    cl_mem_flags      flags,
+    ID3D11Texture3D * resource,
+    UINT              subresource,
+    cl_int *          errcode_ret) CL_API_SUFFIX__VERSION_1_2;
+
+typedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueAcquireD3D11ObjectsKHR_fn)(
+    cl_command_queue command_queue,
+    cl_uint          num_objects,
+    const cl_mem *   mem_objects,
+    cl_uint          num_events_in_wait_list,
+    const cl_event * event_wait_list,
+    cl_event *       event) CL_API_SUFFIX__VERSION_1_2;
+
+typedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueReleaseD3D11ObjectsKHR_fn)(
+    cl_command_queue command_queue,
+    cl_uint          num_objects,
+    const cl_mem *   mem_objects,
+    cl_uint          num_events_in_wait_list,
+    const cl_event * event_wait_list,
+    cl_event *       event) CL_API_SUFFIX__VERSION_1_2;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __OPENCL_CL_D3D11_H */
+

src/3rdparty/CL/cl_dx9_media_sharing.h

@@ -0,0 +1,132 @@
+/**********************************************************************************
+ * Copyright (c) 2008-2015 The Khronos Group Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and/or associated documentation files (the
+ * "Materials"), to deal in the Materials without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Materials, and to
+ * permit persons to whom the Materials are furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Materials.
+ *
+ * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS
+ * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS
+ * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT
+ *    https://www.khronos.org/registry/
+ *
+ * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
+ **********************************************************************************/
+
+/* $Revision: 11708 $ on $Date: 2010-06-13 23:36:24 -0700 (Sun, 13 Jun 2010) $ */
+
+#ifndef __OPENCL_CL_DX9_MEDIA_SHARING_H
+#define __OPENCL_CL_DX9_MEDIA_SHARING_H
+
+#include <CL/cl.h>
+#include <CL/cl_platform.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/******************************************************************************/
+/* cl_khr_dx9_media_sharing                                                   */
+#define cl_khr_dx9_media_sharing 1
+
+typedef cl_uint             cl_dx9_media_adapter_type_khr;
+typedef cl_uint             cl_dx9_media_adapter_set_khr;
+    
+#if defined(_WIN32)
+#include <d3d9.h>
+typedef struct _cl_dx9_surface_info_khr
+{
+    IDirect3DSurface9 *resource;
+    HANDLE shared_handle;
+} cl_dx9_surface_info_khr;
+#endif
+
+
+/******************************************************************************/
+
+/* Error Codes */
+#define CL_INVALID_DX9_MEDIA_ADAPTER_KHR                -1010
+#define CL_INVALID_DX9_MEDIA_SURFACE_KHR                -1011
+#define CL_DX9_MEDIA_SURFACE_ALREADY_ACQUIRED_KHR       -1012
+#define CL_DX9_MEDIA_SURFACE_NOT_ACQUIRED_KHR           -1013
+
+/* cl_media_adapter_type_khr */
+#define CL_ADAPTER_D3D9_KHR                              0x2020
+#define CL_ADAPTER_D3D9EX_KHR                            0x2021
+#define CL_ADAPTER_DXVA_KHR                              0x2022
+
+/* cl_media_adapter_set_khr */
+#define CL_PREFERRED_DEVICES_FOR_DX9_MEDIA_ADAPTER_KHR   0x2023
+#define CL_ALL_DEVICES_FOR_DX9_MEDIA_ADAPTER_KHR         0x2024
+
+/* cl_context_info */
+#define CL_CONTEXT_ADAPTER_D3D9_KHR                      0x2025
+#define CL_CONTEXT_ADAPTER_D3D9EX_KHR                    0x2026
+#define CL_CONTEXT_ADAPTER_DXVA_KHR                      0x2027
+
+/* cl_mem_info */
+#define CL_MEM_DX9_MEDIA_ADAPTER_TYPE_KHR                0x2028
+#define CL_MEM_DX9_MEDIA_SURFACE_INFO_KHR                0x2029
+
+/* cl_image_info */
+#define CL_IMAGE_DX9_MEDIA_PLANE_KHR                     0x202A
+
+/* cl_command_type */
+#define CL_COMMAND_ACQUIRE_DX9_MEDIA_SURFACES_KHR        0x202B
+#define CL_COMMAND_RELEASE_DX9_MEDIA_SURFACES_KHR        0x202C
+
+/******************************************************************************/
+
+typedef CL_API_ENTRY cl_int (CL_API_CALL *clGetDeviceIDsFromDX9MediaAdapterKHR_fn)(
+    cl_platform_id                   platform,
+    cl_uint                          num_media_adapters,
+    cl_dx9_media_adapter_type_khr *  media_adapter_type,
+    void *                           media_adapters,
+    cl_dx9_media_adapter_set_khr     media_adapter_set,
+    cl_uint                          num_entries,
+    cl_device_id *                   devices,
+    cl_uint *                        num_devices) CL_API_SUFFIX__VERSION_1_2;
+
+typedef CL_API_ENTRY cl_mem (CL_API_CALL *clCreateFromDX9MediaSurfaceKHR_fn)(
+    cl_context                    context,
+    cl_mem_flags                  flags,
+    cl_dx9_media_adapter_type_khr adapter_type,
+    void *                        surface_info,
+    cl_uint                       plane,                                                                          
+    cl_int *                      errcode_ret) CL_API_SUFFIX__VERSION_1_2;
+
+typedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueAcquireDX9MediaSurfacesKHR_fn)(
+    cl_command_queue command_queue,
+    cl_uint          num_objects,
+    const cl_mem *   mem_objects,
+    cl_uint          num_events_in_wait_list,
+    const cl_event * event_wait_list,
+    cl_event *       event) CL_API_SUFFIX__VERSION_1_2;
+
+typedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueReleaseDX9MediaSurfacesKHR_fn)(
+    cl_command_queue command_queue,
+    cl_uint          num_objects,
+    const cl_mem *   mem_objects,
+    cl_uint          num_events_in_wait_list,
+    const cl_event * event_wait_list,
+    cl_event *       event) CL_API_SUFFIX__VERSION_1_2;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __OPENCL_CL_DX9_MEDIA_SHARING_H */
+

src/3rdparty/CL/cl_dx9_media_sharing_intel.h

@@ -0,0 +1,182 @@
+/**********************************************************************************
+ * Copyright (c) 2008-2019 The Khronos Group Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and/or associated documentation files (the
+ * "Materials"), to deal in the Materials without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Materials, and to
+ * permit persons to whom the Materials are furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Materials.
+ *
+ * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS
+ * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS
+ * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT
+ *    https://www.khronos.org/registry/
+ *
+ * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
+ **********************************************************************************/
+/*****************************************************************************\
+
+Copyright (c) 2013-2019 Intel Corporation All Rights Reserved.
+
+THESE MATERIALS ARE PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
+CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THESE
+MATERIALS, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+File Name: cl_dx9_media_sharing_intel.h
+
+Abstract:
+
+Notes:
+
+\*****************************************************************************/
+
+#ifndef __OPENCL_CL_DX9_MEDIA_SHARING_INTEL_H
+#define __OPENCL_CL_DX9_MEDIA_SHARING_INTEL_H
+
+#include <CL/cl.h>
+#include <CL/cl_platform.h>
+#include <d3d9.h>
+#include <dxvahd.h>
+#include <wtypes.h>
+#include <d3d9types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************
+* cl_intel_dx9_media_sharing extension *
+****************************************/
+
+#define cl_intel_dx9_media_sharing 1
+
+typedef cl_uint cl_dx9_device_source_intel;
+typedef cl_uint cl_dx9_device_set_intel;
+
+/* error codes */
+#define CL_INVALID_DX9_DEVICE_INTEL                   -1010
+#define CL_INVALID_DX9_RESOURCE_INTEL                 -1011
+#define CL_DX9_RESOURCE_ALREADY_ACQUIRED_INTEL        -1012
+#define CL_DX9_RESOURCE_NOT_ACQUIRED_INTEL            -1013
+
+/* cl_dx9_device_source_intel */
+#define CL_D3D9_DEVICE_INTEL                          0x4022
+#define CL_D3D9EX_DEVICE_INTEL                        0x4070
+#define CL_DXVA_DEVICE_INTEL                          0x4071
+
+/* cl_dx9_device_set_intel */
+#define CL_PREFERRED_DEVICES_FOR_DX9_INTEL            0x4024
+#define CL_ALL_DEVICES_FOR_DX9_INTEL                  0x4025
+
+/* cl_context_info */
+#define CL_CONTEXT_D3D9_DEVICE_INTEL                  0x4026
+#define CL_CONTEXT_D3D9EX_DEVICE_INTEL                0x4072
+#define CL_CONTEXT_DXVA_DEVICE_INTEL                  0x4073
+
+/* cl_mem_info */
+#define CL_MEM_DX9_RESOURCE_INTEL                     0x4027
+#define CL_MEM_DX9_SHARED_HANDLE_INTEL                0x4074
+
+/* cl_image_info */
+#define CL_IMAGE_DX9_PLANE_INTEL                      0x4075
+
+/* cl_command_type */
+#define CL_COMMAND_ACQUIRE_DX9_OBJECTS_INTEL          0x402A
+#define CL_COMMAND_RELEASE_DX9_OBJECTS_INTEL          0x402B
+/******************************************************************************/
+
+extern CL_API_ENTRY cl_int CL_API_CALL
+clGetDeviceIDsFromDX9INTEL(
+    cl_platform_id              platform,
+    cl_dx9_device_source_intel  dx9_device_source,
+    void*                       dx9_object,
+    cl_dx9_device_set_intel     dx9_device_set,
+    cl_uint                     num_entries,
+    cl_device_id*               devices,
+    cl_uint*                    num_devices) CL_EXT_SUFFIX__VERSION_1_1;
+
+typedef CL_API_ENTRY cl_int (CL_API_CALL* clGetDeviceIDsFromDX9INTEL_fn)(
+    cl_platform_id              platform,
+    cl_dx9_device_source_intel  dx9_device_source,
+    void*                       dx9_object,
+    cl_dx9_device_set_intel     dx9_device_set,
+    cl_uint                     num_entries,
+    cl_device_id*               devices,
+    cl_uint*                    num_devices) CL_EXT_SUFFIX__VERSION_1_1;
+
+extern CL_API_ENTRY cl_mem CL_API_CALL
+clCreateFromDX9MediaSurfaceINTEL(
+    cl_context                  context,
+    cl_mem_flags                flags,
+    IDirect3DSurface9*          resource,
+    HANDLE                      sharedHandle,
+    UINT                        plane,
+    cl_int*                     errcode_ret) CL_EXT_SUFFIX__VERSION_1_1;
+
+typedef CL_API_ENTRY cl_mem (CL_API_CALL *clCreateFromDX9MediaSurfaceINTEL_fn)(
+    cl_context                  context,
+    cl_mem_flags                flags,
+    IDirect3DSurface9*          resource,
+    HANDLE                      sharedHandle,
+    UINT                        plane,
+    cl_int*                     errcode_ret) CL_EXT_SUFFIX__VERSION_1_1;
+
+extern CL_API_ENTRY cl_int CL_API_CALL
+clEnqueueAcquireDX9ObjectsINTEL(
+    cl_command_queue            command_queue,
+    cl_uint                     num_objects,
+    const cl_mem*               mem_objects,
+    cl_uint                     num_events_in_wait_list,
+    const cl_event*             event_wait_list,
+    cl_event*                   event) CL_EXT_SUFFIX__VERSION_1_1;
+
+typedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueAcquireDX9ObjectsINTEL_fn)(
+    cl_command_queue            command_queue,
+    cl_uint                     num_objects,
+    const cl_mem*               mem_objects,
+    cl_uint                     num_events_in_wait_list,
+    const cl_event*             event_wait_list,
+    cl_event*                   event) CL_EXT_SUFFIX__VERSION_1_1;
+
+extern CL_API_ENTRY cl_int CL_API_CALL
+clEnqueueReleaseDX9ObjectsINTEL(
+    cl_command_queue            command_queue,
+    cl_uint                     num_objects,
+    cl_mem*                     mem_objects,
+    cl_uint                     num_events_in_wait_list,
+    const cl_event*             event_wait_list,
+    cl_event*                   event) CL_EXT_SUFFIX__VERSION_1_1;
+
+typedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueReleaseDX9ObjectsINTEL_fn)(
+    cl_command_queue            command_queue,
+    cl_uint                     num_objects,
+    cl_mem*                     mem_objects,
+    cl_uint                     num_events_in_wait_list,
+    const cl_event*             event_wait_list,
+    cl_event*                   event) CL_EXT_SUFFIX__VERSION_1_1;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __OPENCL_CL_DX9_MEDIA_SHARING_INTEL_H */
+

src/3rdparty/CL/cl_egl.h

@@ -0,0 +1,132 @@
+/*******************************************************************************
+ * Copyright (c) 2008-2019 The Khronos Group Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and/or associated documentation files (the
+ * "Materials"), to deal in the Materials without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Materials, and to
+ * permit persons to whom the Materials are furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Materials.
+ *
+ * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS
+ * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS
+ * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT
+ *    https://www.khronos.org/registry/
+ *
+ * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
+ ******************************************************************************/
+
+#ifndef __OPENCL_CL_EGL_H
+#define __OPENCL_CL_EGL_H
+
+#include <CL/cl.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Command type for events created with clEnqueueAcquireEGLObjectsKHR */
+#define CL_COMMAND_EGL_FENCE_SYNC_OBJECT_KHR  0x202F
+#define CL_COMMAND_ACQUIRE_EGL_OBJECTS_KHR    0x202D
+#define CL_COMMAND_RELEASE_EGL_OBJECTS_KHR    0x202E
+
+/* Error type for clCreateFromEGLImageKHR */
+#define CL_INVALID_EGL_OBJECT_KHR             -1093
+#define CL_EGL_RESOURCE_NOT_ACQUIRED_KHR      -1092
+
+/* CLeglImageKHR is an opaque handle to an EGLImage */
+typedef void* CLeglImageKHR;
+
+/* CLeglDisplayKHR is an opaque handle to an EGLDisplay */
+typedef void* CLeglDisplayKHR;
+
+/* CLeglSyncKHR is an opaque handle to an EGLSync object */
+typedef void* CLeglSyncKHR;
+
+/* properties passed to clCreateFromEGLImageKHR */
+typedef intptr_t cl_egl_image_properties_khr;
+
+
+#define cl_khr_egl_image 1
+
+extern CL_API_ENTRY cl_mem CL_API_CALL
+clCreateFromEGLImageKHR(cl_context                  context,
+                        CLeglDisplayKHR             egldisplay,
+                        CLeglImageKHR               eglimage,
+                        cl_mem_flags                flags,
+                        const cl_egl_image_properties_khr * properties,
+                        cl_int *                    errcode_ret) CL_API_SUFFIX__VERSION_1_0;
+
+typedef CL_API_ENTRY cl_mem (CL_API_CALL *clCreateFromEGLImageKHR_fn)(
+    cl_context                  context,
+    CLeglDisplayKHR             egldisplay,
+    CLeglImageKHR               eglimage,
+    cl_mem_flags                flags,
+    const cl_egl_image_properties_khr * properties,
+    cl_int *                    errcode_ret);
+
+
+extern CL_API_ENTRY cl_int CL_API_CALL
+clEnqueueAcquireEGLObjectsKHR(cl_command_queue command_queue,
+                              cl_uint          num_objects,
+                              const cl_mem *   mem_objects,
+                              cl_uint          num_events_in_wait_list,
+                              const cl_event * event_wait_list,
+                              cl_event *       event) CL_API_SUFFIX__VERSION_1_0;
+
+typedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueAcquireEGLObjectsKHR_fn)(
+    cl_command_queue command_queue,
+    cl_uint          num_objects,
+    const cl_mem *   mem_objects,
+    cl_uint          num_events_in_wait_list,
+    const cl_event * event_wait_list,
+    cl_event *       event);
+
+
+extern CL_API_ENTRY cl_int CL_API_CALL
+clEnqueueReleaseEGLObjectsKHR(cl_command_queue command_queue,
+                              cl_uint          num_objects,
+                              const cl_mem *   mem_objects,
+                              cl_uint          num_events_in_wait_list,
+                              const cl_event * event_wait_list,
+                              cl_event *       event) CL_API_SUFFIX__VERSION_1_0;
+
+typedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueReleaseEGLObjectsKHR_fn)(
+    cl_command_queue command_queue,
+    cl_uint          num_objects,
+    const cl_mem *   mem_objects,
+    cl_uint          num_events_in_wait_list,
+    const cl_event * event_wait_list,
+    cl_event *       event);
+
+
+#define cl_khr_egl_event 1
+
+extern CL_API_ENTRY cl_event CL_API_CALL
+clCreateEventFromEGLSyncKHR(cl_context      context,
+                            CLeglSyncKHR    sync,
+                            CLeglDisplayKHR display,
+                            cl_int *        errcode_ret) CL_API_SUFFIX__VERSION_1_0;
+
+typedef CL_API_ENTRY cl_event (CL_API_CALL *clCreateEventFromEGLSyncKHR_fn)(
+    cl_context      context,
+    CLeglSyncKHR    sync,
+    CLeglDisplayKHR display,
+    cl_int *        errcode_ret);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __OPENCL_CL_EGL_H */

src/3rdparty/CL/cl_ext.h

@@ -0,0 +1,762 @@
+/*******************************************************************************
+ * Copyright (c) 2008-2019 The Khronos Group Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and/or associated documentation files (the
+ * "Materials"), to deal in the Materials without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Materials, and to
+ * permit persons to whom the Materials are furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Materials.
+ *
+ * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS
+ * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS
+ * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT
+ *    https://www.khronos.org/registry/
+ *
+ * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
+ ******************************************************************************/
+
+/* cl_ext.h contains OpenCL extensions which don't have external */
+/* (OpenGL, D3D) dependencies.                                   */
+
+#ifndef __CL_EXT_H
+#define __CL_EXT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <CL/cl.h>
+
+/* cl_khr_fp64 extension - no extension #define since it has no functions  */
+/* CL_DEVICE_DOUBLE_FP_CONFIG is defined in CL.h for OpenCL >= 120 */
+
+#if CL_TARGET_OPENCL_VERSION <= 110
+#define CL_DEVICE_DOUBLE_FP_CONFIG                       0x1032
+#endif
+
+/* cl_khr_fp16 extension - no extension #define since it has no functions  */
+#define CL_DEVICE_HALF_FP_CONFIG                    0x1033
+
+/* Memory object destruction
+ *
+ * Apple extension for use to manage externally allocated buffers used with cl_mem objects with CL_MEM_USE_HOST_PTR
+ *
+ * Registers a user callback function that will be called when the memory object is deleted and its resources
+ * freed. Each call to clSetMemObjectCallbackFn registers the specified user callback function on a callback
+ * stack associated with memobj. The registered user callback functions are called in the reverse order in
+ * which they were registered. The user callback functions are called and then the memory object is deleted
+ * and its resources freed. This provides a mechanism for the application (and libraries) using memobj to be
+ * notified when the memory referenced by host_ptr, specified when the memory object is created and used as
+ * the storage bits for the memory object, can be reused or freed.
+ *
+ * The application may not call CL api's with the cl_mem object passed to the pfn_notify.
+ *
+ * Please check for the "cl_APPLE_SetMemObjectDestructor" extension using clGetDeviceInfo(CL_DEVICE_EXTENSIONS)
+ * before using.
+ */
+#define cl_APPLE_SetMemObjectDestructor 1
+cl_int  CL_API_ENTRY clSetMemObjectDestructorAPPLE(  cl_mem memobj,
+                                        void (* pfn_notify)(cl_mem memobj, void * user_data),
+                                        void * user_data)             CL_EXT_SUFFIX__VERSION_1_0;
+
+
+/* Context Logging Functions
+ *
+ * The next three convenience functions are intended to be used as the pfn_notify parameter to clCreateContext().
+ * Please check for the "cl_APPLE_ContextLoggingFunctions" extension using clGetDeviceInfo(CL_DEVICE_EXTENSIONS)
+ * before using.
+ *
+ * clLogMessagesToSystemLog forwards on all log messages to the Apple System Logger
+ */
+#define cl_APPLE_ContextLoggingFunctions 1
+extern void CL_API_ENTRY clLogMessagesToSystemLogAPPLE(  const char * errstr,
+                                            const void * private_info,
+                                            size_t       cb,
+                                            void *       user_data)  CL_EXT_SUFFIX__VERSION_1_0;
+
+/* clLogMessagesToStdout sends all log messages to the file descriptor stdout */
+extern void CL_API_ENTRY clLogMessagesToStdoutAPPLE(   const char * errstr,
+                                          const void * private_info,
+                                          size_t       cb,
+                                          void *       user_data)    CL_EXT_SUFFIX__VERSION_1_0;
+
+/* clLogMessagesToStderr sends all log messages to the file descriptor stderr */
+extern void CL_API_ENTRY clLogMessagesToStderrAPPLE(   const char * errstr,
+                                          const void * private_info,
+                                          size_t       cb,
+                                          void *       user_data)    CL_EXT_SUFFIX__VERSION_1_0;
+
+
+/************************
+* cl_khr_icd extension *
+************************/
+#define cl_khr_icd 1
+
+/* cl_platform_info                                                        */
+#define CL_PLATFORM_ICD_SUFFIX_KHR                  0x0920
+
+/* Additional Error Codes                                                  */
+#define CL_PLATFORM_NOT_FOUND_KHR                   -1001
+
+extern CL_API_ENTRY cl_int CL_API_CALL
+clIcdGetPlatformIDsKHR(cl_uint          num_entries,
+                       cl_platform_id * platforms,
+                       cl_uint *        num_platforms);
+
+typedef CL_API_ENTRY cl_int
+(CL_API_CALL *clIcdGetPlatformIDsKHR_fn)(cl_uint          num_entries,
+                                         cl_platform_id * platforms,
+                                         cl_uint *        num_platforms);
+
+
+/*******************************
+ * cl_khr_il_program extension *
+ *******************************/
+#define cl_khr_il_program 1
+
+/* New property to clGetDeviceInfo for retrieving supported intermediate
+ * languages
+ */
+#define CL_DEVICE_IL_VERSION_KHR                    0x105B
+
+/* New property to clGetProgramInfo for retrieving for retrieving the IL of a
+ * program
+ */
+#define CL_PROGRAM_IL_KHR                           0x1169
+
+extern CL_API_ENTRY cl_program CL_API_CALL
+clCreateProgramWithILKHR(cl_context   context,
+                         const void * il,
+                         size_t       length,
+                         cl_int *     errcode_ret);
+
+typedef CL_API_ENTRY cl_program
+(CL_API_CALL *clCreateProgramWithILKHR_fn)(cl_context   context,
+                                           const void * il,
+                                           size_t       length,
+                                           cl_int *     errcode_ret) CL_EXT_SUFFIX__VERSION_1_2;
+
+/* Extension: cl_khr_image2d_from_buffer
+ *
+ * This extension allows a 2D image to be created from a cl_mem buffer without
+ * a copy. The type associated with a 2D image created from a buffer in an
+ * OpenCL program is image2d_t. Both the sampler and sampler-less read_image
+ * built-in functions are supported for 2D images and 2D images created from
+ * a buffer.  Similarly, the write_image built-ins are also supported for 2D
+ * images created from a buffer.
+ *
+ * When the 2D image from buffer is created, the client must specify the
+ * width, height, image format (i.e. channel order and channel data type)
+ * and optionally the row pitch.
+ *
+ * The pitch specified must be a multiple of
+ * CL_DEVICE_IMAGE_PITCH_ALIGNMENT_KHR pixels.
+ * The base address of the buffer must be aligned to
+ * CL_DEVICE_IMAGE_BASE_ADDRESS_ALIGNMENT_KHR pixels.
+ */
+
+#define CL_DEVICE_IMAGE_PITCH_ALIGNMENT_KHR              0x104A
+#define CL_DEVICE_IMAGE_BASE_ADDRESS_ALIGNMENT_KHR       0x104B
+
+
+/**************************************
+ * cl_khr_initialize_memory extension *
+ **************************************/
+
+#define CL_CONTEXT_MEMORY_INITIALIZE_KHR            0x2030
+
+
+/**************************************
+ * cl_khr_terminate_context extension *
+ **************************************/
+
+#define CL_DEVICE_TERMINATE_CAPABILITY_KHR          0x2031
+#define CL_CONTEXT_TERMINATE_KHR                    0x2032
+
+#define cl_khr_terminate_context 1
+extern CL_API_ENTRY cl_int CL_API_CALL
+clTerminateContextKHR(cl_context context) CL_EXT_SUFFIX__VERSION_1_2;
+
+typedef CL_API_ENTRY cl_int
+(CL_API_CALL *clTerminateContextKHR_fn)(cl_context context) CL_EXT_SUFFIX__VERSION_1_2;
+
+
+/*
+ * Extension: cl_khr_spir
+ *
+ * This extension adds support to create an OpenCL program object from a
+ * Standard Portable Intermediate Representation (SPIR) instance
+ */
+
+#define CL_DEVICE_SPIR_VERSIONS                     0x40E0
+#define CL_PROGRAM_BINARY_TYPE_INTERMEDIATE         0x40E1
+
+
+/*****************************************
+ * cl_khr_create_command_queue extension *
+ *****************************************/
+#define cl_khr_create_command_queue 1
+
+typedef cl_bitfield cl_queue_properties_khr;
+
+extern CL_API_ENTRY cl_command_queue CL_API_CALL
+clCreateCommandQueueWithPropertiesKHR(cl_context context,
+                                      cl_device_id device,
+                                      const cl_queue_properties_khr* properties,
+                                      cl_int* errcode_ret) CL_EXT_SUFFIX__VERSION_1_2;
+
+typedef CL_API_ENTRY cl_command_queue
+(CL_API_CALL *clCreateCommandQueueWithPropertiesKHR_fn)(cl_context context,
+                                                        cl_device_id device,
+                                                        const cl_queue_properties_khr* properties,
+                                                        cl_int* errcode_ret) CL_EXT_SUFFIX__VERSION_1_2;
+
+
+/******************************************
+* cl_nv_device_attribute_query extension *
+******************************************/
+
+/* cl_nv_device_attribute_query extension - no extension #define since it has no functions */
+#define CL_DEVICE_COMPUTE_CAPABILITY_MAJOR_NV       0x4000
+#define CL_DEVICE_COMPUTE_CAPABILITY_MINOR_NV       0x4001
+#define CL_DEVICE_REGISTERS_PER_BLOCK_NV            0x4002
+#define CL_DEVICE_WARP_SIZE_NV                      0x4003
+#define CL_DEVICE_GPU_OVERLAP_NV                    0x4004
+#define CL_DEVICE_KERNEL_EXEC_TIMEOUT_NV            0x4005
+#define CL_DEVICE_INTEGRATED_MEMORY_NV              0x4006
+
+
+/*********************************
+* cl_amd_device_attribute_query *
+*********************************/
+
+#define CL_DEVICE_PROFILING_TIMER_OFFSET_AMD        0x4036
+
+
+/*********************************
+* cl_arm_printf extension
+*********************************/
+
+#define CL_PRINTF_CALLBACK_ARM                      0x40B0
+#define CL_PRINTF_BUFFERSIZE_ARM                    0x40B1
+
+
+/***********************************
+* cl_ext_device_fission extension
+***********************************/
+#define cl_ext_device_fission   1
+
+extern CL_API_ENTRY cl_int CL_API_CALL
+clReleaseDeviceEXT(cl_device_id device) CL_EXT_SUFFIX__VERSION_1_1;
+
+typedef CL_API_ENTRY cl_int
+(CL_API_CALL *clReleaseDeviceEXT_fn)(cl_device_id device) CL_EXT_SUFFIX__VERSION_1_1;
+
+extern CL_API_ENTRY cl_int CL_API_CALL
+clRetainDeviceEXT(cl_device_id device) CL_EXT_SUFFIX__VERSION_1_1;
+
+typedef CL_API_ENTRY cl_int
+(CL_API_CALL *clRetainDeviceEXT_fn)(cl_device_id device) CL_EXT_SUFFIX__VERSION_1_1;
+
+typedef cl_ulong  cl_device_partition_property_ext;
+extern CL_API_ENTRY cl_int CL_API_CALL
+clCreateSubDevicesEXT(cl_device_id   in_device,
+                      const cl_device_partition_property_ext * properties,
+                      cl_uint        num_entries,
+                      cl_device_id * out_devices,
+                      cl_uint *      num_devices) CL_EXT_SUFFIX__VERSION_1_1;
+
+typedef CL_API_ENTRY cl_int
+(CL_API_CALL * clCreateSubDevicesEXT_fn)(cl_device_id   in_device,
+                                         const cl_device_partition_property_ext * properties,
+                                         cl_uint        num_entries,
+                                         cl_device_id * out_devices,
+                                         cl_uint *      num_devices) CL_EXT_SUFFIX__VERSION_1_1;
+
+/* cl_device_partition_property_ext */
+#define CL_DEVICE_PARTITION_EQUALLY_EXT             0x4050
+#define CL_DEVICE_PARTITION_BY_COUNTS_EXT           0x4051
+#define CL_DEVICE_PARTITION_BY_NAMES_EXT            0x4052
+#define CL_DEVICE_PARTITION_BY_AFFINITY_DOMAIN_EXT  0x4053
+
+/* clDeviceGetInfo selectors */
+#define CL_DEVICE_PARENT_DEVICE_EXT                 0x4054
+#define CL_DEVICE_PARTITION_TYPES_EXT               0x4055
+#define CL_DEVICE_AFFINITY_DOMAINS_EXT              0x4056
+#define CL_DEVICE_REFERENCE_COUNT_EXT               0x4057
+#define CL_DEVICE_PARTITION_STYLE_EXT               0x4058
+
+/* error codes */
+#define CL_DEVICE_PARTITION_FAILED_EXT              -1057
+#define CL_INVALID_PARTITION_COUNT_EXT              -1058
+#define CL_INVALID_PARTITION_NAME_EXT               -1059
+
+/* CL_AFFINITY_DOMAINs */
+#define CL_AFFINITY_DOMAIN_L1_CACHE_EXT             0x1
+#define CL_AFFINITY_DOMAIN_L2_CACHE_EXT             0x2
+#define CL_AFFINITY_DOMAIN_L3_CACHE_EXT             0x3
+#define CL_AFFINITY_DOMAIN_L4_CACHE_EXT             0x4
+#define CL_AFFINITY_DOMAIN_NUMA_EXT                 0x10
+#define CL_AFFINITY_DOMAIN_NEXT_FISSIONABLE_EXT     0x100
+
+/* cl_device_partition_property_ext list terminators */
+#define CL_PROPERTIES_LIST_END_EXT                  ((cl_device_partition_property_ext) 0)
+#define CL_PARTITION_BY_COUNTS_LIST_END_EXT         ((cl_device_partition_property_ext) 0)
+#define CL_PARTITION_BY_NAMES_LIST_END_EXT          ((cl_device_partition_property_ext) 0 - 1)
+
+
+/***********************************
+ * cl_ext_migrate_memobject extension definitions
+ ***********************************/
+#define cl_ext_migrate_memobject 1
+
+typedef cl_bitfield cl_mem_migration_flags_ext;
+
+#define CL_MIGRATE_MEM_OBJECT_HOST_EXT              0x1
+
+#define CL_COMMAND_MIGRATE_MEM_OBJECT_EXT           0x4040
+
+extern CL_API_ENTRY cl_int CL_API_CALL
+clEnqueueMigrateMemObjectEXT(cl_command_queue command_queue,
+                             cl_uint          num_mem_objects,
+                             const cl_mem *   mem_objects,
+                             cl_mem_migration_flags_ext flags,
+                             cl_uint          num_events_in_wait_list,
+                             const cl_event * event_wait_list,
+                             cl_event *       event);
+
+typedef CL_API_ENTRY cl_int
+(CL_API_CALL *clEnqueueMigrateMemObjectEXT_fn)(cl_command_queue command_queue,
+                                               cl_uint          num_mem_objects,
+                                               const cl_mem *   mem_objects,
+                                               cl_mem_migration_flags_ext flags,
+                                               cl_uint          num_events_in_wait_list,
+                                               const cl_event * event_wait_list,
+                                               cl_event *       event);
+
+
+/*********************************
+* cl_qcom_ext_host_ptr extension
+*********************************/
+#define cl_qcom_ext_host_ptr 1
+
+#define CL_MEM_EXT_HOST_PTR_QCOM                  (1 << 29)
+
+#define CL_DEVICE_EXT_MEM_PADDING_IN_BYTES_QCOM   0x40A0
+#define CL_DEVICE_PAGE_SIZE_QCOM                  0x40A1
+#define CL_IMAGE_ROW_ALIGNMENT_QCOM               0x40A2
+#define CL_IMAGE_SLICE_ALIGNMENT_QCOM             0x40A3
+#define CL_MEM_HOST_UNCACHED_QCOM                 0x40A4
+#define CL_MEM_HOST_WRITEBACK_QCOM                0x40A5
+#define CL_MEM_HOST_WRITETHROUGH_QCOM             0x40A6
+#define CL_MEM_HOST_WRITE_COMBINING_QCOM          0x40A7
+
+typedef cl_uint                                   cl_image_pitch_info_qcom;
+
+extern CL_API_ENTRY cl_int CL_API_CALL
+clGetDeviceImageInfoQCOM(cl_device_id             device,
+                         size_t                   image_width,
+                         size_t                   image_height,
+                         const cl_image_format   *image_format,
+                         cl_image_pitch_info_qcom param_name,
+                         size_t                   param_value_size,
+                         void                    *param_value,
+                         size_t                  *param_value_size_ret);
+
+typedef struct _cl_mem_ext_host_ptr
+{
+    /* Type of external memory allocation. */
+    /* Legal values will be defined in layered extensions. */
+    cl_uint  allocation_type;
+
+    /* Host cache policy for this external memory allocation. */
+    cl_uint  host_cache_policy;
+
+} cl_mem_ext_host_ptr;
+
+
+/*******************************************
+* cl_qcom_ext_host_ptr_iocoherent extension
+********************************************/
+
+/* Cache policy specifying io-coherence */
+#define CL_MEM_HOST_IOCOHERENT_QCOM               0x40A9
+
+
+/*********************************
+* cl_qcom_ion_host_ptr extension
+*********************************/
+
+#define CL_MEM_ION_HOST_PTR_QCOM                  0x40A8
+
+typedef struct _cl_mem_ion_host_ptr
+{
+    /* Type of external memory allocation. */
+    /* Must be CL_MEM_ION_HOST_PTR_QCOM for ION allocations. */
+    cl_mem_ext_host_ptr  ext_host_ptr;
+
+    /* ION file descriptor */
+    int                  ion_filedesc;
+
+    /* Host pointer to the ION allocated memory */
+    void*                ion_hostptr;
+
+} cl_mem_ion_host_ptr;
+
+
+/*********************************
+* cl_qcom_android_native_buffer_host_ptr extension
+*********************************/
+
+#define CL_MEM_ANDROID_NATIVE_BUFFER_HOST_PTR_QCOM                  0x40C6
+
+typedef struct _cl_mem_android_native_buffer_host_ptr
+{
+    /* Type of external memory allocation. */
+    /* Must be CL_MEM_ANDROID_NATIVE_BUFFER_HOST_PTR_QCOM for Android native buffers. */
+    cl_mem_ext_host_ptr  ext_host_ptr;
+
+    /* Virtual pointer to the android native buffer */
+    void*                anb_ptr;
+
+} cl_mem_android_native_buffer_host_ptr;
+
+
+/******************************************
+ * cl_img_yuv_image extension *
+ ******************************************/
+
+/* Image formats used in clCreateImage */
+#define CL_NV21_IMG                                 0x40D0
+#define CL_YV12_IMG                                 0x40D1
+
+
+/******************************************
+ * cl_img_cached_allocations extension *
+ ******************************************/
+
+/* Flag values used by clCreateBuffer */
+#define CL_MEM_USE_UNCACHED_CPU_MEMORY_IMG          (1 << 26)
+#define CL_MEM_USE_CACHED_CPU_MEMORY_IMG            (1 << 27)
+
+
+/******************************************
+ * cl_img_use_gralloc_ptr extension *
+ ******************************************/
+#define cl_img_use_gralloc_ptr 1
+
+/* Flag values used by clCreateBuffer */
+#define CL_MEM_USE_GRALLOC_PTR_IMG                  (1 << 28)
+
+/* To be used by clGetEventInfo: */
+#define CL_COMMAND_ACQUIRE_GRALLOC_OBJECTS_IMG      0x40D2
+#define CL_COMMAND_RELEASE_GRALLOC_OBJECTS_IMG      0x40D3
+
+/* Error code from clEnqueueReleaseGrallocObjectsIMG */
+#define CL_GRALLOC_RESOURCE_NOT_ACQUIRED_IMG        0x40D4
+
+extern CL_API_ENTRY cl_int CL_API_CALL
+clEnqueueAcquireGrallocObjectsIMG(cl_command_queue      command_queue,
+                                  cl_uint               num_objects,
+                                  const cl_mem *        mem_objects,
+                                  cl_uint               num_events_in_wait_list,
+                                  const cl_event *      event_wait_list,
+                                  cl_event *            event) CL_EXT_SUFFIX__VERSION_1_2;
+
+extern CL_API_ENTRY cl_int CL_API_CALL
+clEnqueueReleaseGrallocObjectsIMG(cl_command_queue      command_queue,
+                                  cl_uint               num_objects,
+                                  const cl_mem *        mem_objects,
+                                  cl_uint               num_events_in_wait_list,
+                                  const cl_event *      event_wait_list,
+                                  cl_event *            event) CL_EXT_SUFFIX__VERSION_1_2;
+
+
+/*********************************
+* cl_khr_subgroups extension
+*********************************/
+#define cl_khr_subgroups 1
+
+#if !defined(CL_VERSION_2_1)
+/* For OpenCL 2.1 and newer, cl_kernel_sub_group_info is declared in CL.h.
+   In hindsight, there should have been a khr suffix on this type for
+   the extension, but keeping it un-suffixed to maintain backwards
+   compatibility. */
+typedef cl_uint             cl_kernel_sub_group_info;
+#endif
+
+/* cl_kernel_sub_group_info */
+#define CL_KERNEL_MAX_SUB_GROUP_SIZE_FOR_NDRANGE_KHR    0x2033
+#define CL_KERNEL_SUB_GROUP_COUNT_FOR_NDRANGE_KHR       0x2034
+
+extern CL_API_ENTRY cl_int CL_API_CALL
+clGetKernelSubGroupInfoKHR(cl_kernel    in_kernel,
+                           cl_device_id in_device,
+                           cl_kernel_sub_group_info param_name,
+                           size_t       input_value_size,
+                           const void * input_value,
+                           size_t       param_value_size,
+                           void *       param_value,
+                           size_t *     param_value_size_ret) CL_EXT_SUFFIX__VERSION_2_0_DEPRECATED;
+
+typedef CL_API_ENTRY cl_int
+(CL_API_CALL * clGetKernelSubGroupInfoKHR_fn)(cl_kernel    in_kernel,
+                                              cl_device_id in_device,
+                                              cl_kernel_sub_group_info param_name,
+                                              size_t       input_value_size,
+                                              const void * input_value,
+                                              size_t       param_value_size,
+                                              void *       param_value,
+                                              size_t *     param_value_size_ret) CL_EXT_SUFFIX__VERSION_2_0_DEPRECATED;
+
+
+/*********************************
+* cl_khr_mipmap_image extension
+*********************************/
+
+/* cl_sampler_properties */
+#define CL_SAMPLER_MIP_FILTER_MODE_KHR              0x1155
+#define CL_SAMPLER_LOD_MIN_KHR                      0x1156
+#define CL_SAMPLER_LOD_MAX_KHR                      0x1157
+
+
+/*********************************
+* cl_khr_priority_hints extension
+*********************************/
+/* This extension define is for backwards compatibility.
+   It shouldn't be required since this extension has no new functions. */
+#define cl_khr_priority_hints 1
+
+typedef cl_uint  cl_queue_priority_khr;
+
+/* cl_command_queue_properties */
+#define CL_QUEUE_PRIORITY_KHR 0x1096
+
+/* cl_queue_priority_khr */
+#define CL_QUEUE_PRIORITY_HIGH_KHR (1<<0)
+#define CL_QUEUE_PRIORITY_MED_KHR (1<<1)
+#define CL_QUEUE_PRIORITY_LOW_KHR (1<<2)
+
+
+/*********************************
+* cl_khr_throttle_hints extension
+*********************************/
+/* This extension define is for backwards compatibility.
+   It shouldn't be required since this extension has no new functions. */
+#define cl_khr_throttle_hints 1
+
+typedef cl_uint  cl_queue_throttle_khr;
+
+/* cl_command_queue_properties */
+#define CL_QUEUE_THROTTLE_KHR 0x1097
+
+/* cl_queue_throttle_khr */
+#define CL_QUEUE_THROTTLE_HIGH_KHR (1<<0)
+#define CL_QUEUE_THROTTLE_MED_KHR (1<<1)
+#define CL_QUEUE_THROTTLE_LOW_KHR (1<<2)
+
+
+/*********************************
+* cl_khr_subgroup_named_barrier
+*********************************/
+/* This extension define is for backwards compatibility.
+   It shouldn't be required since this extension has no new functions. */
+#define cl_khr_subgroup_named_barrier 1
+
+/* cl_device_info */
+#define CL_DEVICE_MAX_NAMED_BARRIER_COUNT_KHR       0x2035
+
+
+/**********************************
+ * cl_arm_import_memory extension *
+ **********************************/
+#define cl_arm_import_memory 1
+
+typedef intptr_t cl_import_properties_arm;
+
+/* Default and valid proporties name for cl_arm_import_memory */
+#define CL_IMPORT_TYPE_ARM                        0x40B2
+
+/* Host process memory type default value for CL_IMPORT_TYPE_ARM property */
+#define CL_IMPORT_TYPE_HOST_ARM                   0x40B3
+
+/* DMA BUF memory type value for CL_IMPORT_TYPE_ARM property */
+#define CL_IMPORT_TYPE_DMA_BUF_ARM                0x40B4
+
+/* Protected DMA BUF memory type value for CL_IMPORT_TYPE_ARM property */
+#define CL_IMPORT_TYPE_PROTECTED_ARM              0x40B5
+
+/* This extension adds a new function that allows for direct memory import into
+ * OpenCL via the clImportMemoryARM function.
+ *
+ * Memory imported through this interface will be mapped into the device's page
+ * tables directly, providing zero copy access. It will never fall back to copy
+ * operations and aliased buffers.
+ *
+ * Types of memory supported for import are specified as additional extension
+ * strings.
+ *
+ * This extension produces cl_mem allocations which are compatible with all other
+ * users of cl_mem in the standard API.
+ *
+ * This extension maps pages with the same properties as the normal buffer creation
+ * function clCreateBuffer.
+ */
+extern CL_API_ENTRY cl_mem CL_API_CALL
+clImportMemoryARM( cl_context context,
+                   cl_mem_flags flags,
+                   const cl_import_properties_arm *properties,
+                   void *memory,
+                   size_t size,
+                   cl_int *errcode_ret) CL_EXT_SUFFIX__VERSION_1_0;
+
+
+/******************************************
+ * cl_arm_shared_virtual_memory extension *
+ ******************************************/
+#define cl_arm_shared_virtual_memory 1
+
+/* Used by clGetDeviceInfo */
+#define CL_DEVICE_SVM_CAPABILITIES_ARM                  0x40B6
+
+/* Used by clGetMemObjectInfo */
+#define CL_MEM_USES_SVM_POINTER_ARM                     0x40B7
+
+/* Used by clSetKernelExecInfoARM: */
+#define CL_KERNEL_EXEC_INFO_SVM_PTRS_ARM                0x40B8
+#define CL_KERNEL_EXEC_INFO_SVM_FINE_GRAIN_SYSTEM_ARM   0x40B9
+
+/* To be used by clGetEventInfo: */
+#define CL_COMMAND_SVM_FREE_ARM                         0x40BA
+#define CL_COMMAND_SVM_MEMCPY_ARM                       0x40BB
+#define CL_COMMAND_SVM_MEMFILL_ARM                      0x40BC
+#define CL_COMMAND_SVM_MAP_ARM                          0x40BD
+#define CL_COMMAND_SVM_UNMAP_ARM                        0x40BE
+
+/* Flag values returned by clGetDeviceInfo with CL_DEVICE_SVM_CAPABILITIES_ARM as the param_name. */
+#define CL_DEVICE_SVM_COARSE_GRAIN_BUFFER_ARM           (1 << 0)
+#define CL_DEVICE_SVM_FINE_GRAIN_BUFFER_ARM             (1 << 1)
+#define CL_DEVICE_SVM_FINE_GRAIN_SYSTEM_ARM             (1 << 2)
+#define CL_DEVICE_SVM_ATOMICS_ARM                       (1 << 3)
+
+/* Flag values used by clSVMAllocARM: */
+#define CL_MEM_SVM_FINE_GRAIN_BUFFER_ARM                (1 << 10)
+#define CL_MEM_SVM_ATOMICS_ARM                          (1 << 11)
+
+typedef cl_bitfield cl_svm_mem_flags_arm;
+typedef cl_uint     cl_kernel_exec_info_arm;
+typedef cl_bitfield cl_device_svm_capabilities_arm;
+
+extern CL_API_ENTRY void * CL_API_CALL
+clSVMAllocARM(cl_context       context,
+              cl_svm_mem_flags_arm flags,
+              size_t           size,
+              cl_uint          alignment) CL_EXT_SUFFIX__VERSION_1_2;
+
+extern CL_API_ENTRY void CL_API_CALL
+clSVMFreeARM(cl_context        context,
+             void *            svm_pointer) CL_EXT_SUFFIX__VERSION_1_2;
+
+extern CL_API_ENTRY cl_int CL_API_CALL
+clEnqueueSVMFreeARM(cl_command_queue  command_queue,
+                    cl_uint           num_svm_pointers,
+                    void *            svm_pointers[],
+                    void (CL_CALLBACK * pfn_free_func)(cl_command_queue queue,
+                                                       cl_uint          num_svm_pointers,
+                                                       void *           svm_pointers[],
+                                                       void *           user_data),
+                    void *            user_data,
+                    cl_uint           num_events_in_wait_list,
+                    const cl_event *  event_wait_list,
+                    cl_event *        event) CL_EXT_SUFFIX__VERSION_1_2;
+
+extern CL_API_ENTRY cl_int CL_API_CALL
+clEnqueueSVMMemcpyARM(cl_command_queue  command_queue,
+                      cl_bool           blocking_copy,
+                      void *            dst_ptr,
+                      const void *      src_ptr,
+                      size_t            size,
+                      cl_uint           num_events_in_wait_list,
+                      const cl_event *  event_wait_list,
+                      cl_event *        event) CL_EXT_SUFFIX__VERSION_1_2;
+
+extern CL_API_ENTRY cl_int CL_API_CALL
+clEnqueueSVMMemFillARM(cl_command_queue  command_queue,
+                       void *            svm_ptr,
+                       const void *      pattern,
+                       size_t            pattern_size,
+                       size_t            size,
+                       cl_uint           num_events_in_wait_list,
+                       const cl_event *  event_wait_list,
+                       cl_event *        event) CL_EXT_SUFFIX__VERSION_1_2;
+
+extern CL_API_ENTRY cl_int CL_API_CALL
+clEnqueueSVMMapARM(cl_command_queue  command_queue,
+                   cl_bool           blocking_map,
+                   cl_map_flags      flags,
+                   void *            svm_ptr,
+                   size_t            size,
+                   cl_uint           num_events_in_wait_list,
+                   const cl_event *  event_wait_list,
+                   cl_event *        event) CL_EXT_SUFFIX__VERSION_1_2;
+
+extern CL_API_ENTRY cl_int CL_API_CALL
+clEnqueueSVMUnmapARM(cl_command_queue  command_queue,
+                     void *            svm_ptr,
+                     cl_uint           num_events_in_wait_list,
+                     const cl_event *  event_wait_list,
+                     cl_event *        event) CL_EXT_SUFFIX__VERSION_1_2;
+
+extern CL_API_ENTRY cl_int CL_API_CALL
+clSetKernelArgSVMPointerARM(cl_kernel    kernel,
+                            cl_uint      arg_index,
+                            const void * arg_value) CL_EXT_SUFFIX__VERSION_1_2;
+
+extern CL_API_ENTRY cl_int CL_API_CALL
+clSetKernelExecInfoARM(cl_kernel            kernel,
+                       cl_kernel_exec_info_arm  param_name,
+                       size_t               param_value_size,
+                       const void *         param_value) CL_EXT_SUFFIX__VERSION_1_2;
+
+/********************************
+ * cl_arm_get_core_id extension *
+ ********************************/
+
+#ifdef CL_VERSION_1_2
+
+#define cl_arm_get_core_id 1
+
+/* Device info property for bitfield of cores present */
+#define CL_DEVICE_COMPUTE_UNITS_BITFIELD_ARM      0x40BF
+
+#endif  /* CL_VERSION_1_2 */
+
+/*********************************
+* cl_arm_job_slot_selection
+*********************************/
+
+#define cl_arm_job_slot_selection 1
+
+/* cl_device_info */
+#define CL_DEVICE_JOB_SLOTS_ARM                   0x41E0
+
+/* cl_command_queue_properties */
+#define CL_QUEUE_JOB_SLOT_ARM                     0x41E1
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __CL_EXT_H */

src/3rdparty/CL/cl_ext_intel.h

@@ -0,0 +1,423 @@
+/*******************************************************************************
+ * Copyright (c) 2008-2019 The Khronos Group Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and/or associated documentation files (the
+ * "Materials"), to deal in the Materials without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Materials, and to
+ * permit persons to whom the Materials are furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Materials.
+ *
+ * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS
+ * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS
+ * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT
+ *    https://www.khronos.org/registry/
+ *
+ * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
+ ******************************************************************************/
+/*****************************************************************************\
+
+Copyright (c) 2013-2019 Intel Corporation All Rights Reserved.
+
+THESE MATERIALS ARE PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
+CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THESE
+MATERIALS, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+File Name: cl_ext_intel.h
+
+Abstract:
+
+Notes:
+
+\*****************************************************************************/
+
+#ifndef __CL_EXT_INTEL_H
+#define __CL_EXT_INTEL_H
+
+#include <CL/cl.h>
+#include <CL/cl_platform.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************
+* cl_intel_thread_local_exec extension *
+****************************************/
+
+#define cl_intel_thread_local_exec 1
+
+#define CL_QUEUE_THREAD_LOCAL_EXEC_ENABLE_INTEL      (((cl_bitfield)1) << 31)
+
+/***********************************************
+* cl_intel_device_partition_by_names extension *
+************************************************/
+
+#define cl_intel_device_partition_by_names 1
+
+#define CL_DEVICE_PARTITION_BY_NAMES_INTEL          0x4052
+#define CL_PARTITION_BY_NAMES_LIST_END_INTEL        -1
+
+/************************************************
+* cl_intel_accelerator extension                *
+* cl_intel_motion_estimation extension          *
+* cl_intel_advanced_motion_estimation extension *
+*************************************************/
+
+#define cl_intel_accelerator 1
+#define cl_intel_motion_estimation 1
+#define cl_intel_advanced_motion_estimation 1
+
+typedef struct _cl_accelerator_intel* cl_accelerator_intel;
+typedef cl_uint cl_accelerator_type_intel;
+typedef cl_uint cl_accelerator_info_intel;
+
+typedef struct _cl_motion_estimation_desc_intel {
+    cl_uint mb_block_type;
+    cl_uint subpixel_mode;
+    cl_uint sad_adjust_mode;
+    cl_uint search_path_type;
+} cl_motion_estimation_desc_intel;
+
+/* error codes */
+#define CL_INVALID_ACCELERATOR_INTEL                              -1094
+#define CL_INVALID_ACCELERATOR_TYPE_INTEL                         -1095
+#define CL_INVALID_ACCELERATOR_DESCRIPTOR_INTEL                   -1096
+#define CL_ACCELERATOR_TYPE_NOT_SUPPORTED_INTEL                   -1097
+
+/* cl_accelerator_type_intel */
+#define CL_ACCELERATOR_TYPE_MOTION_ESTIMATION_INTEL               0x0
+
+/* cl_accelerator_info_intel */
+#define CL_ACCELERATOR_DESCRIPTOR_INTEL                           0x4090
+#define CL_ACCELERATOR_REFERENCE_COUNT_INTEL                      0x4091
+#define CL_ACCELERATOR_CONTEXT_INTEL                              0x4092
+#define CL_ACCELERATOR_TYPE_INTEL                                 0x4093
+
+/* cl_motion_detect_desc_intel flags */
+#define CL_ME_MB_TYPE_16x16_INTEL                                 0x0
+#define CL_ME_MB_TYPE_8x8_INTEL                                   0x1
+#define CL_ME_MB_TYPE_4x4_INTEL                                   0x2
+
+#define CL_ME_SUBPIXEL_MODE_INTEGER_INTEL                         0x0
+#define CL_ME_SUBPIXEL_MODE_HPEL_INTEL                            0x1
+#define CL_ME_SUBPIXEL_MODE_QPEL_INTEL                            0x2
+
+#define CL_ME_SAD_ADJUST_MODE_NONE_INTEL                          0x0
+#define CL_ME_SAD_ADJUST_MODE_HAAR_INTEL                          0x1
+
+#define CL_ME_SEARCH_PATH_RADIUS_2_2_INTEL                        0x0
+#define CL_ME_SEARCH_PATH_RADIUS_4_4_INTEL                        0x1
+#define CL_ME_SEARCH_PATH_RADIUS_16_12_INTEL                      0x5
+
+#define CL_ME_SKIP_BLOCK_TYPE_16x16_INTEL                         0x0
+#define CL_ME_CHROMA_INTRA_PREDICT_ENABLED_INTEL                  0x1
+#define CL_ME_LUMA_INTRA_PREDICT_ENABLED_INTEL                    0x2
+#define CL_ME_SKIP_BLOCK_TYPE_8x8_INTEL                           0x4
+
+#define CL_ME_FORWARD_INPUT_MODE_INTEL                            0x1
+#define CL_ME_BACKWARD_INPUT_MODE_INTEL                           0x2
+#define CL_ME_BIDIRECTION_INPUT_MODE_INTEL                        0x3
+
+#define CL_ME_BIDIR_WEIGHT_QUARTER_INTEL                          16
+#define CL_ME_BIDIR_WEIGHT_THIRD_INTEL                            21
+#define CL_ME_BIDIR_WEIGHT_HALF_INTEL                             32
+#define CL_ME_BIDIR_WEIGHT_TWO_THIRD_INTEL                        43
+#define CL_ME_BIDIR_WEIGHT_THREE_QUARTER_INTEL                    48
+
+#define CL_ME_COST_PENALTY_NONE_INTEL                             0x0
+#define CL_ME_COST_PENALTY_LOW_INTEL                              0x1
+#define CL_ME_COST_PENALTY_NORMAL_INTEL                           0x2
+#define CL_ME_COST_PENALTY_HIGH_INTEL                             0x3
+
+#define CL_ME_COST_PRECISION_QPEL_INTEL                           0x0
+#define CL_ME_COST_PRECISION_HPEL_INTEL                           0x1
+#define CL_ME_COST_PRECISION_PEL_INTEL                            0x2
+#define CL_ME_COST_PRECISION_DPEL_INTEL                           0x3
+
+#define CL_ME_LUMA_PREDICTOR_MODE_VERTICAL_INTEL                  0x0
+#define CL_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_INTEL                0x1
+#define CL_ME_LUMA_PREDICTOR_MODE_DC_INTEL                        0x2
+#define CL_ME_LUMA_PREDICTOR_MODE_DIAGONAL_DOWN_LEFT_INTEL        0x3
+
+#define CL_ME_LUMA_PREDICTOR_MODE_DIAGONAL_DOWN_RIGHT_INTEL       0x4
+#define CL_ME_LUMA_PREDICTOR_MODE_PLANE_INTEL                     0x4
+#define CL_ME_LUMA_PREDICTOR_MODE_VERTICAL_RIGHT_INTEL            0x5
+#define CL_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_DOWN_INTEL           0x6
+#define CL_ME_LUMA_PREDICTOR_MODE_VERTICAL_LEFT_INTEL             0x7
+#define CL_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_UP_INTEL             0x8
+
+#define CL_ME_CHROMA_PREDICTOR_MODE_DC_INTEL                      0x0
+#define CL_ME_CHROMA_PREDICTOR_MODE_HORIZONTAL_INTEL              0x1
+#define CL_ME_CHROMA_PREDICTOR_MODE_VERTICAL_INTEL                0x2
+#define CL_ME_CHROMA_PREDICTOR_MODE_PLANE_INTEL                   0x3
+
+/* cl_device_info */
+#define CL_DEVICE_ME_VERSION_INTEL                                0x407E
+
+#define CL_ME_VERSION_LEGACY_INTEL                                0x0
+#define CL_ME_VERSION_ADVANCED_VER_1_INTEL                        0x1
+#define CL_ME_VERSION_ADVANCED_VER_2_INTEL                        0x2
+
+extern CL_API_ENTRY cl_accelerator_intel CL_API_CALL
+clCreateAcceleratorINTEL(
+    cl_context                   context,
+    cl_accelerator_type_intel    accelerator_type,
+    size_t                       descriptor_size,
+    const void*                  descriptor,
+    cl_int*                      errcode_ret) CL_EXT_SUFFIX__VERSION_1_2;
+
+typedef CL_API_ENTRY cl_accelerator_intel (CL_API_CALL *clCreateAcceleratorINTEL_fn)(
+    cl_context                   context,
+    cl_accelerator_type_intel    accelerator_type,
+    size_t                       descriptor_size,
+    const void*                  descriptor,
+    cl_int*                      errcode_ret) CL_EXT_SUFFIX__VERSION_1_2;
+
+extern CL_API_ENTRY cl_int CL_API_CALL
+clGetAcceleratorInfoINTEL(
+    cl_accelerator_intel         accelerator,
+    cl_accelerator_info_intel    param_name,
+    size_t                       param_value_size,
+    void*                        param_value,
+    size_t*                      param_value_size_ret) CL_EXT_SUFFIX__VERSION_1_2;
+
+typedef CL_API_ENTRY cl_int (CL_API_CALL *clGetAcceleratorInfoINTEL_fn)(
+    cl_accelerator_intel         accelerator,
+    cl_accelerator_info_intel    param_name,
+    size_t                       param_value_size,
+    void*                        param_value,
+    size_t*                      param_value_size_ret) CL_EXT_SUFFIX__VERSION_1_2;
+
+extern CL_API_ENTRY cl_int CL_API_CALL
+clRetainAcceleratorINTEL(
+    cl_accelerator_intel         accelerator) CL_EXT_SUFFIX__VERSION_1_2;
+
+typedef CL_API_ENTRY cl_int (CL_API_CALL *clRetainAcceleratorINTEL_fn)(
+    cl_accelerator_intel         accelerator) CL_EXT_SUFFIX__VERSION_1_2;
+
+extern CL_API_ENTRY cl_int CL_API_CALL
+clReleaseAcceleratorINTEL(
+    cl_accelerator_intel         accelerator) CL_EXT_SUFFIX__VERSION_1_2;
+
+typedef CL_API_ENTRY cl_int (CL_API_CALL *clReleaseAcceleratorINTEL_fn)(
+    cl_accelerator_intel         accelerator) CL_EXT_SUFFIX__VERSION_1_2;
+
+/******************************************
+* cl_intel_simultaneous_sharing extension *
+*******************************************/
+
+#define cl_intel_simultaneous_sharing 1
+
+#define CL_DEVICE_SIMULTANEOUS_INTEROPS_INTEL            0x4104
+#define CL_DEVICE_NUM_SIMULTANEOUS_INTEROPS_INTEL        0x4105
+
+/***********************************
+* cl_intel_egl_image_yuv extension *
+************************************/
+
+#define cl_intel_egl_image_yuv 1
+
+#define CL_EGL_YUV_PLANE_INTEL                           0x4107
+
+/********************************
+* cl_intel_packed_yuv extension *
+*********************************/
+
+#define cl_intel_packed_yuv 1
+
+#define CL_YUYV_INTEL                                    0x4076
+#define CL_UYVY_INTEL                                    0x4077
+#define CL_YVYU_INTEL                                    0x4078
+#define CL_VYUY_INTEL                                    0x4079
+
+/********************************************
+* cl_intel_required_subgroup_size extension *
+*********************************************/
+
+#define cl_intel_required_subgroup_size 1
+
+#define CL_DEVICE_SUB_GROUP_SIZES_INTEL                  0x4108
+#define CL_KERNEL_SPILL_MEM_SIZE_INTEL                   0x4109
+#define CL_KERNEL_COMPILE_SUB_GROUP_SIZE_INTEL           0x410A
+
+/****************************************
+* cl_intel_driver_diagnostics extension *
+*****************************************/
+
+#define cl_intel_driver_diagnostics 1
+
+typedef cl_uint cl_diagnostics_verbose_level;
+
+#define CL_CONTEXT_SHOW_DIAGNOSTICS_INTEL                0x4106
+
+#define CL_CONTEXT_DIAGNOSTICS_LEVEL_ALL_INTEL           ( 0xff )
+#define CL_CONTEXT_DIAGNOSTICS_LEVEL_GOOD_INTEL          ( 1 )
+#define CL_CONTEXT_DIAGNOSTICS_LEVEL_BAD_INTEL           ( 1 << 1 )
+#define CL_CONTEXT_DIAGNOSTICS_LEVEL_NEUTRAL_INTEL       ( 1 << 2 )
+
+/********************************
+* cl_intel_planar_yuv extension *
+*********************************/
+
+#define CL_NV12_INTEL                                       0x410E
+
+#define CL_MEM_NO_ACCESS_INTEL                              ( 1 << 24 )
+#define CL_MEM_ACCESS_FLAGS_UNRESTRICTED_INTEL              ( 1 << 25 )
+
+#define CL_DEVICE_PLANAR_YUV_MAX_WIDTH_INTEL                0x417E
+#define CL_DEVICE_PLANAR_YUV_MAX_HEIGHT_INTEL               0x417F
+
+/*******************************************************
+* cl_intel_device_side_avc_motion_estimation extension *
+********************************************************/
+
+#define CL_DEVICE_AVC_ME_VERSION_INTEL                      0x410B
+#define CL_DEVICE_AVC_ME_SUPPORTS_TEXTURE_SAMPLER_USE_INTEL 0x410C
+#define CL_DEVICE_AVC_ME_SUPPORTS_PREEMPTION_INTEL          0x410D
+
+#define CL_AVC_ME_VERSION_0_INTEL                           0x0;  // No support.
+#define CL_AVC_ME_VERSION_1_INTEL                           0x1;  // First supported version.
+
+#define CL_AVC_ME_MAJOR_16x16_INTEL                         0x0
+#define CL_AVC_ME_MAJOR_16x8_INTEL                          0x1
+#define CL_AVC_ME_MAJOR_8x16_INTEL                          0x2
+#define CL_AVC_ME_MAJOR_8x8_INTEL                           0x3
+
+#define CL_AVC_ME_MINOR_8x8_INTEL                           0x0
+#define CL_AVC_ME_MINOR_8x4_INTEL                           0x1
+#define CL_AVC_ME_MINOR_4x8_INTEL                           0x2
+#define CL_AVC_ME_MINOR_4x4_INTEL                           0x3
+
+#define CL_AVC_ME_MAJOR_FORWARD_INTEL                       0x0
+#define CL_AVC_ME_MAJOR_BACKWARD_INTEL                      0x1
+#define CL_AVC_ME_MAJOR_BIDIRECTIONAL_INTEL                 0x2
+
+#define CL_AVC_ME_PARTITION_MASK_ALL_INTEL                  0x0
+#define CL_AVC_ME_PARTITION_MASK_16x16_INTEL                0x7E
+#define CL_AVC_ME_PARTITION_MASK_16x8_INTEL                 0x7D
+#define CL_AVC_ME_PARTITION_MASK_8x16_INTEL                 0x7B
+#define CL_AVC_ME_PARTITION_MASK_8x8_INTEL                  0x77
+#define CL_AVC_ME_PARTITION_MASK_8x4_INTEL                  0x6F
+#define CL_AVC_ME_PARTITION_MASK_4x8_INTEL                  0x5F
+#define CL_AVC_ME_PARTITION_MASK_4x4_INTEL                  0x3F
+
+#define CL_AVC_ME_SEARCH_WINDOW_EXHAUSTIVE_INTEL            0x0
+#define CL_AVC_ME_SEARCH_WINDOW_SMALL_INTEL                 0x1
+#define CL_AVC_ME_SEARCH_WINDOW_TINY_INTEL                  0x2
+#define CL_AVC_ME_SEARCH_WINDOW_EXTRA_TINY_INTEL            0x3
+#define CL_AVC_ME_SEARCH_WINDOW_DIAMOND_INTEL               0x4
+#define CL_AVC_ME_SEARCH_WINDOW_LARGE_DIAMOND_INTEL         0x5
+#define CL_AVC_ME_SEARCH_WINDOW_RESERVED0_INTEL             0x6
+#define CL_AVC_ME_SEARCH_WINDOW_RESERVED1_INTEL             0x7
+#define CL_AVC_ME_SEARCH_WINDOW_CUSTOM_INTEL                0x8
+#define CL_AVC_ME_SEARCH_WINDOW_16x12_RADIUS_INTEL          0x9
+#define CL_AVC_ME_SEARCH_WINDOW_4x4_RADIUS_INTEL            0x2
+#define CL_AVC_ME_SEARCH_WINDOW_2x2_RADIUS_INTEL            0xa
+
+#define CL_AVC_ME_SAD_ADJUST_MODE_NONE_INTEL                0x0
+#define CL_AVC_ME_SAD_ADJUST_MODE_HAAR_INTEL                0x2
+
+#define CL_AVC_ME_SUBPIXEL_MODE_INTEGER_INTEL               0x0
+#define CL_AVC_ME_SUBPIXEL_MODE_HPEL_INTEL                  0x1
+#define CL_AVC_ME_SUBPIXEL_MODE_QPEL_INTEL                  0x3
+
+#define CL_AVC_ME_COST_PRECISION_QPEL_INTEL                 0x0
+#define CL_AVC_ME_COST_PRECISION_HPEL_INTEL                 0x1
+#define CL_AVC_ME_COST_PRECISION_PEL_INTEL                  0x2
+#define CL_AVC_ME_COST_PRECISION_DPEL_INTEL                 0x3
+
+#define CL_AVC_ME_BIDIR_WEIGHT_QUARTER_INTEL                0x10
+#define CL_AVC_ME_BIDIR_WEIGHT_THIRD_INTEL                  0x15
+#define CL_AVC_ME_BIDIR_WEIGHT_HALF_INTEL                   0x20
+#define CL_AVC_ME_BIDIR_WEIGHT_TWO_THIRD_INTEL              0x2B
+#define CL_AVC_ME_BIDIR_WEIGHT_THREE_QUARTER_INTEL          0x30
+
+#define CL_AVC_ME_BORDER_REACHED_LEFT_INTEL                 0x0
+#define CL_AVC_ME_BORDER_REACHED_RIGHT_INTEL                0x2
+#define CL_AVC_ME_BORDER_REACHED_TOP_INTEL                  0x4
+#define CL_AVC_ME_BORDER_REACHED_BOTTOM_INTEL               0x8
+
+#define CL_AVC_ME_SKIP_BLOCK_PARTITION_16x16_INTEL          0x0
+#define CL_AVC_ME_SKIP_BLOCK_PARTITION_8x8_INTEL            0x4000
+
+#define CL_AVC_ME_SKIP_BLOCK_16x16_FORWARD_ENABLE_INTEL     ( 0x1 << 24 )
+#define CL_AVC_ME_SKIP_BLOCK_16x16_BACKWARD_ENABLE_INTEL    ( 0x2 << 24 )
+#define CL_AVC_ME_SKIP_BLOCK_16x16_DUAL_ENABLE_INTEL        ( 0x3 << 24 )
+#define CL_AVC_ME_SKIP_BLOCK_8x8_FORWARD_ENABLE_INTEL       ( 0x55 << 24 )
+#define CL_AVC_ME_SKIP_BLOCK_8x8_BACKWARD_ENABLE_INTEL      ( 0xAA << 24 )
+#define CL_AVC_ME_SKIP_BLOCK_8x8_DUAL_ENABLE_INTEL          ( 0xFF << 24 )
+#define CL_AVC_ME_SKIP_BLOCK_8x8_0_FORWARD_ENABLE_INTEL     ( 0x1 << 24 )
+#define CL_AVC_ME_SKIP_BLOCK_8x8_0_BACKWARD_ENABLE_INTEL    ( 0x2 << 24 )
+#define CL_AVC_ME_SKIP_BLOCK_8x8_1_FORWARD_ENABLE_INTEL     ( 0x1 << 26 )
+#define CL_AVC_ME_SKIP_BLOCK_8x8_1_BACKWARD_ENABLE_INTEL    ( 0x2 << 26 )
+#define CL_AVC_ME_SKIP_BLOCK_8x8_2_FORWARD_ENABLE_INTEL     ( 0x1 << 28 )
+#define CL_AVC_ME_SKIP_BLOCK_8x8_2_BACKWARD_ENABLE_INTEL    ( 0x2 << 28 )
+#define CL_AVC_ME_SKIP_BLOCK_8x8_3_FORWARD_ENABLE_INTEL     ( 0x1 << 30 )
+#define CL_AVC_ME_SKIP_BLOCK_8x8_3_BACKWARD_ENABLE_INTEL    ( 0x2 << 30 )
+
+#define CL_AVC_ME_BLOCK_BASED_SKIP_4x4_INTEL                0x00
+#define CL_AVC_ME_BLOCK_BASED_SKIP_8x8_INTEL                0x80
+
+#define CL_AVC_ME_INTRA_16x16_INTEL                         0x0
+#define CL_AVC_ME_INTRA_8x8_INTEL                           0x1
+#define CL_AVC_ME_INTRA_4x4_INTEL                           0x2
+
+#define CL_AVC_ME_INTRA_LUMA_PARTITION_MASK_16x16_INTEL     0x6
+#define CL_AVC_ME_INTRA_LUMA_PARTITION_MASK_8x8_INTEL       0x5
+#define CL_AVC_ME_INTRA_LUMA_PARTITION_MASK_4x4_INTEL       0x3
+
+#define CL_AVC_ME_INTRA_NEIGHBOR_LEFT_MASK_ENABLE_INTEL         0x60
+#define CL_AVC_ME_INTRA_NEIGHBOR_UPPER_MASK_ENABLE_INTEL        0x10
+#define CL_AVC_ME_INTRA_NEIGHBOR_UPPER_RIGHT_MASK_ENABLE_INTEL  0x8
+#define CL_AVC_ME_INTRA_NEIGHBOR_UPPER_LEFT_MASK_ENABLE_INTEL   0x4
+
+#define CL_AVC_ME_LUMA_PREDICTOR_MODE_VERTICAL_INTEL            0x0
+#define CL_AVC_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_INTEL          0x1
+#define CL_AVC_ME_LUMA_PREDICTOR_MODE_DC_INTEL                  0x2
+#define CL_AVC_ME_LUMA_PREDICTOR_MODE_DIAGONAL_DOWN_LEFT_INTEL  0x3
+#define CL_AVC_ME_LUMA_PREDICTOR_MODE_DIAGONAL_DOWN_RIGHT_INTEL 0x4
+#define CL_AVC_ME_LUMA_PREDICTOR_MODE_PLANE_INTEL               0x4
+#define CL_AVC_ME_LUMA_PREDICTOR_MODE_VERTICAL_RIGHT_INTEL      0x5
+#define CL_AVC_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_DOWN_INTEL     0x6
+#define CL_AVC_ME_LUMA_PREDICTOR_MODE_VERTICAL_LEFT_INTEL       0x7
+#define CL_AVC_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_UP_INTEL       0x8
+#define CL_AVC_ME_CHROMA_PREDICTOR_MODE_DC_INTEL                0x0
+#define CL_AVC_ME_CHROMA_PREDICTOR_MODE_HORIZONTAL_INTEL        0x1
+#define CL_AVC_ME_CHROMA_PREDICTOR_MODE_VERTICAL_INTEL          0x2
+#define CL_AVC_ME_CHROMA_PREDICTOR_MODE_PLANE_INTEL             0x3
+
+#define CL_AVC_ME_FRAME_FORWARD_INTEL                       0x1
+#define CL_AVC_ME_FRAME_BACKWARD_INTEL                      0x2
+#define CL_AVC_ME_FRAME_DUAL_INTEL                          0x3
+
+#define CL_AVC_ME_SLICE_TYPE_PRED_INTEL                     0x0
+#define CL_AVC_ME_SLICE_TYPE_BPRED_INTEL                    0x1
+#define CL_AVC_ME_SLICE_TYPE_INTRA_INTEL                    0x2
+
+#define CL_AVC_ME_INTERLACED_SCAN_TOP_FIELD_INTEL           0x0
+#define CL_AVC_ME_INTERLACED_SCAN_BOTTOM_FIELD_INTEL        0x1
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CL_EXT_INTEL_H */

src/3rdparty/CL/cl_gl.h

@@ -0,0 +1,171 @@
+/**********************************************************************************
+ * Copyright (c) 2008-2019 The Khronos Group Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and/or associated documentation files (the
+ * "Materials"), to deal in the Materials without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Materials, and to
+ * permit persons to whom the Materials are furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Materials.
+ *
+ * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS
+ * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS
+ * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT
+ *    https://www.khronos.org/registry/
+ *
+ * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
+ **********************************************************************************/
+
+#ifndef __OPENCL_CL_GL_H
+#define __OPENCL_CL_GL_H
+
+#include <CL/cl.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef cl_uint     cl_gl_object_type;
+typedef cl_uint     cl_gl_texture_info;
+typedef cl_uint     cl_gl_platform_info;
+typedef struct __GLsync *cl_GLsync;
+
+/* cl_gl_object_type = 0x2000 - 0x200F enum values are currently taken           */
+#define CL_GL_OBJECT_BUFFER                     0x2000
+#define CL_GL_OBJECT_TEXTURE2D                  0x2001
+#define CL_GL_OBJECT_TEXTURE3D                  0x2002
+#define CL_GL_OBJECT_RENDERBUFFER               0x2003
+#ifdef CL_VERSION_1_2
+#define CL_GL_OBJECT_TEXTURE2D_ARRAY            0x200E
+#define CL_GL_OBJECT_TEXTURE1D                  0x200F
+#define CL_GL_OBJECT_TEXTURE1D_ARRAY            0x2010
+#define CL_GL_OBJECT_TEXTURE_BUFFER             0x2011
+#endif
+
+/* cl_gl_texture_info           */
+#define CL_GL_TEXTURE_TARGET                    0x2004
+#define CL_GL_MIPMAP_LEVEL                      0x2005
+#ifdef CL_VERSION_1_2
+#define CL_GL_NUM_SAMPLES                       0x2012
+#endif
+
+
+extern CL_API_ENTRY cl_mem CL_API_CALL
+clCreateFromGLBuffer(cl_context     context,
+                     cl_mem_flags   flags,
+                     cl_GLuint      bufobj,
+                     cl_int *       errcode_ret) CL_API_SUFFIX__VERSION_1_0;
+
+#ifdef CL_VERSION_1_2
+
+extern CL_API_ENTRY cl_mem CL_API_CALL
+clCreateFromGLTexture(cl_context      context,
+                      cl_mem_flags    flags,
+                      cl_GLenum       target,
+                      cl_GLint        miplevel,
+                      cl_GLuint       texture,
+                      cl_int *        errcode_ret) CL_API_SUFFIX__VERSION_1_2;
+
+#endif
+
+extern CL_API_ENTRY cl_mem CL_API_CALL
+clCreateFromGLRenderbuffer(cl_context   context,
+                           cl_mem_flags flags,
+                           cl_GLuint    renderbuffer,
+                           cl_int *     errcode_ret) CL_API_SUFFIX__VERSION_1_0;
+
+extern CL_API_ENTRY cl_int CL_API_CALL
+clGetGLObjectInfo(cl_mem                memobj,
+                  cl_gl_object_type *   gl_object_type,
+                  cl_GLuint *           gl_object_name) CL_API_SUFFIX__VERSION_1_0;
+
+extern CL_API_ENTRY cl_int CL_API_CALL
+clGetGLTextureInfo(cl_mem               memobj,
+                   cl_gl_texture_info   param_name,
+                   size_t               param_value_size,
+                   void *               param_value,
+                   size_t *             param_value_size_ret) CL_API_SUFFIX__VERSION_1_0;
+
+extern CL_API_ENTRY cl_int CL_API_CALL
+clEnqueueAcquireGLObjects(cl_command_queue      command_queue,
+                          cl_uint               num_objects,
+                          const cl_mem *        mem_objects,
+                          cl_uint               num_events_in_wait_list,
+                          const cl_event *      event_wait_list,
+                          cl_event *            event) CL_API_SUFFIX__VERSION_1_0;
+
+extern CL_API_ENTRY cl_int CL_API_CALL
+clEnqueueReleaseGLObjects(cl_command_queue      command_queue,
+                          cl_uint               num_objects,
+                          const cl_mem *        mem_objects,
+                          cl_uint               num_events_in_wait_list,
+                          const cl_event *      event_wait_list,
+                          cl_event *            event) CL_API_SUFFIX__VERSION_1_0;
+
+
+/* Deprecated OpenCL 1.1 APIs */
+extern CL_API_ENTRY CL_EXT_PREFIX__VERSION_1_1_DEPRECATED cl_mem CL_API_CALL
+clCreateFromGLTexture2D(cl_context      context,
+                        cl_mem_flags    flags,
+                        cl_GLenum       target,
+                        cl_GLint        miplevel,
+                        cl_GLuint       texture,
+                        cl_int *        errcode_ret) CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED;
+
+extern CL_API_ENTRY CL_EXT_PREFIX__VERSION_1_1_DEPRECATED cl_mem CL_API_CALL
+clCreateFromGLTexture3D(cl_context      context,
+                        cl_mem_flags    flags,
+                        cl_GLenum       target,
+                        cl_GLint        miplevel,
+                        cl_GLuint       texture,
+                        cl_int *        errcode_ret) CL_EXT_SUFFIX__VERSION_1_1_DEPRECATED;
+
+/* cl_khr_gl_sharing extension  */
+
+#define cl_khr_gl_sharing 1
+
+typedef cl_uint     cl_gl_context_info;
+
+/* Additional Error Codes  */
+#define CL_INVALID_GL_SHAREGROUP_REFERENCE_KHR  -1000
+
+/* cl_gl_context_info  */
+#define CL_CURRENT_DEVICE_FOR_GL_CONTEXT_KHR    0x2006
+#define CL_DEVICES_FOR_GL_CONTEXT_KHR           0x2007
+
+/* Additional cl_context_properties  */
+#define CL_GL_CONTEXT_KHR                       0x2008
+#define CL_EGL_DISPLAY_KHR                      0x2009
+#define CL_GLX_DISPLAY_KHR                      0x200A
+#define CL_WGL_HDC_KHR                          0x200B
+#define CL_CGL_SHAREGROUP_KHR                   0x200C
+
+extern CL_API_ENTRY cl_int CL_API_CALL
+clGetGLContextInfoKHR(const cl_context_properties * properties,
+                      cl_gl_context_info            param_name,
+                      size_t                        param_value_size,
+                      void *                        param_value,
+                      size_t *                      param_value_size_ret) CL_API_SUFFIX__VERSION_1_0;
+
+typedef CL_API_ENTRY cl_int (CL_API_CALL *clGetGLContextInfoKHR_fn)(
+    const cl_context_properties * properties,
+    cl_gl_context_info            param_name,
+    size_t                        param_value_size,
+    void *                        param_value,
+    size_t *                      param_value_size_ret);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __OPENCL_CL_GL_H */

src/3rdparty/CL/cl_gl_ext.h

@@ -0,0 +1,52 @@
+/**********************************************************************************
+ * Copyright (c) 2008-2019 The Khronos Group Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and/or associated documentation files (the
+ * "Materials"), to deal in the Materials without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Materials, and to
+ * permit persons to whom the Materials are furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Materials.
+ *
+ * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS
+ * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS
+ * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT
+ *    https://www.khronos.org/registry/
+ *
+ * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
+ **********************************************************************************/
+
+#ifndef __OPENCL_CL_GL_EXT_H
+#define __OPENCL_CL_GL_EXT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <CL/cl_gl.h>
+
+/* 
+ *  cl_khr_gl_event extension
+ */
+#define CL_COMMAND_GL_FENCE_SYNC_OBJECT_KHR     0x200D
+
+extern CL_API_ENTRY cl_event CL_API_CALL
+clCreateEventFromGLsyncKHR(cl_context context,
+                           cl_GLsync  cl_GLsync,
+                           cl_int *   errcode_ret) CL_EXT_SUFFIX__VERSION_1_1;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* __OPENCL_CL_GL_EXT_H  */

src/3rdparty/CL/cl_va_api_media_sharing_intel.h

@@ -0,0 +1,172 @@
+/**********************************************************************************
+ * Copyright (c) 2008-2019 The Khronos Group Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and/or associated documentation files (the
+ * "Materials"), to deal in the Materials without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Materials, and to
+ * permit persons to whom the Materials are furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Materials.
+ *
+ * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS
+ * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS
+ * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT
+ *    https://www.khronos.org/registry/
+ *
+ * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
+ **********************************************************************************/
+/*****************************************************************************\
+
+Copyright (c) 2013-2019 Intel Corporation All Rights Reserved.
+
+THESE MATERIALS ARE PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS
+CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THESE
+MATERIALS, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+File Name: cl_va_api_media_sharing_intel.h
+
+Abstract:
+
+Notes:
+
+\*****************************************************************************/
+
+
+#ifndef __OPENCL_CL_VA_API_MEDIA_SHARING_INTEL_H
+#define __OPENCL_CL_VA_API_MEDIA_SHARING_INTEL_H
+
+#include <CL/cl.h>
+#include <CL/cl_platform.h>
+#include <va/va.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/******************************************
+* cl_intel_va_api_media_sharing extension *
+*******************************************/
+
+#define cl_intel_va_api_media_sharing 1
+
+/* error codes */
+#define CL_INVALID_VA_API_MEDIA_ADAPTER_INTEL               -1098
+#define CL_INVALID_VA_API_MEDIA_SURFACE_INTEL               -1099
+#define CL_VA_API_MEDIA_SURFACE_ALREADY_ACQUIRED_INTEL      -1100
+#define CL_VA_API_MEDIA_SURFACE_NOT_ACQUIRED_INTEL          -1101
+
+/* cl_va_api_device_source_intel */
+#define CL_VA_API_DISPLAY_INTEL                             0x4094
+
+/* cl_va_api_device_set_intel */
+#define CL_PREFERRED_DEVICES_FOR_VA_API_INTEL               0x4095
+#define CL_ALL_DEVICES_FOR_VA_API_INTEL                     0x4096
+
+/* cl_context_info */
+#define CL_CONTEXT_VA_API_DISPLAY_INTEL                     0x4097
+
+/* cl_mem_info */
+#define CL_MEM_VA_API_MEDIA_SURFACE_INTEL                   0x4098
+
+/* cl_image_info */
+#define CL_IMAGE_VA_API_PLANE_INTEL                         0x4099
+
+/* cl_command_type */
+#define CL_COMMAND_ACQUIRE_VA_API_MEDIA_SURFACES_INTEL      0x409A
+#define CL_COMMAND_RELEASE_VA_API_MEDIA_SURFACES_INTEL      0x409B
+
+typedef cl_uint cl_va_api_device_source_intel;
+typedef cl_uint cl_va_api_device_set_intel;
+
+extern CL_API_ENTRY cl_int CL_API_CALL
+clGetDeviceIDsFromVA_APIMediaAdapterINTEL(
+    cl_platform_id                platform,
+    cl_va_api_device_source_intel media_adapter_type,
+    void*                         media_adapter,
+    cl_va_api_device_set_intel    media_adapter_set,
+    cl_uint                       num_entries,
+    cl_device_id*                 devices,
+    cl_uint*                      num_devices) CL_EXT_SUFFIX__VERSION_1_2;
+
+typedef CL_API_ENTRY cl_int (CL_API_CALL * clGetDeviceIDsFromVA_APIMediaAdapterINTEL_fn)(
+    cl_platform_id                platform,
+    cl_va_api_device_source_intel media_adapter_type,
+    void*                         media_adapter,
+    cl_va_api_device_set_intel    media_adapter_set,
+    cl_uint                       num_entries,
+    cl_device_id*                 devices,
+    cl_uint*                      num_devices) CL_EXT_SUFFIX__VERSION_1_2;
+
+extern CL_API_ENTRY cl_mem CL_API_CALL
+clCreateFromVA_APIMediaSurfaceINTEL(
+    cl_context                    context,
+    cl_mem_flags                  flags,
+    VASurfaceID*                  surface,
+    cl_uint                       plane,
+    cl_int*                       errcode_ret) CL_EXT_SUFFIX__VERSION_1_2;
+
+typedef CL_API_ENTRY cl_mem (CL_API_CALL * clCreateFromVA_APIMediaSurfaceINTEL_fn)(
+    cl_context                    context,
+    cl_mem_flags                  flags,
+    VASurfaceID*                  surface,
+    cl_uint                       plane,
+    cl_int*                       errcode_ret) CL_EXT_SUFFIX__VERSION_1_2;
+
+extern CL_API_ENTRY cl_int CL_API_CALL
+clEnqueueAcquireVA_APIMediaSurfacesINTEL(
+    cl_command_queue              command_queue,
+    cl_uint                       num_objects,
+    const cl_mem*                 mem_objects,
+    cl_uint                       num_events_in_wait_list,
+    const cl_event*               event_wait_list,
+    cl_event*                     event) CL_EXT_SUFFIX__VERSION_1_2;
+
+typedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueAcquireVA_APIMediaSurfacesINTEL_fn)(
+    cl_command_queue              command_queue,
+    cl_uint                       num_objects,
+    const cl_mem*                 mem_objects,
+    cl_uint                       num_events_in_wait_list,
+    const cl_event*               event_wait_list,
+    cl_event*                     event) CL_EXT_SUFFIX__VERSION_1_2;
+
+extern CL_API_ENTRY cl_int CL_API_CALL
+clEnqueueReleaseVA_APIMediaSurfacesINTEL(
+    cl_command_queue              command_queue,
+    cl_uint                       num_objects,
+    const cl_mem*                 mem_objects,
+    cl_uint                       num_events_in_wait_list,
+    const cl_event*               event_wait_list,
+    cl_event*                     event) CL_EXT_SUFFIX__VERSION_1_2;
+
+typedef CL_API_ENTRY cl_int (CL_API_CALL *clEnqueueReleaseVA_APIMediaSurfacesINTEL_fn)(
+    cl_command_queue              command_queue,
+    cl_uint                       num_objects,
+    const cl_mem*                 mem_objects,
+    cl_uint                       num_events_in_wait_list,
+    const cl_event*               event_wait_list,
+    cl_event*                     event) CL_EXT_SUFFIX__VERSION_1_2;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __OPENCL_CL_VA_API_MEDIA_SHARING_INTEL_H */
+

src/3rdparty/CL/cl_version.h

@@ -0,0 +1,86 @@
+/*******************************************************************************
+ * Copyright (c) 2018 The Khronos Group Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and/or associated documentation files (the
+ * "Materials"), to deal in the Materials without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Materials, and to
+ * permit persons to whom the Materials are furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Materials.
+ *
+ * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS
+ * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS
+ * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT
+ *    https://www.khronos.org/registry/
+ *
+ * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
+ ******************************************************************************/
+
+#ifndef __CL_VERSION_H
+#define __CL_VERSION_H
+
+/* Detect which version to target */
+#if !defined(CL_TARGET_OPENCL_VERSION)
+#pragma message("cl_version.h: CL_TARGET_OPENCL_VERSION is not defined. Defaulting to 220 (OpenCL 2.2)")
+#define CL_TARGET_OPENCL_VERSION 220
+#endif
+#if CL_TARGET_OPENCL_VERSION != 100 && \
+    CL_TARGET_OPENCL_VERSION != 110 && \
+    CL_TARGET_OPENCL_VERSION != 120 && \
+    CL_TARGET_OPENCL_VERSION != 200 && \
+    CL_TARGET_OPENCL_VERSION != 210 && \
+    CL_TARGET_OPENCL_VERSION != 220
+#pragma message("cl_version: CL_TARGET_OPENCL_VERSION is not a valid value (100, 110, 120, 200, 210, 220). Defaulting to 220 (OpenCL 2.2)")
+#undef CL_TARGET_OPENCL_VERSION
+#define CL_TARGET_OPENCL_VERSION 220
+#endif
+
+
+/* OpenCL Version */
+#if CL_TARGET_OPENCL_VERSION >= 220 && !defined(CL_VERSION_2_2)
+#define CL_VERSION_2_2  1
+#endif
+#if CL_TARGET_OPENCL_VERSION >= 210 && !defined(CL_VERSION_2_1)
+#define CL_VERSION_2_1  1
+#endif
+#if CL_TARGET_OPENCL_VERSION >= 200 && !defined(CL_VERSION_2_0)
+#define CL_VERSION_2_0  1
+#endif
+#if CL_TARGET_OPENCL_VERSION >= 120 && !defined(CL_VERSION_1_2)
+#define CL_VERSION_1_2  1
+#endif
+#if CL_TARGET_OPENCL_VERSION >= 110 && !defined(CL_VERSION_1_1)
+#define CL_VERSION_1_1  1
+#endif
+#if CL_TARGET_OPENCL_VERSION >= 100 && !defined(CL_VERSION_1_0)
+#define CL_VERSION_1_0  1
+#endif
+
+/* Allow deprecated APIs for older OpenCL versions. */
+#if CL_TARGET_OPENCL_VERSION <= 210 && !defined(CL_USE_DEPRECATED_OPENCL_2_1_APIS)
+#define CL_USE_DEPRECATED_OPENCL_2_1_APIS
+#endif
+#if CL_TARGET_OPENCL_VERSION <= 200 && !defined(CL_USE_DEPRECATED_OPENCL_2_0_APIS)
+#define CL_USE_DEPRECATED_OPENCL_2_0_APIS
+#endif
+#if CL_TARGET_OPENCL_VERSION <= 120 && !defined(CL_USE_DEPRECATED_OPENCL_1_2_APIS)
+#define CL_USE_DEPRECATED_OPENCL_1_2_APIS
+#endif
+#if CL_TARGET_OPENCL_VERSION <= 110 && !defined(CL_USE_DEPRECATED_OPENCL_1_1_APIS)
+#define CL_USE_DEPRECATED_OPENCL_1_1_APIS
+#endif
+#if CL_TARGET_OPENCL_VERSION <= 100 && !defined(CL_USE_DEPRECATED_OPENCL_1_0_APIS)
+#define CL_USE_DEPRECATED_OPENCL_1_0_APIS
+#endif
+
+#endif  /* __CL_VERSION_H */

src/3rdparty/CL/opencl.h

@@ -0,0 +1,47 @@
+/*******************************************************************************
+ * Copyright (c) 2008-2015 The Khronos Group Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and/or associated documentation files (the
+ * "Materials"), to deal in the Materials without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Materials, and to
+ * permit persons to whom the Materials are furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Materials.
+ *
+ * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS
+ * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS
+ * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT
+ *    https://www.khronos.org/registry/
+ *
+ * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
+ ******************************************************************************/
+
+/* $Revision: 11708 $ on $Date: 2010-06-13 23:36:24 -0700 (Sun, 13 Jun 2010) $ */
+
+#ifndef __OPENCL_H
+#define __OPENCL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <CL/cl.h>
+#include <CL/cl_gl.h>
+#include <CL/cl_gl_ext.h>
+#include <CL/cl_ext.h>
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __OPENCL_H   */

src/3rdparty/adl/adl_sdk.h

@@ -0,0 +1,44 @@
+//
+// Copyright (c) 2016 Advanced Micro Devices, Inc. All rights reserved.
+//
+// MIT LICENSE:
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in
+// all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
+
+/// \file adl_sdk.h
+/// \brief Contains the definition of the Memory Allocation Callback.\n <b>Included in ADL SDK</b>
+///
+/// \n\n
+/// This file contains the definition of the Memory Allocation Callback.\n
+/// It also includes definitions of the respective structures and constants.\n
+/// <b> This is the only header file to be included in a C/C++ project using ADL </b>
+
+#ifndef ADL_SDK_H_
+#define ADL_SDK_H_
+
+#include "adl_structures.h"
+
+#if defined (LINUX)
+#define __stdcall
+#endif /* (LINUX) */
+
+/// Memory Allocation Call back 
+typedef void* ( __stdcall *ADL_MAIN_MALLOC_CALLBACK )( int );
+
+
+#endif /* ADL_SDK_H_ */

src/3rdparty/argon2.h

@@ -4,8 +4,9 @@
  * Copyright 2014      Lucas Jones <https://github.com/lucasjones>
  * Copyright 2014-2016 Wolf9466    <https://github.com/OhGodAPet>
  * Copyright 2016      Jay D Dee   <jayddee246@gmail.com>
- * Copyright 2016-2017 XMRig       <support@xmrig.com>
- *
+ * Copyright 2017-2018 XMR-Stak    <https://github.com/fireice-uk>, <https://github.com/psychocrypt>
+ * Copyright 2018-2019 SChernykh   <https://github.com/SChernykh>
+ * Copyright 2016-2019 XMRig       <https://github.com/xmrig>, <support@xmrig.com>
  *
  *   This program is free software: you can redistribute it and/or modify
  *   it under the terms of the GNU General Public License as published by
@@ -22,24 +23,11 @@
  */
 
 
-#include <pthread.h>
-#include <sched.h>
-#include <unistd.h>
+#ifndef XMRIG_3RDPARTY_ARGON2_H
+#define XMRIG_3RDPARTY_ARGON2_H
 
 
-#include "Cpu.h"
+#include "3rdparty/argon2/include/argon2.h"
 
 
-void Cpu::init()
-{
-#   ifdef XMRIG_NO_LIBCPUID
-    m_totalThreads = sysconf(_SC_NPROCESSORS_CONF);
-#   endif
-
-    initCommon();
-}
-
-
-void Cpu::setAffinity(int id, uint64_t mask)
-{
-}
+#endif /* XMRIG_3RDPARTY_ARGON2_H */

src/3rdparty/argon2/CMakeLists.txt

@@ -0,0 +1,88 @@
+cmake_minimum_required(VERSION 2.8)
+
+project(argon2 C)
+set(CMAKE_C_STANDARD 99)
+set(CMAKE_C_STANDARD_REQUIRED ON)
+
+include(CheckCSourceCompiles)
+
+set(ARGON2_SOURCES
+    lib/argon2.c
+    lib/core.c
+    lib/encoding.c
+    lib/genkat.c
+    lib/impl-select.c
+    lib/blake2/blake2.c
+    )
+
+set(ARGON2_X86_64_ENABLED ON)
+set(ARGON2_X86_64_LIBS    argon2-sse2 argon2-ssse3 argon2-xop argon2-avx2 argon2-avx512f)
+set(ARGON2_X86_64_SOURCES arch/x86_64/lib/argon2-arch.c)
+
+if (CMAKE_C_COMPILER_ID MATCHES MSVC)
+    function(add_feature_impl FEATURE MSVC_FLAG DEF)
+        add_library(argon2-${FEATURE} STATIC arch/x86_64/lib/argon2-${FEATURE}.c)
+        target_include_directories(argon2-${FEATURE} PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/../../)
+        target_include_directories(argon2-${FEATURE} PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/lib)
+        set_target_properties(argon2-${FEATURE} PROPERTIES POSITION_INDEPENDENT_CODE True)
+
+        target_compile_options(argon2-${FEATURE} PRIVATE ${MSVC_FLAG})
+        target_compile_definitions(argon2-${FEATURE} PRIVATE ${DEF})
+    endfunction()
+
+    add_feature_impl(sse2    ""              HAVE_SSE2)
+    add_feature_impl(ssse3   "/arch:SSSE3"   HAVE_SSSE3)
+    add_feature_impl(xop     ""              HAVE_XOP)
+    add_feature_impl(avx2    "/arch:AVX2"    HAVE_AVX2)
+    add_feature_impl(avx512f "/arch:AVX512F" HAVE_AVX512F)
+elseif (NOT XMRIG_ARM AND CMAKE_SIZEOF_VOID_P EQUAL 8)
+    function(add_feature_impl FEATURE GCC_FLAG DEF)
+        add_library(argon2-${FEATURE} STATIC arch/x86_64/lib/argon2-${FEATURE}.c)
+        target_include_directories(argon2-${FEATURE} PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/../../)
+        target_include_directories(argon2-${FEATURE} PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/lib)
+        set_target_properties(argon2-${FEATURE} PROPERTIES POSITION_INDEPENDENT_CODE True)
+
+        message("-- argon2: detecting feature '${FEATURE}'...")
+        file(READ arch/x86_64/src/test-feature-${FEATURE}.c SOURCE_CODE)
+
+        # try without flag:
+        check_c_source_compiles("${SOURCE_CODE}" FEATURE_${FEATURE}_NOFLAG)
+        set(HAS_FEATURE ${FEATURE_${FEATURE}_NOFLAG})
+        if (NOT "${HAS_FEATURE}")
+            # try with -m<feature> flag:
+            set(CMAKE_REQUIRED_FLAGS ${GCC_FLAG})
+            check_c_source_compiles("${SOURCE_CODE}" FEATURE_${FEATURE}_FLAG)
+            set(CMAKE_REQUIRED_FLAGS "")
+
+            set(HAS_FEATURE ${FEATURE_${FEATURE}_FLAG})
+            if (${HAS_FEATURE})
+                target_compile_options(argon2-${FEATURE} PRIVATE ${GCC_FLAG})
+            endif()
+        endif()
+
+        if (${HAS_FEATURE})
+            message("-- argon2: feature '${FEATURE}' detected!")
+            target_compile_definitions(argon2-${FEATURE} PRIVATE ${DEF})
+        endif()
+    endfunction()
+
+    add_feature_impl(sse2    -msse2    HAVE_SSE2)
+    add_feature_impl(ssse3   -mssse3   HAVE_SSSE3)
+    add_feature_impl(xop     -mxop     HAVE_XOP)
+    add_feature_impl(avx2    -mavx2    HAVE_AVX2)
+    add_feature_impl(avx512f -mavx512f HAVE_AVX512F)
+else()
+    set(ARGON2_X86_64_ENABLED OFF)
+    list(APPEND ARGON2_SOURCES arch/generic/lib/argon2-arch.c)
+endif()
+
+if (ARGON2_X86_64_ENABLED)
+    set(ARGON2_LIBS ${ARGON2_X86_64_LIBS})
+    list(APPEND ARGON2_SOURCES ${ARGON2_X86_64_SOURCES})
+endif()
+
+add_library(argon2 STATIC ${ARGON2_SOURCES})
+target_link_libraries(argon2 ${ARGON2_LIBS})
+
+target_include_directories(argon2 PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/../../)
+target_include_directories(argon2 PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/lib)

src/3rdparty/argon2/LICENSE

@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) 2016 Ondrej Mosnáček
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

src/3rdparty/argon2/README.md

@@ -0,0 +1,58 @@
+# Argon2 [![Build Status](https://travis-ci.org/WOnder93/argon2.svg?branch=master)](https://travis-ci.org/WOnder93/argon2)
+A multi-arch library implementing the Argon2 password hashing algorithm.
+
+This project is based on the [original source code](https://github.com/P-H-C/phc-winner-argon2) by the Argon2 authors. The goal of this project is to provide efficient Argon2 implementations for various HW architectures (x86, SSE, ARM, PowerPC, ...).
+
+For the x86_64 architecture, the library implements a simple CPU dispatch which automatically selects the best implementation based on CPU flags and quick benchmarks.
+
+# Building
+## Using GNU autotools
+
+To prepare the build environment, run:
+```bash
+autoreconf -i
+./configure
+```
+
+After that, just run `make` to build the library.
+
+### Running tests
+After configuring the build environment, run `make check` to run the tests.
+
+### Architecture options
+You can specify the target architecture by passing the `--host=...` flag to `./configure`.
+
+Supported architectures:
+ * `x86_64` – 64-bit x86 architecture
+ * `generic` – use generic C impementation
+
+## Using CMake
+
+To prepare the build environment, run:
+```bash
+cmake -DCMAKE_BUILD_TYPE=Release .
+```
+
+Then you can run `make` to build the library.
+
+## Using QMake/Qt Creator
+A [QMake](http://doc.qt.io/qt-4.8/qmake-manual.html) project is also available in the `qmake` directory. You can open it in the [Qt Creator IDE](http://wiki.qt.io/Category:Tools::QtCreator) or build it from terminal:
+```bash
+cd qmake
+# see table below for the list of possible ARCH and CONFIG values
+qmake ARCH=... CONFIG+=...
+make
+```
+
+### Architecture options
+For QMake builds you can configure support for different architectures. Use the `ARCH` variable to choose the architecture and the `CONFIG` variable to set additional options.
+
+Supported architectures:
+ * `x86_64` – 64-bit x86 architecture
+   * QMake config flags:
+     * `USE_SSE2` – use SSE2 instructions
+     * `USE_SSSE3` – use SSSE3 instructions
+     * `USE_XOP` – use XOP instructions
+     * `USE_AVX2` – use AVX2 instructions
+     * `USE_AVX512F` – use AVX-512F instructions
+ * `generic` – use generic C impementation

src/3rdparty/argon2/arch/generic/lib/argon2-arch.c

@@ -0,0 +1,20 @@
+#include <stdint.h>
+#include <string.h>
+#include <stdlib.h>
+
+#include "impl-select.h"
+
+#define rotr64(x, n) (((x) >> (n)) | ((x) << (64 - (n))))
+
+#include "argon2-template-64.h"
+
+void fill_segment_default(const argon2_instance_t *instance,
+                          argon2_position_t position)
+{
+    fill_segment_64(instance, position);
+}
+
+void argon2_get_impl_list(argon2_impl_list *list)
+{
+    list->count = 0;
+}

src/3rdparty/argon2/arch/x86_64/lib/argon2-arch.c

@@ -0,0 +1,38 @@
+#include <stdint.h>
+#include <string.h>
+#include <stdlib.h>
+
+#include "impl-select.h"
+
+#include "argon2-sse2.h"
+#include "argon2-ssse3.h"
+#include "argon2-xop.h"
+#include "argon2-avx2.h"
+#include "argon2-avx512f.h"
+
+/* NOTE: there is no portable intrinsic for 64-bit rotate, but any
+ * sane compiler should be able to compile this into a ROR instruction: */
+#define rotr64(x, n) ((x) >> (n)) | ((x) << (64 - (n)))
+
+#include "argon2-template-64.h"
+
+void fill_segment_default(const argon2_instance_t *instance,
+                          argon2_position_t position)
+{
+    fill_segment_64(instance, position);
+}
+
+void argon2_get_impl_list(argon2_impl_list *list)
+{
+    static const argon2_impl IMPLS[] = {
+        { "x86_64",     NULL,                     fill_segment_default },
+        { "SSE2",       xmrig_ar2_check_sse2,     xmrig_ar2_fill_segment_sse2 },
+        { "SSSE3",      xmrig_ar2_check_ssse3,    xmrig_ar2_fill_segment_ssse3 },
+        { "XOP",        xmrig_ar2_check_xop,      xmrig_ar2_fill_segment_xop },
+        { "AVX2",       xmrig_ar2_check_avx2,     xmrig_ar2_fill_segment_avx2 },
+        { "AVX-512F",   xmrig_ar2_check_avx512f,  xmrig_ar2_fill_segment_avx512f },
+    };
+
+    list->count = sizeof(IMPLS) / sizeof(IMPLS[0]);
+    list->entries = IMPLS;
+}

src/3rdparty/argon2/arch/x86_64/lib/argon2-avx2.c

@@ -0,0 +1,335 @@
+#include "argon2-avx2.h"
+
+#ifdef HAVE_AVX2
+#include <string.h>
+
+#ifdef __GNUC__
+#   include <x86intrin.h>
+#else
+#   include <intrin.h>
+#endif
+
+#define r16 (_mm256_setr_epi8( \
+     2,  3,  4,  5,  6,  7,  0,  1, \
+    10, 11, 12, 13, 14, 15,  8,  9, \
+    18, 19, 20, 21, 22, 23, 16, 17, \
+    26, 27, 28, 29, 30, 31, 24, 25))
+
+#define r24 (_mm256_setr_epi8( \
+     3,  4,  5,  6,  7,  0,  1,  2, \
+    11, 12, 13, 14, 15,  8,  9, 10, \
+    19, 20, 21, 22, 23, 16, 17, 18, \
+    27, 28, 29, 30, 31, 24, 25, 26))
+
+#define ror64_16(x) _mm256_shuffle_epi8((x), r16)
+#define ror64_24(x) _mm256_shuffle_epi8((x), r24)
+#define ror64_32(x) _mm256_shuffle_epi32((x), _MM_SHUFFLE(2, 3, 0, 1))
+#define ror64_63(x) \
+    _mm256_xor_si256(_mm256_srli_epi64((x), 63), _mm256_add_epi64((x), (x)))
+
+static __m256i f(__m256i x, __m256i y)
+{
+    __m256i z = _mm256_mul_epu32(x, y);
+    return _mm256_add_epi64(_mm256_add_epi64(x, y), _mm256_add_epi64(z, z));
+}
+
+#define G1(A0, B0, C0, D0, A1, B1, C1, D1) \
+    do { \
+        A0 = f(A0, B0); \
+        A1 = f(A1, B1); \
+\
+        D0 = _mm256_xor_si256(D0, A0); \
+        D1 = _mm256_xor_si256(D1, A1); \
+\
+        D0 = ror64_32(D0); \
+        D1 = ror64_32(D1); \
+\
+        C0 = f(C0, D0); \
+        C1 = f(C1, D1); \
+\
+        B0 = _mm256_xor_si256(B0, C0); \
+        B1 = _mm256_xor_si256(B1, C1); \
+\
+        B0 = ror64_24(B0); \
+        B1 = ror64_24(B1); \
+    } while ((void)0, 0)
+
+#define G2(A0, B0, C0, D0, A1, B1, C1, D1) \
+    do { \
+        A0 = f(A0, B0); \
+        A1 = f(A1, B1); \
+\
+        D0 = _mm256_xor_si256(D0, A0); \
+        D1 = _mm256_xor_si256(D1, A1); \
+\
+        D0 = ror64_16(D0); \
+        D1 = ror64_16(D1); \
+\
+        C0 = f(C0, D0); \
+        C1 = f(C1, D1); \
+\
+        B0 = _mm256_xor_si256(B0, C0); \
+        B1 = _mm256_xor_si256(B1, C1); \
+\
+        B0 = ror64_63(B0); \
+        B1 = ror64_63(B1); \
+    } while ((void)0, 0)
+
+#define DIAGONALIZE1(A0, B0, C0, D0, A1, B1, C1, D1) \
+    do { \
+        B0 = _mm256_permute4x64_epi64(B0, _MM_SHUFFLE(0, 3, 2, 1)); \
+        B1 = _mm256_permute4x64_epi64(B1, _MM_SHUFFLE(0, 3, 2, 1)); \
+\
+        C0 = _mm256_permute4x64_epi64(C0, _MM_SHUFFLE(1, 0, 3, 2)); \
+        C1 = _mm256_permute4x64_epi64(C1, _MM_SHUFFLE(1, 0, 3, 2)); \
+\
+        D0 = _mm256_permute4x64_epi64(D0, _MM_SHUFFLE(2, 1, 0, 3)); \
+        D1 = _mm256_permute4x64_epi64(D1, _MM_SHUFFLE(2, 1, 0, 3)); \
+    } while ((void)0, 0)
+
+#define UNDIAGONALIZE1(A0, B0, C0, D0, A1, B1, C1, D1) \
+    do { \
+        B0 = _mm256_permute4x64_epi64(B0, _MM_SHUFFLE(2, 1, 0, 3)); \
+        B1 = _mm256_permute4x64_epi64(B1, _MM_SHUFFLE(2, 1, 0, 3)); \
+\
+        C0 = _mm256_permute4x64_epi64(C0, _MM_SHUFFLE(1, 0, 3, 2)); \
+        C1 = _mm256_permute4x64_epi64(C1, _MM_SHUFFLE(1, 0, 3, 2)); \
+\
+        D0 = _mm256_permute4x64_epi64(D0, _MM_SHUFFLE(0, 3, 2, 1)); \
+        D1 = _mm256_permute4x64_epi64(D1, _MM_SHUFFLE(0, 3, 2, 1)); \
+    } while ((void)0, 0)
+
+#define DIAGONALIZE2(A0, B0, C0, D0, A1, B1, C1, D1) \
+    do { \
+        __m256i tmp1, tmp2; \
+        tmp1 = _mm256_blend_epi32(B0, B1, 0xCC); \
+        tmp2 = _mm256_blend_epi32(B0, B1, 0x33); \
+        B1 = _mm256_permute4x64_epi64(tmp1, _MM_SHUFFLE(2,3,0,1)); \
+        B0 = _mm256_permute4x64_epi64(tmp2, _MM_SHUFFLE(2,3,0,1)); \
+\
+        tmp1 = C0; \
+        C0 = C1; \
+        C1 = tmp1; \
+\
+        tmp1 = _mm256_blend_epi32(D0, D1, 0xCC); \
+        tmp2 = _mm256_blend_epi32(D0, D1, 0x33); \
+        D0 = _mm256_permute4x64_epi64(tmp1, _MM_SHUFFLE(2,3,0,1)); \
+        D1 = _mm256_permute4x64_epi64(tmp2, _MM_SHUFFLE(2,3,0,1)); \
+    } while ((void)0, 0)
+
+#define UNDIAGONALIZE2(A0, B0, C0, D0, A1, B1, C1, D1) \
+    do { \
+        __m256i tmp1, tmp2; \
+        tmp1 = _mm256_blend_epi32(B0, B1, 0xCC); \
+        tmp2 = _mm256_blend_epi32(B0, B1, 0x33); \
+        B0 = _mm256_permute4x64_epi64(tmp1, _MM_SHUFFLE(2,3,0,1)); \
+        B1 = _mm256_permute4x64_epi64(tmp2, _MM_SHUFFLE(2,3,0,1)); \
+\
+        tmp1 = C0; \
+        C0 = C1; \
+        C1 = tmp1; \
+\
+        tmp1 = _mm256_blend_epi32(D0, D1, 0xCC); \
+        tmp2 = _mm256_blend_epi32(D0, D1, 0x33); \
+        D1 = _mm256_permute4x64_epi64(tmp1, _MM_SHUFFLE(2,3,0,1)); \
+        D0 = _mm256_permute4x64_epi64(tmp2, _MM_SHUFFLE(2,3,0,1)); \
+    } while ((void)0, 0)
+
+#define BLAKE2_ROUND1(A0, B0, C0, D0, A1, B1, C1, D1) \
+    do { \
+        G1(A0, B0, C0, D0, A1, B1, C1, D1); \
+        G2(A0, B0, C0, D0, A1, B1, C1, D1); \
+\
+        DIAGONALIZE1(A0, B0, C0, D0, A1, B1, C1, D1); \
+\
+        G1(A0, B0, C0, D0, A1, B1, C1, D1); \
+        G2(A0, B0, C0, D0, A1, B1, C1, D1); \
+\
+        UNDIAGONALIZE1(A0, B0, C0, D0, A1, B1, C1, D1); \
+    } while ((void)0, 0)
+
+#define BLAKE2_ROUND2(A0, A1, B0, B1, C0, C1, D0, D1) \
+    do { \
+        G1(A0, B0, C0, D0, A1, B1, C1, D1); \
+        G2(A0, B0, C0, D0, A1, B1, C1, D1); \
+\
+        DIAGONALIZE2(A0, B0, C0, D0, A1, B1, C1, D1); \
+\
+        G1(A0, B0, C0, D0, A1, B1, C1, D1); \
+        G2(A0, B0, C0, D0, A1, B1, C1, D1); \
+\
+        UNDIAGONALIZE2(A0, B0, C0, D0, A1, B1, C1, D1); \
+    } while ((void)0, 0)
+
+enum {
+    ARGON2_HWORDS_IN_BLOCK = ARGON2_OWORDS_IN_BLOCK / 2,
+};
+
+static void fill_block(__m256i *s, const block *ref_block, block *next_block,
+                       int with_xor)
+{
+    __m256i block_XY[ARGON2_HWORDS_IN_BLOCK];
+    unsigned int i;
+
+    if (with_xor) {
+        for (i = 0; i < ARGON2_HWORDS_IN_BLOCK; i++) {
+            s[i] =_mm256_xor_si256(
+                s[i], _mm256_loadu_si256((const __m256i *)ref_block->v + i));
+            block_XY[i] = _mm256_xor_si256(
+                s[i], _mm256_loadu_si256((const __m256i *)next_block->v + i));
+        }
+
+    } else {
+        for (i = 0; i < ARGON2_HWORDS_IN_BLOCK; i++) {
+            block_XY[i] = s[i] =_mm256_xor_si256(
+                s[i], _mm256_loadu_si256((const __m256i *)ref_block->v + i));
+        }
+    }
+
+    for (i = 0; i < 4; ++i) {
+        BLAKE2_ROUND1(
+            s[8 * i + 0], s[8 * i + 1], s[8 * i + 2], s[8 * i + 3],
+            s[8 * i + 4], s[8 * i + 5], s[8 * i + 6], s[8 * i + 7]);
+    }
+
+    for (i = 0; i < 4; ++i) {
+        BLAKE2_ROUND2(
+            s[4 * 0 + i], s[4 * 1 + i], s[4 * 2 + i], s[4 * 3 + i],
+            s[4 * 4 + i], s[4 * 5 + i], s[4 * 6 + i], s[4 * 7 + i]);
+    }
+
+    for (i = 0; i < ARGON2_HWORDS_IN_BLOCK; i++) {
+        s[i] = _mm256_xor_si256(s[i], block_XY[i]);
+        _mm256_storeu_si256((__m256i *)next_block->v + i, s[i]);
+    }
+}
+
+static void next_addresses(block *address_block, block *input_block)
+{
+    /*Temporary zero-initialized blocks*/
+    __m256i zero_block[ARGON2_HWORDS_IN_BLOCK];
+    __m256i zero2_block[ARGON2_HWORDS_IN_BLOCK];
+
+    memset(zero_block, 0, sizeof(zero_block));
+    memset(zero2_block, 0, sizeof(zero2_block));
+
+    /*Increasing index counter*/
+    input_block->v[6]++;
+
+    /*First iteration of G*/
+    fill_block(zero_block, input_block, address_block, 0);
+
+    /*Second iteration of G*/
+    fill_block(zero2_block, address_block, address_block, 0);
+}
+
+void xmrig_ar2_fill_segment_avx2(const argon2_instance_t *instance, argon2_position_t position)
+{
+    block *ref_block = NULL, *curr_block = NULL;
+    block address_block, input_block;
+    uint64_t pseudo_rand, ref_index, ref_lane;
+    uint32_t prev_offset, curr_offset;
+    uint32_t starting_index, i;
+    __m256i state[ARGON2_HWORDS_IN_BLOCK];
+    int data_independent_addressing;
+
+    if (instance == NULL) {
+        return;
+    }
+
+    data_independent_addressing = (instance->type == Argon2_i) ||
+            (instance->type == Argon2_id && (position.pass == 0) &&
+             (position.slice < ARGON2_SYNC_POINTS / 2));
+
+    if (data_independent_addressing) {
+        init_block_value(&input_block, 0);
+
+        input_block.v[0] = position.pass;
+        input_block.v[1] = position.lane;
+        input_block.v[2] = position.slice;
+        input_block.v[3] = instance->memory_blocks;
+        input_block.v[4] = instance->passes;
+        input_block.v[5] = instance->type;
+    }
+
+    starting_index = 0;
+
+    if ((0 == position.pass) && (0 == position.slice)) {
+        starting_index = 2; /* we have already generated the first two blocks */
+
+        /* Don't forget to generate the first block of addresses: */
+        if (data_independent_addressing) {
+            next_addresses(&address_block, &input_block);
+        }
+    }
+
+    /* Offset of the current block */
+    curr_offset = position.lane * instance->lane_length +
+                  position.slice * instance->segment_length + starting_index;
+
+    if (0 == curr_offset % instance->lane_length) {
+        /* Last block in this lane */
+        prev_offset = curr_offset + instance->lane_length - 1;
+    } else {
+        /* Previous block */
+        prev_offset = curr_offset - 1;
+    }
+
+    memcpy(state, ((instance->memory + prev_offset)->v), ARGON2_BLOCK_SIZE);
+
+    for (i = starting_index; i < instance->segment_length;
+         ++i, ++curr_offset, ++prev_offset) {
+        /*1.1 Rotating prev_offset if needed */
+        if (curr_offset % instance->lane_length == 1) {
+            prev_offset = curr_offset - 1;
+        }
+
+        /* 1.2 Computing the index of the reference block */
+        /* 1.2.1 Taking pseudo-random value from the previous block */
+        if (data_independent_addressing) {
+            if (i % ARGON2_ADDRESSES_IN_BLOCK == 0) {
+                next_addresses(&address_block, &input_block);
+            }
+            pseudo_rand = address_block.v[i % ARGON2_ADDRESSES_IN_BLOCK];
+        } else {
+            pseudo_rand = instance->memory[prev_offset].v[0];
+        }
+
+        /* 1.2.2 Computing the lane of the reference block */
+        ref_lane = ((pseudo_rand >> 32)) % instance->lanes;
+
+        if ((position.pass == 0) && (position.slice == 0)) {
+            /* Can not reference other lanes yet */
+            ref_lane = position.lane;
+        }
+
+        /* 1.2.3 Computing the number of possible reference block within the
+         * lane.
+         */
+        position.index = i;
+        ref_index = xmrig_ar2_index_alpha(instance, &position, pseudo_rand & 0xFFFFFFFF, ref_lane == position.lane);
+
+        /* 2 Creating a new block */
+        ref_block =
+            instance->memory + instance->lane_length * ref_lane + ref_index;
+        curr_block = instance->memory + curr_offset;
+
+        /* version 1.2.1 and earlier: overwrite, not XOR */
+        if (0 == position.pass || ARGON2_VERSION_10 == instance->version) {
+            fill_block(state, ref_block, curr_block, 0);
+        } else {
+            fill_block(state, ref_block, curr_block, 1);
+        }
+    }
+}
+
+
+extern int cpu_flags_has_avx2(void);
+int xmrig_ar2_check_avx2(void) { return cpu_flags_has_avx2(); }
+
+#else
+
+void xmrig_ar2_fill_segment_avx2(const argon2_instance_t *instance, argon2_position_t position) {}
+int xmrig_ar2_check_avx2(void) { return 0; }
+
+#endif

src/3rdparty/argon2/arch/x86_64/lib/argon2-avx2.h

@@ -0,0 +1,9 @@
+#ifndef ARGON2_AVX2_H
+#define ARGON2_AVX2_H
+
+#include "core.h"
+
+void xmrig_ar2_fill_segment_avx2(const argon2_instance_t *instance, argon2_position_t position);
+int xmrig_ar2_check_avx2(void);
+
+#endif // ARGON2_AVX2_H

src/3rdparty/argon2/arch/x86_64/lib/argon2-avx512f.c

@@ -0,0 +1,319 @@
+#include "argon2-avx512f.h"
+
+#ifdef HAVE_AVX512F
+#include <stdint.h>
+#include <string.h>
+
+#ifdef __GNUC__
+#   include <x86intrin.h>
+#else
+#   include <intrin.h>
+#endif
+
+#define ror64(x, n) _mm512_ror_epi64((x), (n))
+
+static __m512i f(__m512i x, __m512i y)
+{
+    __m512i z = _mm512_mul_epu32(x, y);
+    return _mm512_add_epi64(_mm512_add_epi64(x, y), _mm512_add_epi64(z, z));
+}
+
+#define G1(A0, B0, C0, D0, A1, B1, C1, D1) \
+    do { \
+        A0 = f(A0, B0); \
+        A1 = f(A1, B1); \
+\
+        D0 = _mm512_xor_si512(D0, A0); \
+        D1 = _mm512_xor_si512(D1, A1); \
+\
+        D0 = ror64(D0, 32); \
+        D1 = ror64(D1, 32); \
+\
+        C0 = f(C0, D0); \
+        C1 = f(C1, D1); \
+\
+        B0 = _mm512_xor_si512(B0, C0); \
+        B1 = _mm512_xor_si512(B1, C1); \
+\
+        B0 = ror64(B0, 24); \
+        B1 = ror64(B1, 24); \
+    } while ((void)0, 0)
+
+#define G2(A0, B0, C0, D0, A1, B1, C1, D1) \
+    do { \
+        A0 = f(A0, B0); \
+        A1 = f(A1, B1); \
+\
+        D0 = _mm512_xor_si512(D0, A0); \
+        D1 = _mm512_xor_si512(D1, A1); \
+\
+        D0 = ror64(D0, 16); \
+        D1 = ror64(D1, 16); \
+\
+        C0 = f(C0, D0); \
+        C1 = f(C1, D1); \
+\
+        B0 = _mm512_xor_si512(B0, C0); \
+        B1 = _mm512_xor_si512(B1, C1); \
+\
+        B0 = ror64(B0, 63); \
+        B1 = ror64(B1, 63); \
+    } while ((void)0, 0)
+
+#define DIAGONALIZE(A0, B0, C0, D0, A1, B1, C1, D1) \
+    do { \
+        B0 = _mm512_permutex_epi64(B0, _MM_SHUFFLE(0, 3, 2, 1)); \
+        B1 = _mm512_permutex_epi64(B1, _MM_SHUFFLE(0, 3, 2, 1)); \
+\
+        C0 = _mm512_permutex_epi64(C0, _MM_SHUFFLE(1, 0, 3, 2)); \
+        C1 = _mm512_permutex_epi64(C1, _MM_SHUFFLE(1, 0, 3, 2)); \
+\
+        D0 = _mm512_permutex_epi64(D0, _MM_SHUFFLE(2, 1, 0, 3)); \
+        D1 = _mm512_permutex_epi64(D1, _MM_SHUFFLE(2, 1, 0, 3)); \
+    } while ((void)0, 0)
+
+#define UNDIAGONALIZE(A0, B0, C0, D0, A1, B1, C1, D1) \
+    do { \
+        B0 = _mm512_permutex_epi64(B0, _MM_SHUFFLE(2, 1, 0, 3)); \
+        B1 = _mm512_permutex_epi64(B1, _MM_SHUFFLE(2, 1, 0, 3)); \
+\
+        C0 = _mm512_permutex_epi64(C0, _MM_SHUFFLE(1, 0, 3, 2)); \
+        C1 = _mm512_permutex_epi64(C1, _MM_SHUFFLE(1, 0, 3, 2)); \
+\
+        D0 = _mm512_permutex_epi64(D0, _MM_SHUFFLE(0, 3, 2, 1)); \
+        D1 = _mm512_permutex_epi64(D1, _MM_SHUFFLE(0, 3, 2, 1)); \
+    } while ((void)0, 0)
+
+#define BLAKE2_ROUND(A0, B0, C0, D0, A1, B1, C1, D1) \
+    do { \
+        G1(A0, B0, C0, D0, A1, B1, C1, D1); \
+        G2(A0, B0, C0, D0, A1, B1, C1, D1); \
+\
+        DIAGONALIZE(A0, B0, C0, D0, A1, B1, C1, D1); \
+\
+        G1(A0, B0, C0, D0, A1, B1, C1, D1); \
+        G2(A0, B0, C0, D0, A1, B1, C1, D1); \
+\
+        UNDIAGONALIZE(A0, B0, C0, D0, A1, B1, C1, D1); \
+    } while ((void)0, 0)
+
+#define SWAP_HALVES(A0, A1) \
+    do { \
+        __m512i t0, t1; \
+        t0 = _mm512_shuffle_i64x2(A0, A1, _MM_SHUFFLE(1, 0, 1, 0)); \
+        t1 = _mm512_shuffle_i64x2(A0, A1, _MM_SHUFFLE(3, 2, 3, 2)); \
+        A0 = t0; \
+        A1 = t1; \
+    } while((void)0, 0)
+
+#define SWAP_QUARTERS(A0, A1) \
+    do { \
+        SWAP_HALVES(A0, A1); \
+        A0 = _mm512_permutexvar_epi64(_mm512_setr_epi64(0, 1, 4, 5, 2, 3, 6, 7), A0); \
+        A1 = _mm512_permutexvar_epi64(_mm512_setr_epi64(0, 1, 4, 5, 2, 3, 6, 7), A1); \
+    } while((void)0, 0)
+
+#define UNSWAP_QUARTERS(A0, A1) \
+    do { \
+        A0 = _mm512_permutexvar_epi64(_mm512_setr_epi64(0, 1, 4, 5, 2, 3, 6, 7), A0); \
+        A1 = _mm512_permutexvar_epi64(_mm512_setr_epi64(0, 1, 4, 5, 2, 3, 6, 7), A1); \
+        SWAP_HALVES(A0, A1); \
+    } while((void)0, 0)
+
+#define BLAKE2_ROUND1(A0, C0, B0, D0, A1, C1, B1, D1) \
+    do { \
+        SWAP_HALVES(A0, B0); \
+        SWAP_HALVES(C0, D0); \
+        SWAP_HALVES(A1, B1); \
+        SWAP_HALVES(C1, D1); \
+        BLAKE2_ROUND(A0, B0, C0, D0, A1, B1, C1, D1); \
+        SWAP_HALVES(A0, B0); \
+        SWAP_HALVES(C0, D0); \
+        SWAP_HALVES(A1, B1); \
+        SWAP_HALVES(C1, D1); \
+    } while ((void)0, 0)
+
+#define BLAKE2_ROUND2(A0, A1, B0, B1, C0, C1, D0, D1) \
+    do { \
+        SWAP_QUARTERS(A0, A1); \
+        SWAP_QUARTERS(B0, B1); \
+        SWAP_QUARTERS(C0, C1); \
+        SWAP_QUARTERS(D0, D1); \
+        BLAKE2_ROUND(A0, B0, C0, D0, A1, B1, C1, D1); \
+        UNSWAP_QUARTERS(A0, A1); \
+        UNSWAP_QUARTERS(B0, B1); \
+        UNSWAP_QUARTERS(C0, C1); \
+        UNSWAP_QUARTERS(D0, D1); \
+    } while ((void)0, 0)
+
+enum {
+    ARGON2_VECS_IN_BLOCK = ARGON2_OWORDS_IN_BLOCK / 4,
+};
+
+static void fill_block(__m512i *s, const block *ref_block, block *next_block,
+                       int with_xor)
+{
+    __m512i block_XY[ARGON2_VECS_IN_BLOCK];
+    unsigned int i;
+
+    if (with_xor) {
+        for (i = 0; i < ARGON2_VECS_IN_BLOCK; i++) {
+            s[i] =_mm512_xor_si512(
+                s[i], _mm512_loadu_si512((const __m512i *)ref_block->v + i));
+            block_XY[i] = _mm512_xor_si512(
+                s[i], _mm512_loadu_si512((const __m512i *)next_block->v + i));
+        }
+
+    } else {
+        for (i = 0; i < ARGON2_VECS_IN_BLOCK; i++) {
+            block_XY[i] = s[i] =_mm512_xor_si512(
+                s[i], _mm512_loadu_si512((const __m512i *)ref_block->v + i));
+        }
+    }
+
+    for (i = 0; i < 2; ++i) {
+        BLAKE2_ROUND1(
+            s[8 * i + 0], s[8 * i + 1], s[8 * i + 2], s[8 * i + 3],
+            s[8 * i + 4], s[8 * i + 5], s[8 * i + 6], s[8 * i + 7]);
+    }
+
+    for (i = 0; i < 2; ++i) {
+        BLAKE2_ROUND2(
+            s[2 * 0 + i], s[2 * 1 + i], s[2 * 2 + i], s[2 * 3 + i],
+            s[2 * 4 + i], s[2 * 5 + i], s[2 * 6 + i], s[2 * 7 + i]);
+    }
+
+    for (i = 0; i < ARGON2_VECS_IN_BLOCK; i++) {
+        s[i] = _mm512_xor_si512(s[i], block_XY[i]);
+        _mm512_storeu_si512((__m512i *)next_block->v + i, s[i]);
+    }
+}
+
+static void next_addresses(block *address_block, block *input_block)
+{
+    /*Temporary zero-initialized blocks*/
+    __m512i zero_block[ARGON2_VECS_IN_BLOCK];
+    __m512i zero2_block[ARGON2_VECS_IN_BLOCK];
+
+    memset(zero_block, 0, sizeof(zero_block));
+    memset(zero2_block, 0, sizeof(zero2_block));
+
+    /*Increasing index counter*/
+    input_block->v[6]++;
+
+    /*First iteration of G*/
+    fill_block(zero_block, input_block, address_block, 0);
+
+    /*Second iteration of G*/
+    fill_block(zero2_block, address_block, address_block, 0);
+}
+
+void xmrig_ar2_fill_segment_avx512f(const argon2_instance_t *instance, argon2_position_t position)
+{
+    block *ref_block = NULL, *curr_block = NULL;
+    block address_block, input_block;
+    uint64_t pseudo_rand, ref_index, ref_lane;
+    uint32_t prev_offset, curr_offset;
+    uint32_t starting_index, i;
+    __m512i state[ARGON2_VECS_IN_BLOCK];
+    int data_independent_addressing;
+
+    if (instance == NULL) {
+        return;
+    }
+
+    data_independent_addressing = (instance->type == Argon2_i) ||
+            (instance->type == Argon2_id && (position.pass == 0) &&
+             (position.slice < ARGON2_SYNC_POINTS / 2));
+
+    if (data_independent_addressing) {
+        init_block_value(&input_block, 0);
+
+        input_block.v[0] = position.pass;
+        input_block.v[1] = position.lane;
+        input_block.v[2] = position.slice;
+        input_block.v[3] = instance->memory_blocks;
+        input_block.v[4] = instance->passes;
+        input_block.v[5] = instance->type;
+    }
+
+    starting_index = 0;
+
+    if ((0 == position.pass) && (0 == position.slice)) {
+        starting_index = 2; /* we have already generated the first two blocks */
+
+        /* Don't forget to generate the first block of addresses: */
+        if (data_independent_addressing) {
+            next_addresses(&address_block, &input_block);
+        }
+    }
+
+    /* Offset of the current block */
+    curr_offset = position.lane * instance->lane_length +
+                  position.slice * instance->segment_length + starting_index;
+
+    if (0 == curr_offset % instance->lane_length) {
+        /* Last block in this lane */
+        prev_offset = curr_offset + instance->lane_length - 1;
+    } else {
+        /* Previous block */
+        prev_offset = curr_offset - 1;
+    }
+
+    memcpy(state, ((instance->memory + prev_offset)->v), ARGON2_BLOCK_SIZE);
+
+    for (i = starting_index; i < instance->segment_length;
+         ++i, ++curr_offset, ++prev_offset) {
+        /*1.1 Rotating prev_offset if needed */
+        if (curr_offset % instance->lane_length == 1) {
+            prev_offset = curr_offset - 1;
+        }
+
+        /* 1.2 Computing the index of the reference block */
+        /* 1.2.1 Taking pseudo-random value from the previous block */
+        if (data_independent_addressing) {
+            if (i % ARGON2_ADDRESSES_IN_BLOCK == 0) {
+                next_addresses(&address_block, &input_block);
+            }
+            pseudo_rand = address_block.v[i % ARGON2_ADDRESSES_IN_BLOCK];
+        } else {
+            pseudo_rand = instance->memory[prev_offset].v[0];
+        }
+
+        /* 1.2.2 Computing the lane of the reference block */
+        ref_lane = ((pseudo_rand >> 32)) % instance->lanes;
+
+        if ((position.pass == 0) && (position.slice == 0)) {
+            /* Can not reference other lanes yet */
+            ref_lane = position.lane;
+        }
+
+        /* 1.2.3 Computing the number of possible reference block within the
+         * lane.
+         */
+        position.index = i;
+        ref_index = xmrig_ar2_index_alpha(instance, &position, pseudo_rand & 0xFFFFFFFF, ref_lane == position.lane);
+
+        /* 2 Creating a new block */
+        ref_block =
+            instance->memory + instance->lane_length * ref_lane + ref_index;
+        curr_block = instance->memory + curr_offset;
+
+        /* version 1.2.1 and earlier: overwrite, not XOR */
+        if (0 == position.pass || ARGON2_VERSION_10 == instance->version) {
+            fill_block(state, ref_block, curr_block, 0);
+        } else {
+            fill_block(state, ref_block, curr_block, 1);
+        }
+    }
+}
+
+extern int cpu_flags_has_avx512f(void);
+int xmrig_ar2_check_avx512f(void) { return cpu_flags_has_avx512f(); }
+
+#else
+
+void xmrig_ar2_fill_segment_avx512f(const argon2_instance_t *instance, argon2_position_t position) {}
+int xmrig_ar2_check_avx512f(void) { return 0; }
+
+#endif

src/3rdparty/argon2/arch/x86_64/lib/argon2-avx512f.h

@@ -0,0 +1,9 @@
+#ifndef ARGON2_AVX512F_H
+#define ARGON2_AVX512F_H
+
+#include "core.h"
+
+void xmrig_ar2_fill_segment_avx512f(const argon2_instance_t *instance, argon2_position_t position);
+int xmrig_ar2_check_avx512f(void);
+
+#endif // ARGON2_AVX512F_H

src/3rdparty/argon2/arch/x86_64/lib/argon2-sse2.c

@@ -0,0 +1,116 @@
+#include "argon2-sse2.h"
+
+#ifdef HAVE_SSE2
+#ifdef __GNUC__
+#   include <x86intrin.h>
+#else
+#   include <intrin.h>
+#endif
+
+#define ror64_16(x) \
+    _mm_shufflehi_epi16( \
+        _mm_shufflelo_epi16((x), _MM_SHUFFLE(0, 3, 2, 1)), \
+        _MM_SHUFFLE(0, 3, 2, 1))
+#define ror64_24(x) \
+    _mm_xor_si128(_mm_srli_epi64((x), 24), _mm_slli_epi64((x), 40))
+#define ror64_32(x) _mm_shuffle_epi32((x), _MM_SHUFFLE(2, 3, 0, 1))
+#define ror64_63(x) \
+    _mm_xor_si128(_mm_srli_epi64((x), 63), _mm_add_epi64((x), (x)))
+
+static __m128i f(__m128i x, __m128i y)
+{
+    __m128i z = _mm_mul_epu32(x, y);
+    return _mm_add_epi64(_mm_add_epi64(x, y), _mm_add_epi64(z, z));
+}
+
+#define G1(A0, B0, C0, D0, A1, B1, C1, D1) \
+    do { \
+        A0 = f(A0, B0); \
+        A1 = f(A1, B1); \
+\
+        D0 = _mm_xor_si128(D0, A0); \
+        D1 = _mm_xor_si128(D1, A1); \
+\
+        D0 = ror64_32(D0); \
+        D1 = ror64_32(D1); \
+\
+        C0 = f(C0, D0); \
+        C1 = f(C1, D1); \
+\
+        B0 = _mm_xor_si128(B0, C0); \
+        B1 = _mm_xor_si128(B1, C1); \
+\
+        B0 = ror64_24(B0); \
+        B1 = ror64_24(B1); \
+    } while ((void)0, 0)
+
+#define G2(A0, B0, C0, D0, A1, B1, C1, D1) \
+    do { \
+        A0 = f(A0, B0); \
+        A1 = f(A1, B1); \
+\
+        D0 = _mm_xor_si128(D0, A0); \
+        D1 = _mm_xor_si128(D1, A1); \
+\
+        D0 = ror64_16(D0); \
+        D1 = ror64_16(D1); \
+\
+        C0 = f(C0, D0); \
+        C1 = f(C1, D1); \
+\
+        B0 = _mm_xor_si128(B0, C0); \
+        B1 = _mm_xor_si128(B1, C1); \
+\
+        B0 = ror64_63(B0); \
+        B1 = ror64_63(B1); \
+    } while ((void)0, 0)
+
+#define DIAGONALIZE(A0, B0, C0, D0, A1, B1, C1, D1) \
+    do { \
+        __m128i t0 = D0; \
+        __m128i t1 = B0; \
+        D0 = _mm_unpackhi_epi64(D1, _mm_unpacklo_epi64(t0, t0)); \
+        D1 = _mm_unpackhi_epi64(t0, _mm_unpacklo_epi64(D1, D1)); \
+        B0 = _mm_unpackhi_epi64(B0, _mm_unpacklo_epi64(B1, B1)); \
+        B1 = _mm_unpackhi_epi64(B1, _mm_unpacklo_epi64(t1, t1)); \
+    } while ((void)0, 0)
+
+#define UNDIAGONALIZE(A0, B0, C0, D0, A1, B1, C1, D1) \
+    do { \
+        __m128i t0 = B0; \
+        __m128i t1 = D0; \
+        B0 = _mm_unpackhi_epi64(B1, _mm_unpacklo_epi64(B0, B0)); \
+        B1 = _mm_unpackhi_epi64(t0, _mm_unpacklo_epi64(B1, B1)); \
+        D0 = _mm_unpackhi_epi64(D0, _mm_unpacklo_epi64(D1, D1)); \
+        D1 = _mm_unpackhi_epi64(D1, _mm_unpacklo_epi64(t1, t1)); \
+    } while ((void)0, 0)
+
+#define BLAKE2_ROUND(A0, A1, B0, B1, C0, C1, D0, D1) \
+    do { \
+        G1(A0, B0, C0, D0, A1, B1, C1, D1); \
+        G2(A0, B0, C0, D0, A1, B1, C1, D1); \
+\
+        DIAGONALIZE(A0, B0, C0, D0, A1, B1, C1, D1); \
+\
+        G1(A0, B0, C1, D0, A1, B1, C0, D1); \
+        G2(A0, B0, C1, D0, A1, B1, C0, D1); \
+\
+        UNDIAGONALIZE(A0, B0, C0, D0, A1, B1, C1, D1); \
+    } while ((void)0, 0)
+
+#include "argon2-template-128.h"
+
+void xmrig_ar2_fill_segment_sse2(const argon2_instance_t *instance, argon2_position_t position)
+{
+    fill_segment_128(instance, position);
+}
+
+extern int cpu_flags_has_sse2(void);
+int xmrig_ar2_check_sse2(void) { return cpu_flags_has_sse2(); }
+
+#else
+
+void xmrig_ar2_fill_segment_sse2(const argon2_instance_t *instance, argon2_position_t position) {}
+int xmrig_ar2_check_sse2(void) { return 0; }
+
+#endif

src/3rdparty/argon2/arch/x86_64/lib/argon2-sse2.h

@@ -0,0 +1,9 @@
+#ifndef ARGON2_SSE2_H
+#define ARGON2_SSE2_H
+
+#include "core.h"
+
+void xmrig_ar2_fill_segment_sse2(const argon2_instance_t *instance, argon2_position_t position);
+int xmrig_ar2_check_sse2(void);
+
+#endif // ARGON2_SSE2_H

src/3rdparty/argon2/arch/x86_64/lib/argon2-ssse3.c

@@ -0,0 +1,128 @@
+#include "argon2-ssse3.h"
+
+#ifdef HAVE_SSSE3
+#include <string.h>
+
+#ifdef __GNUC__
+#   include <x86intrin.h>
+#else
+#   include <intrin.h>
+#endif
+
+#define r16 (_mm_setr_epi8( \
+     2,  3,  4,  5,  6,  7,  0,  1, \
+    10, 11, 12, 13, 14, 15,  8,  9))
+
+#define r24 (_mm_setr_epi8( \
+     3,  4,  5,  6,  7,  0,  1,  2, \
+    11, 12, 13, 14, 15,  8,  9, 10))
+
+#define ror64_16(x) _mm_shuffle_epi8((x), r16)
+#define ror64_24(x) _mm_shuffle_epi8((x), r24)
+#define ror64_32(x) _mm_shuffle_epi32((x), _MM_SHUFFLE(2, 3, 0, 1))
+#define ror64_63(x) \
+    _mm_xor_si128(_mm_srli_epi64((x), 63), _mm_add_epi64((x), (x)))
+
+static __m128i f(__m128i x, __m128i y)
+{
+    __m128i z = _mm_mul_epu32(x, y);
+    return _mm_add_epi64(_mm_add_epi64(x, y), _mm_add_epi64(z, z));
+}
+
+#define G1(A0, B0, C0, D0, A1, B1, C1, D1) \
+    do { \
+        A0 = f(A0, B0); \
+        A1 = f(A1, B1); \
+\
+        D0 = _mm_xor_si128(D0, A0); \
+        D1 = _mm_xor_si128(D1, A1); \
+\
+        D0 = ror64_32(D0); \
+        D1 = ror64_32(D1); \
+\
+        C0 = f(C0, D0); \
+        C1 = f(C1, D1); \
+\
+        B0 = _mm_xor_si128(B0, C0); \
+        B1 = _mm_xor_si128(B1, C1); \
+\
+        B0 = ror64_24(B0); \
+        B1 = ror64_24(B1); \
+    } while ((void)0, 0)
+
+#define G2(A0, B0, C0, D0, A1, B1, C1, D1) \
+    do { \
+        A0 = f(A0, B0); \
+        A1 = f(A1, B1); \
+\
+        D0 = _mm_xor_si128(D0, A0); \
+        D1 = _mm_xor_si128(D1, A1); \
+\
+        D0 = ror64_16(D0); \
+        D1 = ror64_16(D1); \
+\
+        C0 = f(C0, D0); \
+        C1 = f(C1, D1); \
+\
+        B0 = _mm_xor_si128(B0, C0); \
+        B1 = _mm_xor_si128(B1, C1); \
+\
+        B0 = ror64_63(B0); \
+        B1 = ror64_63(B1); \
+    } while ((void)0, 0)
+
+#define DIAGONALIZE(A0, B0, C0, D0, A1, B1, C1, D1) \
+    do { \
+        __m128i t0 = _mm_alignr_epi8(B1, B0, 8); \
+        __m128i t1 = _mm_alignr_epi8(B0, B1, 8); \
+        B0 = t0; \
+        B1 = t1; \
+\
+        t0 = _mm_alignr_epi8(D1, D0, 8); \
+        t1 = _mm_alignr_epi8(D0, D1, 8); \
+        D0 = t1; \
+        D1 = t0; \
+    } while ((void)0, 0)
+
+#define UNDIAGONALIZE(A0, B0, C0, D0, A1, B1, C1, D1) \
+    do { \
+        __m128i t0 = _mm_alignr_epi8(B0, B1, 8); \
+        __m128i t1 = _mm_alignr_epi8(B1, B0, 8); \
+        B0 = t0; \
+        B1 = t1; \
+\
+        t0 = _mm_alignr_epi8(D0, D1, 8); \
+        t1 = _mm_alignr_epi8(D1, D0, 8); \
+        D0 = t1; \
+        D1 = t0; \
+    } while ((void)0, 0)
+
+#define BLAKE2_ROUND(A0, A1, B0, B1, C0, C1, D0, D1) \
+    do { \
+        G1(A0, B0, C0, D0, A1, B1, C1, D1); \
+        G2(A0, B0, C0, D0, A1, B1, C1, D1); \
+\
+        DIAGONALIZE(A0, B0, C0, D0, A1, B1, C1, D1); \
+\
+        G1(A0, B0, C1, D0, A1, B1, C0, D1); \
+        G2(A0, B0, C1, D0, A1, B1, C0, D1); \
+\
+        UNDIAGONALIZE(A0, B0, C0, D0, A1, B1, C1, D1); \
+    } while ((void)0, 0)
+
+#include "argon2-template-128.h"
+
+void xmrig_ar2_fill_segment_ssse3(const argon2_instance_t *instance, argon2_position_t position)
+{
+    fill_segment_128(instance, position);
+}
+
+extern int cpu_flags_has_ssse3(void);
+int xmrig_ar2_check_ssse3(void) { return cpu_flags_has_ssse3(); }
+
+#else
+
+void xmrig_ar2_fill_segment_ssse3(const argon2_instance_t *instance, argon2_position_t position) {}
+int xmrig_ar2_check_ssse3(void) { return 0; }
+
+#endif

src/3rdparty/argon2/arch/x86_64/lib/argon2-ssse3.h

@@ -0,0 +1,9 @@
+#ifndef ARGON2_SSSE3_H
+#define ARGON2_SSSE3_H
+
+#include "core.h"
+
+void xmrig_ar2_fill_segment_ssse3(const argon2_instance_t *instance, argon2_position_t position);
+int xmrig_ar2_check_ssse3(void);
+
+#endif // ARGON2_SSSE3_H