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40 Commits

Author SHA1 Message Date
XMRig
8084ff37a5 v6.21.0 2023-11-23 20:40:58 +07:00
XMRig
7cf3db7750 Merge branch 'dev' 2023-11-23 20:40:34 +07:00
XMRig
4bda6e054d v6.21.0-dev 2023-11-23 19:51:41 +07:00
xmrig
64a0ed413b Merge pull request #3358 from SChernykh/dev
Zephyr solo mining: handle multiple outputs
2023-11-15 22:36:35 +07:00
SChernykh
0b59b7eb43 Zephyr solo mining: handle multiple outputs 2023-11-15 16:18:05 +01:00
xmrig
ae6b10b5a4 Merge pull request #3356 from SChernykh/dev
Updated pricing record size for Zephyr solo mining
2023-11-15 08:27:02 +07:00
SChernykh
705a7eac0c Updated pricing record size for Zephyr solo mining 2023-11-14 13:06:10 +01:00
xmrig
10bfffe033 Merge pull request #3348 from SChernykh/dev
Update to latest sse2neon.h
2023-10-31 11:52:38 +07:00
SChernykh
4131aa4754 Update sse2neon.h 2023-10-30 20:07:03 +01:00
xmrig
fee51b20fa Merge pull request #3346 from SChernykh/dev
ARM64 JIT: don't use `x18` register
2023-10-20 07:36:12 +07:00
SChernykh
5e66efabcf ARM64 JIT: don't use x18 register
From https://developer.apple.com/documentation/xcode/writing-arm64-code-for-apple-platforms
> The platforms reserve register x18. Don’t use this register.

This PR fixes invalid hashes when running on Apple silicon with the latest macOS SDK.
2023-10-19 17:45:15 +02:00
XMRig
08901a9a4b Merge branch 'JacksonZ03-main' into dev 2023-10-09 15:15:32 +07:00
XMRig
a19f590ee6 Merge branch 'main' of https://github.com/JacksonZ03/xmrig into JacksonZ03-main 2023-10-09 15:14:50 +07:00
Jackson Zheng
2fa754825d Update cn_main_loop.asm
Found this line to be missing. I looked through the history and seemed like the original author of the commit missed it out.
2023-10-08 23:29:52 +01:00
Jackson Zheng
f3446c0a94 Update cn_main_loop.asm
I was scanning the code and found this line to be missing. Not sure if this was a mistake or if it was intentionally left out?
2023-10-08 23:12:58 +01:00
xmrig
71209d4cd7 Merge pull request #3339 from SChernykh/dev
Added SNI option for TLS connections
2023-09-29 19:15:29 +07:00
SChernykh
0a3313cb76 Added SNI option for TLS connections
Disabled by default, add `"sni": true,` to pool config to enable it.
2023-09-29 08:33:49 +02:00
xmrig
e855723cd9 Merge pull request #3320 from SChernykh/dev
Add "built for OS/architecture/bits" to "ABOUT"
2023-08-21 19:00:14 +07:00
SChernykh
6e294bd046 Add "built for OS/architecture/bits" to "ABOUT"
To make it more clear what binary it is on some XMRig screenshot.
2023-08-21 13:49:21 +02:00
XMRig
dfe70d9ea7 Fixed huge pages availability info on Linux. 2023-08-08 17:48:44 +07:00
XMRig
2ecf10cdcb Make Platform::hasKeepalive() constexpr where always supported and code cleanup. 2023-08-06 20:26:07 +07:00
xmrig
b55ca8e547 Merge pull request #3312 from SChernykh/dev
Disable TCP keepalive before closing socket
2023-08-06 20:14:37 +07:00
SChernykh
12577df7ba Disable TCP keepalive before closing socket 2023-08-06 14:51:25 +02:00
xmrig
64f5bb467a Merge pull request #3302 from SChernykh/dev
Enabled keepalive for Windows (>= Vista)
2023-07-17 17:17:39 +07:00
SChernykh
5717e72367 Enabled keepalive for Windows (>= Vista) 2023-07-17 09:49:10 +02:00
XMRig
e7de104d88 v6.20.1-dev 2023-07-03 18:47:55 +07:00
XMRig
3b5e04b1b7 Merge branch 'master' into dev 2023-07-03 18:47:22 +07:00
XMRig
2e77faa80c v6.20.0 2023-07-03 12:42:00 +07:00
XMRig
6e63a246bf Merge branch 'dev' 2023-07-03 12:41:35 +07:00
XMRig
09abc81255 v6.20.0-dev 2023-07-03 12:37:36 +07:00
xmrig
fc698f7bcf Merge pull request #3291 from SChernykh/dev
Zephyr solo mining: fix for blocks with transactions
2023-06-24 20:22:53 +07:00
SChernykh
cb2f8fd453 Zephyr solo mining: fix for blocks with transactions 2023-06-24 15:15:37 +02:00
xmrig
59c6c42ceb Merge pull request #3290 from SChernykh/dev
Zephyr coin support
2023-06-24 19:53:54 +07:00
SChernykh
6c10cc5a4b Zephyr coin support
Solo mining will require `--coin Zephyr` in command line, or `"coin": "Zephyr",` in `pools` section of config.json
2023-06-24 14:37:20 +02:00
xmrig
d5a8f8a5ae Merge pull request #3288 from SChernykh/dev
KawPow: fixed data race when building programs
2023-06-19 17:40:24 +07:00
SChernykh
d94d052e6c KawPow: fixed data race when building programs
`uv_queue_work` can't be called from other threads, only `uv_async_send` is thread-safe.
2023-06-19 12:32:28 +02:00
XMRig
ae2b7e3348 Merge branch 'Spudz76-dev-addApiRebind' into dev 2023-06-07 20:49:34 +07:00
XMRig
7d7f30701f Code cleanup. 2023-06-07 20:48:56 +07:00
XMRig
e80fc25789 Merge branch 'dev-addApiRebind' of https://github.com/Spudz76/xmrig into Spudz76-dev-addApiRebind 2023-06-07 20:12:58 +07:00
Tony Butler
548fbb9f71 Add API rebind polling 2023-05-23 16:49:43 -06:00
27 changed files with 1258 additions and 902 deletions

View File

@@ -1,3 +1,22 @@
# v6.21.0
- [#3302](https://github.com/xmrig/xmrig/pull/3302) [#3312](https://github.com/xmrig/xmrig/pull/3312) Enabled keepalive for Windows (>= Vista).
- [#3320](https://github.com/xmrig/xmrig/pull/3320) Added "built for OS/architecture/bits" to "ABOUT".
- [#3339](https://github.com/xmrig/xmrig/pull/3339) Added SNI option for TLS connections.
- [#3342](https://github.com/xmrig/xmrig/pull/3342) Update `cn_main_loop.asm`.
- [#3346](https://github.com/xmrig/xmrig/pull/3346) ARM64 JIT: don't use `x18` register.
- [#3348](https://github.com/xmrig/xmrig/pull/3348) Update to latest `sse2neon.h`.
- [#3356](https://github.com/xmrig/xmrig/pull/3356) Updated pricing record size for **Zephyr** solo mining.
- [#3358](https://github.com/xmrig/xmrig/pull/3358) **Zephyr** solo mining: handle multiple outputs.
# v6.20.0
- Added new ARM CPU names.
- [#2394](https://github.com/xmrig/xmrig/pull/2394) Added new CMake options `ARM_V8` and `ARM_V7`.
- [#2830](https://github.com/xmrig/xmrig/pull/2830) Added API rebind polling.
- [#2927](https://github.com/xmrig/xmrig/pull/2927) Fixed compatibility with hwloc 1.11.x.
- [#3060](https://github.com/xmrig/xmrig/pull/3060) Added x86 to `README.md`.
- [#3236](https://github.com/xmrig/xmrig/pull/3236) Fixed: receive CUDA loader error on Linux too.
- [#3290](https://github.com/xmrig/xmrig/pull/3290) Added [Zephyr](https://www.zephyrprotocol.com/) coin support for solo mining.
# v6.19.3
- [#3245](https://github.com/xmrig/xmrig/issues/3245) Improved algorithm negotiation for donation rounds by sending extra information about current mining job.
- [#3254](https://github.com/xmrig/xmrig/pull/3254) Tweaked auto-tuning for Intel CPUs.

View File

@@ -399,6 +399,9 @@ private:
uv_loop_t* m_loop = nullptr;
uv_thread_t m_loopThread = {};
uv_async_t m_shutdownAsync = {};
uv_async_t m_batonAsync = {};
std::vector<KawPowBaton> m_batons;
static void loop(void* data)
{
@@ -419,19 +422,37 @@ void KawPowBuilder::build_async(const IOclRunner& runner, uint64_t period, uint3
if (!m_loop) {
m_loop = new uv_loop_t{};
uv_loop_init(m_loop);
uv_async_init(m_loop, &m_shutdownAsync, [](uv_async_t* handle) { uv_close(reinterpret_cast<uv_handle_t*>(handle), nullptr); });
uv_async_init(m_loop, &m_shutdownAsync, [](uv_async_t* handle)
{
KawPowBuilder* builder = reinterpret_cast<KawPowBuilder*>(handle->data);
uv_close(reinterpret_cast<uv_handle_t*>(&builder->m_shutdownAsync), nullptr);
uv_close(reinterpret_cast<uv_handle_t*>(&builder->m_batonAsync), nullptr);
});
uv_async_init(m_loop, &m_batonAsync, [](uv_async_t* handle)
{
std::vector<KawPowBaton> batons;
{
KawPowBuilder* b = reinterpret_cast<KawPowBuilder*>(handle->data);
std::lock_guard<std::mutex> lock(b->m_mutex);
batons = std::move(b->m_batons);
}
for (const KawPowBaton& baton : batons) {
builder.build(baton.runner, baton.period, baton.worksize);
}
});
m_shutdownAsync.data = this;
m_batonAsync.data = this;
uv_thread_create(&m_loopThread, loop, this);
}
KawPowBaton* baton = new KawPowBaton(runner, period, worksize);
uv_queue_work(m_loop, &baton->req,
[](uv_work_t* req) {
KawPowBaton* baton = static_cast<KawPowBaton*>(req->data);
builder.build(baton->runner, baton->period, baton->worksize);
},
[](uv_work_t* req, int) { delete static_cast<KawPowBaton*>(req->data); }
);
m_batons.emplace_back(runner, period, worksize);
uv_async_send(&m_batonAsync);
}

View File

@@ -1,6 +1,6 @@
/* XMRig
* Copyright (c) 2018-2021 SChernykh <https://github.com/SChernykh>
* Copyright (c) 2016-2021 XMRig <https://github.com/xmrig>, <support@xmrig.com>
* Copyright (c) 2018-2023 SChernykh <https://github.com/SChernykh>
* Copyright (c) 2016-2023 XMRig <https://github.com/xmrig>, <support@xmrig.com>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -123,6 +123,21 @@ void xmrig::Api::stop()
}
void xmrig::Api::tick()
{
# ifdef XMRIG_FEATURE_HTTP
if (m_httpd->isBound() || !m_base->config()->http().isEnabled()) {
return;
}
if (++m_ticks % 10 == 0) {
m_ticks = 0;
m_httpd->start();
}
# endif
}
void xmrig::Api::onConfigChanged(Config *config, Config *previousConfig)
{
if (config->apiId() != previousConfig->apiId()) {

View File

@@ -1,6 +1,6 @@
/* XMRig
* Copyright (c) 2018-2021 SChernykh <https://github.com/SChernykh>
* Copyright (c) 2016-2021 XMRig <https://github.com/xmrig>, <support@xmrig.com>
* Copyright (c) 2018-2023 SChernykh <https://github.com/SChernykh>
* Copyright (c) 2016-2023 XMRig <https://github.com/xmrig>, <support@xmrig.com>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -21,7 +21,6 @@
#include <vector>
#include <cstdint>
#include "base/kernel/interfaces/IBaseListener.h"
@@ -44,7 +43,7 @@ class Api : public IBaseListener
public:
XMRIG_DISABLE_COPY_MOVE_DEFAULT(Api)
Api(Base *base);
explicit Api(Base *base);
~Api() override;
inline const char *id() const { return m_id; }
@@ -54,6 +53,7 @@ public:
void request(const HttpData &req);
void start();
void stop();
void tick();
protected:
void onConfigChanged(Config *config, Config *previousConfig) override;
@@ -65,14 +65,15 @@ private:
Base *m_base;
char m_id[32]{};
String m_workerId;
const uint64_t m_timestamp;
Httpd *m_httpd = nullptr;
Httpd *m_httpd = nullptr;
std::vector<IApiListener *> m_listeners;
String m_workerId;
uint8_t m_ticks = 0;
};
} // namespace xmrig
#endif /* XMRIG_API_H */
#endif // XMRIG_API_H

View File

@@ -1,6 +1,6 @@
/* XMRig
* Copyright (c) 2018-2021 SChernykh <https://github.com/SChernykh>
* Copyright (c) 2016-2021 XMRig <https://github.com/xmrig>, <support@xmrig.com>
* Copyright (c) 2018-2023 SChernykh <https://github.com/SChernykh>
* Copyright (c) 2016-2023 XMRig <https://github.com/xmrig>, <support@xmrig.com>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -22,11 +22,6 @@
#include "base/kernel/interfaces/IBaseListener.h"
#include "base/net/http/HttpListener.h"
#include "base/tools/Object.h"
#include <cstdint>
#include <memory>
namespace xmrig {
@@ -43,9 +38,11 @@ class Httpd : public IBaseListener, public IHttpListener
public:
XMRIG_DISABLE_COPY_MOVE_DEFAULT(Httpd)
Httpd(Base *base);
explicit Httpd(Base *base);
~Httpd() override;
inline bool isBound() const { return m_server != nullptr; }
bool start();
void stop();
@@ -69,7 +66,7 @@ private:
};
} /* namespace xmrig */
} // namespace xmrig
#endif /* XMRIG_HTTPD_H */
#endif // XMRIG_HTTPD_H

View File

@@ -53,6 +53,7 @@ static const CoinInfo coinInfo[] = {
{ Algorithm::RX_KEVA, "KVA", "Kevacoin", 0, 0, MAGENTA_BG_BOLD(WHITE_BOLD_S " keva ") },
{ Algorithm::KAWPOW_RVN, "RVN", "Ravencoin", 0, 0, BLUE_BG_BOLD( WHITE_BOLD_S " raven ") },
{ Algorithm::RX_WOW, "WOW", "Wownero", 300, 100000000000, MAGENTA_BG_BOLD(WHITE_BOLD_S " wownero ") },
{ Algorithm::RX_0, "ZEPH", "Zephyr", 120, 1000000000000, BLUE_BG_BOLD( WHITE_BOLD_S " zephyr ") },
};

View File

@@ -39,6 +39,7 @@ public:
KEVA,
RAVEN,
WOWNERO,
ZEPHYR,
MAX
};

View File

@@ -1,6 +1,6 @@
/* XMRig
* Copyright (c) 2018-2021 SChernykh <https://github.com/SChernykh>
* Copyright (c) 2016-2021 XMRig <https://github.com/xmrig>, <support@xmrig.com>
* Copyright (c) 2018-2023 SChernykh <https://github.com/SChernykh>
* Copyright (c) 2016-2023 XMRig <https://github.com/xmrig>, <support@xmrig.com>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -49,6 +49,12 @@ public:
static inline bool isUserActive(uint64_t ms) { return idleTime() < ms; }
static inline const String &userAgent() { return m_userAgent; }
# ifdef XMRIG_OS_WIN
static bool hasKeepalive();
# else
static constexpr bool hasKeepalive() { return true; }
# endif
static bool isOnBatteryPower();
static uint64_t idleTime();

View File

@@ -1,6 +1,6 @@
/* XMRig
* Copyright (c) 2018-2021 SChernykh <https://github.com/SChernykh>
* Copyright (c) 2016-2021 XMRig <https://github.com/xmrig>, <support@xmrig.com>
* Copyright (c) 2018-2023 SChernykh <https://github.com/SChernykh>
* Copyright (c) 2016-2023 XMRig <https://github.com/xmrig>, <support@xmrig.com>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -16,7 +16,6 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <algorithm>
#include <winsock2.h>
#include <windows.h>
@@ -70,6 +69,12 @@ char *xmrig::Platform::createUserAgent()
}
bool xmrig::Platform::hasKeepalive()
{
return winOsVersion().dwMajorVersion >= 6;
}
#ifndef XMRIG_FEATURE_HWLOC
bool xmrig::Platform::setThreadAffinity(uint64_t cpu_id)
{

View File

@@ -142,7 +142,7 @@ void xmrig::BaseConfig::printVersions()
snprintf(buf, sizeof buf, "MSVC/%d", MSVC_VERSION);
# endif
Log::print(GREEN_BOLD(" * ") WHITE_BOLD("%-13s") CYAN_BOLD("%s/%s") WHITE_BOLD(" %s"), "ABOUT", APP_NAME, APP_VERSION, buf);
Log::print(GREEN_BOLD(" * ") WHITE_BOLD("%-13s") CYAN_BOLD("%s/%s") WHITE_BOLD(" %s") WHITE_BOLD(" (built for %s") WHITE_BOLD(" %s,") WHITE_BOLD(" %s)"), "ABOUT", APP_NAME, APP_VERSION, buf, APP_OS, APP_ARCH, APP_BITS);
std::string libs;

View File

@@ -1,7 +1,7 @@
/* XMRig
* Copyright (c) 2019 jtgrassie <https://github.com/jtgrassie>
* Copyright (c) 2018-2021 SChernykh <https://github.com/SChernykh>
* Copyright (c) 2016-2021 XMRig <https://github.com/xmrig>, <support@xmrig.com>
* Copyright (c) 2018-2023 SChernykh <https://github.com/SChernykh>
* Copyright (c) 2016-2023 XMRig <https://github.com/xmrig>, <support@xmrig.com>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -42,13 +42,14 @@
#include "base/io/json/JsonRequest.h"
#include "base/io/log/Log.h"
#include "base/kernel/interfaces/IClientListener.h"
#include "base/kernel/Platform.h"
#include "base/net/dns/Dns.h"
#include "base/net/dns/DnsRecords.h"
#include "base/net/stratum/Socks5.h"
#include "base/net/tools/NetBuffer.h"
#include "base/tools/Chrono.h"
#include "base/tools/Cvt.h"
#include "base/tools/cryptonote/BlobReader.h"
#include "base/tools/Cvt.h"
#include "net/JobResult.h"
@@ -343,6 +344,9 @@ bool xmrig::Client::close()
setState(ClosingState);
if (uv_is_closing(reinterpret_cast<uv_handle_t*>(m_socket)) == 0) {
if (Platform::hasKeepalive()) {
uv_tcp_keepalive(m_socket, 0, 60);
}
uv_close(reinterpret_cast<uv_handle_t*>(m_socket), Client::onClose);
}
@@ -567,9 +571,9 @@ void xmrig::Client::connect(const sockaddr *addr)
uv_tcp_init(uv_default_loop(), m_socket);
uv_tcp_nodelay(m_socket, 1);
# ifndef WIN32
uv_tcp_keepalive(m_socket, 1, 60);
# endif
if (Platform::hasKeepalive()) {
uv_tcp_keepalive(m_socket, 1, 60);
}
uv_tcp_connect(req, m_socket, addr, onConnect);
}
@@ -585,7 +589,7 @@ void xmrig::Client::handshake()
if (isTLS()) {
m_expire = Chrono::steadyMSecs() + kResponseTimeout;
m_tls->handshake();
m_tls->handshake(m_pool.isSNI() ? m_pool.host().data() : nullptr);
}
else
# endif

View File

@@ -1,13 +1,13 @@
/* XMRig
* Copyright 2010 Jeff Garzik <jgarzik@pobox.com>
* Copyright 2012-2014 pooler <pooler@litecoinpool.org>
* Copyright 2014 Lucas Jones <https://github.com/lucasjones>
* Copyright 2014-2016 Wolf9466 <https://github.com/OhGodAPet>
* Copyright 2016 Jay D Dee <jayddee246@gmail.com>
* Copyright 2017-2018 XMR-Stak <https://github.com/fireice-uk>, <https://github.com/psychocrypt>
* Copyright 2019 Howard Chu <https://github.com/hyc>
* Copyright 2018-2020 SChernykh <https://github.com/SChernykh>
* Copyright 2016-2020 XMRig <https://github.com/xmrig>, <support@xmrig.com>
* Copyright (c) 2010 Jeff Garzik <jgarzik@pobox.com>
* Copyright (c) 2012-2014 pooler <pooler@litecoinpool.org>
* Copyright (c) 2014 Lucas Jones <https://github.com/lucasjones>
* Copyright (c) 2014-2016 Wolf9466 <https://github.com/OhGodAPet>
* Copyright (c) 2016 Jay D Dee <jayddee246@gmail.com>
* Copyright (c) 2017-2018 XMR-Stak <https://github.com/fireice-uk>, <https://github.com/psychocrypt>
* Copyright (c) 2019 Howard Chu <https://github.com/hyc>
* Copyright (c) 2018-2023 SChernykh <https://github.com/SChernykh>
* Copyright (c) 2016-2023 XMRig <https://github.com/xmrig>, <support@xmrig.com>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -23,7 +23,6 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <uv.h>
@@ -34,6 +33,7 @@
#include "base/io/json/JsonRequest.h"
#include "base/io/log/Log.h"
#include "base/kernel/interfaces/IClientListener.h"
#include "base/kernel/Platform.h"
#include "base/net/dns/Dns.h"
#include "base/net/dns/DnsRecords.h"
#include "base/net/http/Fetch.h"
@@ -42,9 +42,9 @@
#include "base/net/stratum/SubmitResult.h"
#include "base/net/tools/NetBuffer.h"
#include "base/tools/bswap_64.h"
#include "base/tools/cryptonote/Signatures.h"
#include "base/tools/Cvt.h"
#include "base/tools/Timer.h"
#include "base/tools/cryptonote/Signatures.h"
#include "net/JobResult.h"
@@ -358,9 +358,9 @@ void xmrig::DaemonClient::onResolved(const DnsRecords &records, int status, cons
uv_tcp_init(uv_default_loop(), s);
uv_tcp_nodelay(s, 1);
# ifndef WIN32
uv_tcp_keepalive(s, 1, 60);
# endif
if (Platform::hasKeepalive()) {
uv_tcp_keepalive(s, 1, 60);
}
if (m_pool.zmq_port() > 0) {
delete m_ZMQSocket;
@@ -589,6 +589,9 @@ void xmrig::DaemonClient::retry()
}
if ((m_ZMQConnectionState != ZMQ_NOT_CONNECTED) && (m_ZMQConnectionState != ZMQ_DISCONNECTING)) {
if (Platform::hasKeepalive()) {
uv_tcp_keepalive(m_ZMQSocket, 0, 60);
}
uv_close(reinterpret_cast<uv_handle_t*>(m_ZMQSocket), onZMQClose);
}
@@ -916,6 +919,9 @@ bool xmrig::DaemonClient::ZMQClose(bool shutdown)
m_ZMQConnectionState = ZMQ_DISCONNECTING;
if (uv_is_closing(reinterpret_cast<uv_handle_t*>(m_ZMQSocket)) == 0) {
if (Platform::hasKeepalive()) {
uv_tcp_keepalive(m_ZMQSocket, 0, 60);
}
uv_close(reinterpret_cast<uv_handle_t*>(m_ZMQSocket), shutdown ? onZMQShutdown : onZMQClose);
if (!shutdown) {
retry();

View File

@@ -77,6 +77,7 @@ const char *Pool::kSelfSelect = "self-select";
const char *Pool::kSOCKS5 = "socks5";
const char *Pool::kSubmitToOrigin = "submit-to-origin";
const char *Pool::kTls = "tls";
const char *Pool::kSni = "sni";
const char *Pool::kUrl = "url";
const char *Pool::kUser = "user";
const char *Pool::kSpendSecretKey = "spend-secret-key";
@@ -137,6 +138,7 @@ xmrig::Pool::Pool(const rapidjson::Value &object) :
m_flags.set(FLAG_ENABLED, Json::getBool(object, kEnabled, true));
m_flags.set(FLAG_NICEHASH, Json::getBool(object, kNicehash) || m_url.host().contains(kNicehashHost));
m_flags.set(FLAG_TLS, Json::getBool(object, kTls) || m_url.isTLS());
m_flags.set(FLAG_SNI, Json::getBool(object, kSni));
setKeepAlive(Json::getValue(object, kKeepalive));
@@ -299,6 +301,7 @@ rapidjson::Value xmrig::Pool::toJSON(rapidjson::Document &doc) const
obj.AddMember(StringRef(kEnabled), m_flags.test(FLAG_ENABLED), allocator);
obj.AddMember(StringRef(kTls), isTLS(), allocator);
obj.AddMember(StringRef(kSni), isSNI(), allocator);
obj.AddMember(StringRef(kFingerprint), m_fingerprint.toJSON(), allocator);
obj.AddMember(StringRef(kDaemon), m_mode == MODE_DAEMON, allocator);
obj.AddMember(StringRef(kSOCKS5), m_proxy.toJSON(doc), allocator);

View File

@@ -70,6 +70,7 @@ public:
static const char *kSOCKS5;
static const char *kSubmitToOrigin;
static const char *kTls;
static const char* kSni;
static const char *kUrl;
static const char *kUser;
static const char* kSpendSecretKey;
@@ -95,6 +96,7 @@ public:
inline bool isNicehash() const { return m_flags.test(FLAG_NICEHASH); }
inline bool isTLS() const { return m_flags.test(FLAG_TLS) || m_url.isTLS(); }
inline bool isSNI() const { return m_flags.test(FLAG_SNI); }
inline bool isValid() const { return m_url.isValid(); }
inline const Algorithm &algorithm() const { return m_algorithm; }
inline const Coin &coin() const { return m_coin; }
@@ -138,6 +140,7 @@ private:
FLAG_ENABLED,
FLAG_NICEHASH,
FLAG_TLS,
FLAG_SNI,
FLAG_MAX
};

View File

@@ -60,7 +60,7 @@ xmrig::Client::Tls::~Tls()
}
bool xmrig::Client::Tls::handshake()
bool xmrig::Client::Tls::handshake(const char* servername)
{
m_ssl = SSL_new(m_ctx);
assert(m_ssl != nullptr);
@@ -69,6 +69,10 @@ bool xmrig::Client::Tls::handshake()
return false;
}
if (servername) {
SSL_set_tlsext_host_name(m_ssl, servername);
}
SSL_set_connect_state(m_ssl);
SSL_set_bio(m_ssl, m_read, m_write);
SSL_do_handshake(m_ssl);

View File

@@ -42,7 +42,7 @@ public:
Tls(Client *client);
~Tls();
bool handshake();
bool handshake(const char* servername);
bool send(const char *data, size_t size);
const char *fingerprint() const;
const char *version() const;

View File

@@ -197,6 +197,11 @@ bool xmrig::BlockTemplate::parse(bool hashes)
ar(m_vote);
}
if (m_coin == Coin::ZEPHYR) {
uint8_t pricing_record[120];
ar(pricing_record);
}
// Miner transaction begin
// Prefix begin
setOffset(MINER_TX_PREFIX_OFFSET, ar.index());
@@ -220,8 +225,12 @@ bool xmrig::BlockTemplate::parse(bool hashes)
ar(m_height);
ar(m_numOutputs);
// must be 1 output
if (m_numOutputs != 1) {
if (m_coin == Coin::ZEPHYR) {
if (m_numOutputs < 2) {
return false;
}
}
else if (m_numOutputs != 1) {
return false;
}
@@ -237,7 +246,37 @@ bool xmrig::BlockTemplate::parse(bool hashes)
ar(m_ephPublicKey, kKeySize);
if (m_outputType == 3) {
if (m_coin == Coin::ZEPHYR) {
if (m_outputType != 2) {
return false;
}
uint64_t asset_type_len;
ar(asset_type_len);
ar.skip(asset_type_len);
ar(m_viewTag);
for (uint64_t k = 1; k < m_numOutputs; ++k) {
uint64_t amount2;
ar(amount2);
uint8_t output_type2;
ar(output_type2);
if (output_type2 != 2) {
return false;
}
Span key2;
ar(key2, kKeySize);
ar(asset_type_len);
ar.skip(asset_type_len);
uint8_t view_tag2;
ar(view_tag2);
}
}
else if (m_outputType == 3) {
ar(m_viewTag);
}
@@ -248,6 +287,8 @@ bool xmrig::BlockTemplate::parse(bool hashes)
BlobReader<true> ar_extra(blob(TX_EXTRA_OFFSET), m_extraSize);
ar.skip(m_extraSize);
bool pubkey_offset_first = true;
while (ar_extra.index() < m_extraSize) {
uint64_t extra_tag = 0;
uint64_t size = 0;
@@ -256,7 +297,10 @@ bool xmrig::BlockTemplate::parse(bool hashes)
switch (extra_tag) {
case 0x01: // TX_EXTRA_TAG_PUBKEY
setOffset(TX_PUBKEY_OFFSET, offset(TX_EXTRA_OFFSET) + ar_extra.index());
if (pubkey_offset_first) {
pubkey_offset_first = false;
setOffset(TX_PUBKEY_OFFSET, offset(TX_EXTRA_OFFSET) + ar_extra.index());
}
ar_extra.skip(kKeySize);
break;
@@ -277,6 +321,13 @@ bool xmrig::BlockTemplate::parse(bool hashes)
}
}
if (m_coin == Coin::ZEPHYR) {
uint64_t pricing_record_height, amount_burnt, amount_minted;
ar(pricing_record_height);
ar(amount_burnt);
ar(amount_minted);
}
setOffset(MINER_TX_PREFIX_END_OFFSET, ar.index());
// Prefix end

View File

@@ -37,36 +37,14 @@ class CnAlgo
public:
constexpr CnAlgo() {};
# define ASSERT_CN static_assert(Algorithm::isCN(ALGO), "invalid CRYPTONIGHT algorithm")
constexpr inline Algorithm::Id base() const { ASSERT_CN; return Algorithm::base(ALGO); }
constexpr inline size_t memory() const { ASSERT_CN; return Algorithm::l3(ALGO); }
constexpr inline uint32_t iterations() const { ASSERT_CN; return CN_ITER; }
constexpr inline Algorithm::Id base() const { static_assert(Algorithm::isCN(ALGO), "invalid CRYPTONIGHT algorithm"); return Algorithm::base(ALGO); }
constexpr inline bool isHeavy() const { return Algorithm::family(ALGO) == Algorithm::CN_HEAVY; }
constexpr inline bool isR() const { return ALGO == Algorithm::CN_R; }
constexpr inline size_t memory() const { static_assert(Algorithm::isCN(ALGO), "invalid CRYPTONIGHT algorithm"); return Algorithm::l3(ALGO); }
constexpr inline uint32_t iterations() const { static_assert(Algorithm::isCN(ALGO), "invalid CRYPTONIGHT algorithm"); return CN_ITER; }
constexpr inline uint32_t mask() const { return static_cast<uint32_t>(((memory() - 1) / 16) * 16); }
constexpr inline uint32_t half_mem() const { return mask() < memory() / 2; }
constexpr inline bool isBase1() const { ASSERT_CN; return Algorithm::base(ALGO) == Algorithm::CN_1; }
constexpr inline bool isBase2() const { ASSERT_CN; return Algorithm::base(ALGO) == Algorithm::CN_2; }
constexpr inline bool is2() const { return ALGO == Algorithm::CN_2; }
constexpr inline bool isR() const { return ALGO == Algorithm::CN_R; }
constexpr inline bool isHalf() const { return ALGO == Algorithm::CN_HALF; }
constexpr inline bool isRTO() const { return ALGO == Algorithm::CN_RTO; }
constexpr inline bool isRWZ() const { return ALGO == Algorithm::CN_RWZ; }
constexpr inline bool isZLS() const { return ALGO == Algorithm::CN_ZLS; }
constexpr inline bool isDouble() const { return ALGO == Algorithm::CN_DOUBLE; }
constexpr inline bool isCCX() const { return ALGO == Algorithm::CN_CCX; }
constexpr inline bool isHeavy() const { ASSERT_CN; return Algorithm::family(ALGO) == Algorithm::CN_HEAVY; }
constexpr inline bool isHeavyTube() const { return ALGO == Algorithm::CN_HEAVY_TUBE; }
constexpr inline bool isHeavyXHV() const { return ALGO == Algorithm::CN_HEAVY_XHV; }
constexpr inline bool isPico0() const { return ALGO == Algorithm::CN_PICO_0; }
constexpr inline bool isPicoTLO() const { return ALGO == Algorithm::CN_PICO_TLO; }
constexpr inline bool isUPX2() const { return ALGO == Algorithm::CN_UPX2; }
constexpr inline bool isGR0() const { return ALGO == Algorithm::CN_GR_0; }
constexpr inline bool isGR1() const { return ALGO == Algorithm::CN_GR_1; }
constexpr inline bool isGR2() const { return ALGO == Algorithm::CN_GR_2; }
constexpr inline bool isGR3() const { return ALGO == Algorithm::CN_GR_3; }
constexpr inline bool isGR4() const { return ALGO == Algorithm::CN_GR_4; }
constexpr inline bool isGR5() const { return ALGO == Algorithm::CN_GR_5; }
inline static uint32_t iterations(Algorithm::Id algo)
{
switch (algo) {

View File

@@ -603,7 +603,7 @@ static inline void cryptonight_monero_tweak(uint64_t *mem_out, const uint8_t *l,
constexpr CnAlgo<ALGO> props;
if (props.base() == Algorithm::CN_2) {
VARIANT2_SHUFFLE(l, idx, ax0, bx0, bx1, cx, ((props.isRWZ() || props.isUPX2()) ? 1 : 0));
VARIANT2_SHUFFLE(l, idx, ax0, bx0, bx1, cx, (((ALGO == Algorithm::CN_RWZ) || (ALGO == Algorithm::CN_UPX2)) ? 1 : 0));
_mm_store_si128(reinterpret_cast<__m128i *>(mem_out), _mm_xor_si128(bx0, cx));
} else {
__m128i tmp = _mm_xor_si128(bx0, cx);
@@ -665,8 +665,15 @@ inline void cryptonight_single_hash(const uint8_t *__restrict__ input, size_t si
constexpr CnAlgo<ALGO> props;
constexpr size_t MASK = props.mask();
constexpr Algorithm::Id BASE = props.base();
if (props.isBase1() && size < 43) {
# ifdef XMRIG_ALGO_CN_HEAVY
constexpr bool IS_CN_HEAVY_TUBE = ALGO == Algorithm::CN_HEAVY_TUBE;
# else
constexpr bool IS_CN_HEAVY_TUBE = false;
# endif
if (BASE == Algorithm::CN_1 && size < 43) {
memset(output, 0, 32);
return;
}
@@ -687,7 +694,10 @@ inline void cryptonight_single_hash(const uint8_t *__restrict__ input, size_t si
V4_Instruction code[256];
const int code_size = v4_random_math_init<ALGO>(code, height);
v4_soft_aes_compile_code(code, code_size, reinterpret_cast<void*>(ctx[0]->generated_code), Assembly::NONE);
if (ALGO == Algorithm::CN_R) {
v4_soft_aes_compile_code(code, code_size, reinterpret_cast<void*>(ctx[0]->generated_code), Assembly::NONE);
}
ctx[0]->generated_code_data = { ALGO, height };
}
@@ -708,26 +718,26 @@ inline void cryptonight_single_hash(const uint8_t *__restrict__ input, size_t si
__m128i bx1 = _mm_set_epi64x(static_cast<int64_t>(h0[9] ^ h0[11]), static_cast<int64_t>(h0[8] ^ h0[10]));
__m128 conc_var;
if (props.isCCX()) {
if (ALGO == Algorithm::CN_CCX) {
conc_var = _mm_setzero_ps();
RESTORE_ROUNDING_MODE();
}
for (size_t i = 0; i < props.iterations(); i++) {
__m128i cx;
if (props.isHeavyTube() || !SOFT_AES) {
if (IS_CN_HEAVY_TUBE || !SOFT_AES) {
cx = _mm_load_si128(reinterpret_cast<const __m128i *>(&l0[interleaved_index<interleave>(idx0 & MASK)]));
if (props.isCCX()) {
if (ALGO == Algorithm::CN_CCX) {
cryptonight_conceal_tweak(cx, conc_var);
}
}
const __m128i ax0 = _mm_set_epi64x(static_cast<int64_t>(ah0), static_cast<int64_t>(al0));
if (props.isHeavyTube()) {
if (IS_CN_HEAVY_TUBE) {
cx = aes_round_tweak_div(cx, ax0);
}
else if (SOFT_AES) {
if (props.isCCX()) {
if (ALGO == Algorithm::CN_CCX) {
cx = _mm_load_si128(reinterpret_cast<const __m128i*>(&l0[interleaved_index<interleave>(idx0 & MASK)]));
cryptonight_conceal_tweak(cx, conc_var);
cx = soft_aesenc(&cx, ax0, reinterpret_cast<const uint32_t*>(saes_table));
@@ -740,7 +750,7 @@ inline void cryptonight_single_hash(const uint8_t *__restrict__ input, size_t si
cx = _mm_aesenc_si128(cx, ax0);
}
if (props.isBase1() || props.isBase2()) {
if (BASE == Algorithm::CN_1 || BASE == Algorithm::CN_2) {
cryptonight_monero_tweak<ALGO>(reinterpret_cast<uint64_t*>(&l0[interleaved_index<interleave>(idx0 & MASK)]), l0, idx0 & MASK, ax0, bx0, bx1, cx);
} else {
_mm_store_si128(reinterpret_cast<__m128i *>(&l0[interleaved_index<interleave>(idx0 & MASK)]), _mm_xor_si128(bx0, cx));
@@ -752,11 +762,13 @@ inline void cryptonight_single_hash(const uint8_t *__restrict__ input, size_t si
cl = (reinterpret_cast<uint64_t*>(&l0[interleaved_index<interleave>(idx0 & MASK)]))[0];
ch = (reinterpret_cast<uint64_t*>(&l0[interleaved_index<interleave>(idx0 & MASK)]))[1];
if (props.isBase2()) {
if (BASE == Algorithm::CN_2) {
if (props.isR()) {
VARIANT4_RANDOM_MATH(0, al0, ah0, cl, bx0, bx1);
al0 ^= r0[2] | (static_cast<uint64_t>(r0[3]) << 32);
ah0 ^= r0[0] | (static_cast<uint64_t>(r0[1]) << 32);
if (ALGO == Algorithm::CN_R) {
al0 ^= r0[2] | (static_cast<uint64_t>(r0[3]) << 32);
ah0 ^= r0[0] | (static_cast<uint64_t>(r0[1]) << 32);
}
} else {
VARIANT2_INTEGER_MATH(0, cl, cx);
}
@@ -764,11 +776,11 @@ inline void cryptonight_single_hash(const uint8_t *__restrict__ input, size_t si
lo = __umul128(idx0, cl, &hi);
if (props.isBase2()) {
if (props.isR()) {
if (BASE == Algorithm::CN_2) {
if (ALGO == Algorithm::CN_R) {
VARIANT2_SHUFFLE(l0, idx0 & MASK, ax0, bx0, bx1, cx, 0);
} else {
VARIANT2_SHUFFLE2(l0, idx0 & MASK, ax0, bx0, bx1, hi, lo, ((props.isRWZ() || props.isUPX2()) ? 1 : 0));
VARIANT2_SHUFFLE2(l0, idx0 & MASK, ax0, bx0, bx1, hi, lo, (((ALGO == Algorithm::CN_RWZ) || (ALGO == Algorithm::CN_UPX2)) ? 1 : 0));
}
}
@@ -777,9 +789,9 @@ inline void cryptonight_single_hash(const uint8_t *__restrict__ input, size_t si
reinterpret_cast<uint64_t*>(&l0[interleaved_index<interleave>(idx0 & MASK)])[0] = al0;
if (props.isHeavyTube() || props.isRTO()) {
if (IS_CN_HEAVY_TUBE || ALGO == Algorithm::CN_RTO) {
reinterpret_cast<uint64_t*>(&l0[interleaved_index<interleave>(idx0 & MASK)])[1] = ah0 ^ tweak1_2_0 ^ al0;
} else if (props.isBase1()) {
} else if (BASE == Algorithm::CN_1) {
reinterpret_cast<uint64_t*>(&l0[interleaved_index<interleave>(idx0 & MASK)])[1] = ah0 ^ tweak1_2_0;
} else {
reinterpret_cast<uint64_t*>(&l0[interleaved_index<interleave>(idx0 & MASK)])[1] = ah0;
@@ -807,7 +819,7 @@ inline void cryptonight_single_hash(const uint8_t *__restrict__ input, size_t si
((int64_t*)&l0[interleaved_index<interleave>(idx0 & MASK)])[0] = n ^ q;
if (props.isHeavyXHV()) {
if (ALGO == Algorithm::CN_HEAVY_XHV) {
d = ~d;
}
@@ -815,7 +827,7 @@ inline void cryptonight_single_hash(const uint8_t *__restrict__ input, size_t si
}
# endif
if (props.isBase2()) {
if (BASE == Algorithm::CN_2) {
bx1 = bx0;
}
@@ -948,7 +960,7 @@ inline void cryptonight_single_hash_asm(const uint8_t *__restrict__ input, size_
}
cn_explode_scratchpad<ALGO, false, 0>(ctx[0]);
if (props.is2()) {
if (ALGO == Algorithm::CN_2) {
if (ASM == Assembly::INTEL) {
cnv2_mainloop_ivybridge_asm(ctx);
}
@@ -959,7 +971,7 @@ inline void cryptonight_single_hash_asm(const uint8_t *__restrict__ input, size_
cnv2_mainloop_bulldozer_asm(ctx);
}
}
else if (props.isHalf()) {
else if (ALGO == Algorithm::CN_HALF) {
if (ASM == Assembly::INTEL) {
cn_half_mainloop_ivybridge_asm(ctx);
}
@@ -971,7 +983,7 @@ inline void cryptonight_single_hash_asm(const uint8_t *__restrict__ input, size_
}
}
# ifdef XMRIG_ALGO_CN_PICO
else if (props.isPico0()) {
else if (ALGO == Algorithm::CN_PICO_0) {
if (ASM == Assembly::INTEL) {
cn_trtl_mainloop_ivybridge_asm(ctx);
}
@@ -982,7 +994,7 @@ inline void cryptonight_single_hash_asm(const uint8_t *__restrict__ input, size_
cn_trtl_mainloop_bulldozer_asm(ctx);
}
}
else if (props.isPicoTLO()) {
else if (ALGO == Algorithm::CN_PICO_TLO) {
if (ASM == Assembly::INTEL) {
cn_tlo_mainloop_ivybridge_asm(ctx);
}
@@ -994,10 +1006,10 @@ inline void cryptonight_single_hash_asm(const uint8_t *__restrict__ input, size_
}
}
# endif
else if (props.isRWZ()) {
else if (ALGO == Algorithm::CN_RWZ) {
cnv2_rwz_mainloop_asm(ctx);
}
else if (props.isZLS()) {
else if (ALGO == Algorithm::CN_ZLS) {
if (ASM == Assembly::INTEL) {
cn_zls_mainloop_ivybridge_asm(ctx);
}
@@ -1008,7 +1020,7 @@ inline void cryptonight_single_hash_asm(const uint8_t *__restrict__ input, size_
cn_zls_mainloop_bulldozer_asm(ctx);
}
}
else if (props.isDouble()) {
else if (ALGO == Algorithm::CN_DOUBLE) {
if (ASM == Assembly::INTEL) {
cn_double_mainloop_ivybridge_asm(ctx);
}
@@ -1020,7 +1032,7 @@ inline void cryptonight_single_hash_asm(const uint8_t *__restrict__ input, size_
}
}
# ifdef XMRIG_ALGO_CN_FEMTO
else if (props.isUPX2()) {
else if (ALGO == Algorithm::CN_UPX2) {
cn_upx2_mainloop_asm(ctx);
}
# endif
@@ -1066,22 +1078,22 @@ inline void cryptonight_double_hash_asm(const uint8_t *__restrict__ input, size_
cn_explode_scratchpad<ALGO, false, 0>(ctx[1]);
}
if (props.is2()) {
if (ALGO == Algorithm::CN_2) {
cnv2_double_mainloop_sandybridge_asm(ctx);
}
else if (props.isHalf()){
else if (ALGO == Algorithm::CN_HALF) {
cn_half_double_mainloop_sandybridge_asm(ctx);
}
# ifdef XMRIG_ALGO_CN_PICO
else if (props.isPico0()) {
else if (ALGO == Algorithm::CN_PICO_0) {
cn_trtl_double_mainloop_sandybridge_asm(ctx);
}
else if (props.isPicoTLO()) {
else if (ALGO == Algorithm::CN_PICO_TLO) {
cn_tlo_double_mainloop_sandybridge_asm(ctx);
}
# endif
# ifdef XMRIG_ALGO_CN_FEMTO
else if (props.isUPX2()) {
else if (ALGO == Algorithm::CN_UPX2) {
if (Cpu::info()->arch() == ICpuInfo::ARCH_ZEN3) {
cnv2_upx_double_mainloop_zen3_asm(ctx);
}
@@ -1090,13 +1102,13 @@ inline void cryptonight_double_hash_asm(const uint8_t *__restrict__ input, size_
}
}
# endif
else if (props.isRWZ()) {
else if (ALGO == Algorithm::CN_RWZ) {
cnv2_rwz_double_mainloop_asm(ctx);
}
else if (props.isZLS()) {
else if (ALGO == Algorithm::CN_ZLS) {
cn_zls_double_mainloop_sandybridge_asm(ctx);
}
else if (props.isDouble()) {
else if (ALGO == Algorithm::CN_DOUBLE) {
cn_double_double_mainloop_sandybridge_asm(ctx);
}
else if (props.isR()) {
@@ -1134,8 +1146,9 @@ template<Algorithm::Id ALGO>
static NOINLINE void cryptonight_single_hash_gr_sse41(const uint8_t* __restrict__ input, size_t size, uint8_t* __restrict__ output, cryptonight_ctx** __restrict__ ctx, uint64_t height)
{
constexpr CnAlgo<ALGO> props;
constexpr Algorithm::Id BASE = props.base();
if (props.isBase1() && size < 43) {
if (BASE == Algorithm::CN_1 && size < 43) {
memset(output, 0, 32);
return;
}
@@ -1150,12 +1163,12 @@ static NOINLINE void cryptonight_single_hash_gr_sse41(const uint8_t* __restrict_
VARIANT1_INIT(0);
ctx[0]->tweak1_2 = tweak1_2_0;
ctx[0]->tweak1_table = tweak1_table;
if (props.isGR0()) cn_gr0_single_mainloop_asm(ctx);
if (props.isGR1()) cn_gr1_single_mainloop_asm(ctx);
if (props.isGR2()) cn_gr2_single_mainloop_asm(ctx);
if (props.isGR3()) cn_gr3_single_mainloop_asm(ctx);
if (props.isGR4()) cn_gr4_single_mainloop_asm(ctx);
if (props.isGR5()) cn_gr5_single_mainloop_asm(ctx);
if (ALGO == Algorithm::CN_GR_0) cn_gr0_single_mainloop_asm(ctx);
if (ALGO == Algorithm::CN_GR_1) cn_gr1_single_mainloop_asm(ctx);
if (ALGO == Algorithm::CN_GR_2) cn_gr2_single_mainloop_asm(ctx);
if (ALGO == Algorithm::CN_GR_3) cn_gr3_single_mainloop_asm(ctx);
if (ALGO == Algorithm::CN_GR_4) cn_gr4_single_mainloop_asm(ctx);
if (ALGO == Algorithm::CN_GR_5) cn_gr5_single_mainloop_asm(ctx);
cn_implode_scratchpad<ALGO, false, 0>(ctx[0]);
keccakf(reinterpret_cast<uint64_t*>(ctx[0]->state), 24);
@@ -1167,8 +1180,9 @@ template<Algorithm::Id ALGO>
static NOINLINE void cryptonight_double_hash_gr_sse41(const uint8_t *__restrict__ input, size_t size, uint8_t *__restrict__ output, cryptonight_ctx **__restrict__ ctx, uint64_t height)
{
constexpr CnAlgo<ALGO> props;
constexpr Algorithm::Id BASE = props.base();
if (props.isBase1() && size < 43) {
if (BASE == Algorithm::CN_1 && size < 43) {
memset(output, 0, 64);
return;
}
@@ -1182,7 +1196,7 @@ static NOINLINE void cryptonight_double_hash_gr_sse41(const uint8_t *__restrict_
}
# ifdef XMRIG_VAES
if (cn_vaes_enabled) {
if (!props.isHeavy() && cn_vaes_enabled) {
cn_explode_scratchpad_vaes_double(ctx[0], ctx[1], props.memory(), props.half_mem());
}
else
@@ -1200,15 +1214,15 @@ static NOINLINE void cryptonight_double_hash_gr_sse41(const uint8_t *__restrict_
ctx[0]->tweak1_table = tweak1_table;
if (props.isGR0()) cn_gr0_double_mainloop_asm(ctx);
if (props.isGR1()) cn_gr1_double_mainloop_asm(ctx);
if (props.isGR2()) cn_gr2_double_mainloop_asm(ctx);
if (props.isGR3()) cn_gr3_double_mainloop_asm(ctx);
if (props.isGR4()) cn_gr4_double_mainloop_asm(ctx);
if (props.isGR5()) cn_gr5_double_mainloop_asm(ctx);
if (ALGO == Algorithm::CN_GR_0) cn_gr0_double_mainloop_asm(ctx);
if (ALGO == Algorithm::CN_GR_1) cn_gr1_double_mainloop_asm(ctx);
if (ALGO == Algorithm::CN_GR_2) cn_gr2_double_mainloop_asm(ctx);
if (ALGO == Algorithm::CN_GR_3) cn_gr3_double_mainloop_asm(ctx);
if (ALGO == Algorithm::CN_GR_4) cn_gr4_double_mainloop_asm(ctx);
if (ALGO == Algorithm::CN_GR_5) cn_gr5_double_mainloop_asm(ctx);
# ifdef XMRIG_VAES
if (cn_vaes_enabled) {
if (!props.isHeavy() && cn_vaes_enabled) {
cn_implode_scratchpad_vaes_double(ctx[0], ctx[1], props.memory(), props.half_mem());
}
else
@@ -1253,8 +1267,15 @@ inline void cryptonight_double_hash(const uint8_t *__restrict__ input, size_t si
constexpr CnAlgo<ALGO> props;
constexpr size_t MASK = props.mask();
constexpr Algorithm::Id BASE = props.base();
if (props.isBase1() && size < 43) {
# ifdef XMRIG_ALGO_CN_HEAVY
constexpr bool IS_CN_HEAVY_TUBE = ALGO == Algorithm::CN_HEAVY_TUBE;
# else
constexpr bool IS_CN_HEAVY_TUBE = false;
# endif
if (BASE == Algorithm::CN_1 && size < 43) {
memset(output, 0, 64);
return;
}
@@ -1302,7 +1323,7 @@ inline void cryptonight_double_hash(const uint8_t *__restrict__ input, size_t si
__m128i bx11 = _mm_set_epi64x(h1[9] ^ h1[11], h1[8] ^ h1[10]);
__m128 conc_var0, conc_var1;
if (props.isCCX()) {
if (ALGO == Algorithm::CN_CCX) {
conc_var0 = _mm_setzero_ps();
conc_var1 = _mm_setzero_ps();
RESTORE_ROUNDING_MODE();
@@ -1313,10 +1334,10 @@ inline void cryptonight_double_hash(const uint8_t *__restrict__ input, size_t si
for (size_t i = 0; i < props.iterations(); i++) {
__m128i cx0, cx1;
if (props.isHeavyTube() || !SOFT_AES) {
if (IS_CN_HEAVY_TUBE || !SOFT_AES) {
cx0 = _mm_load_si128(reinterpret_cast<const __m128i *>(&l0[idx0 & MASK]));
cx1 = _mm_load_si128(reinterpret_cast<const __m128i *>(&l1[idx1 & MASK]));
if (props.isCCX()) {
if (ALGO == Algorithm::CN_CCX) {
cryptonight_conceal_tweak(cx0, conc_var0);
cryptonight_conceal_tweak(cx1, conc_var1);
}
@@ -1324,12 +1345,12 @@ inline void cryptonight_double_hash(const uint8_t *__restrict__ input, size_t si
const __m128i ax0 = _mm_set_epi64x(ah0, al0);
const __m128i ax1 = _mm_set_epi64x(ah1, al1);
if (props.isHeavyTube()) {
if (IS_CN_HEAVY_TUBE) {
cx0 = aes_round_tweak_div(cx0, ax0);
cx1 = aes_round_tweak_div(cx1, ax1);
}
else if (SOFT_AES) {
if (props.isCCX()) {
if (ALGO == Algorithm::CN_CCX) {
cx0 = _mm_load_si128(reinterpret_cast<const __m128i*>(&l0[idx0 & MASK]));
cx1 = _mm_load_si128(reinterpret_cast<const __m128i*>(&l1[idx1 & MASK]));
cryptonight_conceal_tweak(cx0, conc_var0);
@@ -1347,7 +1368,7 @@ inline void cryptonight_double_hash(const uint8_t *__restrict__ input, size_t si
cx1 = _mm_aesenc_si128(cx1, ax1);
}
if (props.isBase1() || props.isBase2()) {
if (BASE == Algorithm::CN_1 || BASE == Algorithm::CN_2) {
cryptonight_monero_tweak<ALGO>((uint64_t*)&l0[idx0 & MASK], l0, idx0 & MASK, ax0, bx00, bx01, cx0);
cryptonight_monero_tweak<ALGO>((uint64_t*)&l1[idx1 & MASK], l1, idx1 & MASK, ax1, bx10, bx11, cx1);
} else {
@@ -1362,11 +1383,13 @@ inline void cryptonight_double_hash(const uint8_t *__restrict__ input, size_t si
cl = ((uint64_t*) &l0[idx0 & MASK])[0];
ch = ((uint64_t*) &l0[idx0 & MASK])[1];
if (props.isBase2()) {
if (BASE == Algorithm::CN_2) {
if (props.isR()) {
VARIANT4_RANDOM_MATH(0, al0, ah0, cl, bx00, bx01);
al0 ^= r0[2] | ((uint64_t)(r0[3]) << 32);
ah0 ^= r0[0] | ((uint64_t)(r0[1]) << 32);
if (ALGO == Algorithm::CN_R) {
al0 ^= r0[2] | ((uint64_t)(r0[3]) << 32);
ah0 ^= r0[0] | ((uint64_t)(r0[1]) << 32);
}
} else {
VARIANT2_INTEGER_MATH(0, cl, cx0);
}
@@ -1374,11 +1397,11 @@ inline void cryptonight_double_hash(const uint8_t *__restrict__ input, size_t si
lo = __umul128(idx0, cl, &hi);
if (props.isBase2()) {
if (props.isR()) {
if (BASE == Algorithm::CN_2) {
if (ALGO == Algorithm::CN_R) {
VARIANT2_SHUFFLE(l0, idx0 & MASK, ax0, bx00, bx01, cx0, 0);
} else {
VARIANT2_SHUFFLE2(l0, idx0 & MASK, ax0, bx00, bx01, hi, lo, ((props.isRWZ() || props.isUPX2()) ? 1 : 0));
VARIANT2_SHUFFLE2(l0, idx0 & MASK, ax0, bx00, bx01, hi, lo, (((ALGO == Algorithm::CN_RWZ) || (ALGO == Algorithm::CN_UPX2)) ? 1 : 0));
}
}
@@ -1387,9 +1410,9 @@ inline void cryptonight_double_hash(const uint8_t *__restrict__ input, size_t si
((uint64_t*)&l0[idx0 & MASK])[0] = al0;
if (props.isHeavyTube() || props.isRTO()) {
if (IS_CN_HEAVY_TUBE || ALGO == Algorithm::CN_RTO) {
((uint64_t*) &l0[idx0 & MASK])[1] = ah0 ^ tweak1_2_0 ^ al0;
} else if (props.isBase1()) {
} else if (BASE == Algorithm::CN_1) {
((uint64_t*) &l0[idx0 & MASK])[1] = ah0 ^ tweak1_2_0;
} else {
((uint64_t*) &l0[idx0 & MASK])[1] = ah0;
@@ -1407,7 +1430,7 @@ inline void cryptonight_double_hash(const uint8_t *__restrict__ input, size_t si
((int64_t*)&l0[idx0 & MASK])[0] = n ^ q;
if (props.isHeavyXHV()) {
if (ALGO == Algorithm::CN_HEAVY_XHV) {
d = ~d;
}
@@ -1418,11 +1441,13 @@ inline void cryptonight_double_hash(const uint8_t *__restrict__ input, size_t si
cl = ((uint64_t*) &l1[idx1 & MASK])[0];
ch = ((uint64_t*) &l1[idx1 & MASK])[1];
if (props.isBase2()) {
if (BASE == Algorithm::CN_2) {
if (props.isR()) {
VARIANT4_RANDOM_MATH(1, al1, ah1, cl, bx10, bx11);
al1 ^= r1[2] | ((uint64_t)(r1[3]) << 32);
ah1 ^= r1[0] | ((uint64_t)(r1[1]) << 32);
if (ALGO == Algorithm::CN_R) {
al1 ^= r1[2] | ((uint64_t)(r1[3]) << 32);
ah1 ^= r1[0] | ((uint64_t)(r1[1]) << 32);
}
} else {
VARIANT2_INTEGER_MATH(1, cl, cx1);
}
@@ -1430,11 +1455,11 @@ inline void cryptonight_double_hash(const uint8_t *__restrict__ input, size_t si
lo = __umul128(idx1, cl, &hi);
if (props.isBase2()) {
if (props.isR()) {
if (BASE == Algorithm::CN_2) {
if (ALGO == Algorithm::CN_R) {
VARIANT2_SHUFFLE(l1, idx1 & MASK, ax1, bx10, bx11, cx1, 0);
} else {
VARIANT2_SHUFFLE2(l1, idx1 & MASK, ax1, bx10, bx11, hi, lo, ((props.isRWZ() || props.isUPX2()) ? 1 : 0));
VARIANT2_SHUFFLE2(l1, idx1 & MASK, ax1, bx10, bx11, hi, lo, (((ALGO == Algorithm::CN_RWZ) || (ALGO == Algorithm::CN_UPX2)) ? 1 : 0));
}
}
@@ -1443,9 +1468,9 @@ inline void cryptonight_double_hash(const uint8_t *__restrict__ input, size_t si
((uint64_t*)&l1[idx1 & MASK])[0] = al1;
if (props.isHeavyTube() || props.isRTO()) {
if (IS_CN_HEAVY_TUBE || ALGO == Algorithm::CN_RTO) {
((uint64_t*)&l1[idx1 & MASK])[1] = ah1 ^ tweak1_2_1 ^ al1;
} else if (props.isBase1()) {
} else if (BASE == Algorithm::CN_1) {
((uint64_t*)&l1[idx1 & MASK])[1] = ah1 ^ tweak1_2_1;
} else {
((uint64_t*)&l1[idx1 & MASK])[1] = ah1;
@@ -1463,7 +1488,7 @@ inline void cryptonight_double_hash(const uint8_t *__restrict__ input, size_t si
((int64_t*)&l1[idx1 & MASK])[0] = n ^ q;
if (props.isHeavyXHV()) {
if (ALGO == Algorithm::CN_HEAVY_XHV) {
d = ~d;
}
@@ -1471,7 +1496,7 @@ inline void cryptonight_double_hash(const uint8_t *__restrict__ input, size_t si
}
# endif
if (props.isBase2()) {
if (BASE == Algorithm::CN_2) {
bx01 = bx00;
bx11 = bx10;
}
@@ -1504,8 +1529,9 @@ template<Algorithm::Id ALGO>
static NOINLINE void cryptonight_quad_hash_gr_sse41(const uint8_t* __restrict__ input, size_t size, uint8_t* __restrict__ output, cryptonight_ctx** __restrict__ ctx, uint64_t height)
{
constexpr CnAlgo<ALGO> props;
constexpr Algorithm::Id BASE = props.base();
if (props.isBase1() && size < 43) {
if (BASE == Algorithm::CN_1 && size < 43) {
memset(output, 0, 32 * 4);
return;
}
@@ -1523,7 +1549,7 @@ static NOINLINE void cryptonight_quad_hash_gr_sse41(const uint8_t* __restrict__
}
# ifdef XMRIG_VAES
if (cn_vaes_enabled) {
if (!props.isHeavy() && cn_vaes_enabled) {
cn_explode_scratchpad_vaes_double(ctx[0], ctx[1], props.memory(), props.half_mem());
cn_explode_scratchpad_vaes_double(ctx[2], ctx[3], props.memory(), props.half_mem());
}
@@ -1543,15 +1569,15 @@ static NOINLINE void cryptonight_quad_hash_gr_sse41(const uint8_t* __restrict__
ctx[0]->tweak1_table = tweak1_table;
if (props.isGR0()) cn_gr0_quad_mainloop_asm(ctx);
if (props.isGR1()) cn_gr1_quad_mainloop_asm(ctx);
if (props.isGR2()) cn_gr2_quad_mainloop_asm(ctx);
if (props.isGR3()) cn_gr3_quad_mainloop_asm(ctx);
if (props.isGR4()) cn_gr4_quad_mainloop_asm(ctx);
if (props.isGR5()) cn_gr5_quad_mainloop_asm(ctx);
if (ALGO == Algorithm::CN_GR_0) cn_gr0_quad_mainloop_asm(ctx);
if (ALGO == Algorithm::CN_GR_1) cn_gr1_quad_mainloop_asm(ctx);
if (ALGO == Algorithm::CN_GR_2) cn_gr2_quad_mainloop_asm(ctx);
if (ALGO == Algorithm::CN_GR_3) cn_gr3_quad_mainloop_asm(ctx);
if (ALGO == Algorithm::CN_GR_4) cn_gr4_quad_mainloop_asm(ctx);
if (ALGO == Algorithm::CN_GR_5) cn_gr5_quad_mainloop_asm(ctx);
# ifdef XMRIG_VAES
if (cn_vaes_enabled) {
if (!props.isHeavy() && cn_vaes_enabled) {
cn_implode_scratchpad_vaes_double(ctx[0], ctx[1], props.memory(), props.half_mem());
cn_implode_scratchpad_vaes_double(ctx[2], ctx[3], props.memory(), props.half_mem());
}
@@ -1580,14 +1606,14 @@ static NOINLINE void cryptonight_quad_hash_gr_sse41(const uint8_t* __restrict__
#define CN_STEP1(a, b0, b1, c, l, ptr, idx, conc_var) \
ptr = reinterpret_cast<__m128i*>(&l[idx & MASK]); \
c = _mm_load_si128(ptr); \
if (props.isCCX()) { \
if (ALGO == Algorithm::CN_CCX) { \
cryptonight_conceal_tweak(c, conc_var); \
}
#define CN_STEP2(a, b0, b1, c, l, ptr, idx) \
if (props.isHeavyTube()) { \
if (IS_CN_HEAVY_TUBE) { \
c = aes_round_tweak_div(c, a); \
} \
else if (SOFT_AES) { \
@@ -1596,7 +1622,7 @@ static NOINLINE void cryptonight_quad_hash_gr_sse41(const uint8_t* __restrict__
c = _mm_aesenc_si128(c, a); \
} \
\
if (props.isBase1() || props.isBase2()) { \
if (BASE == Algorithm::CN_1 || BASE == Algorithm::CN_2) { \
cryptonight_monero_tweak<ALGO>((uint64_t*)ptr, l, idx & MASK, a, b0, b1, c); \
} else { \
_mm_store_si128(ptr, _mm_xor_si128(b0, c)); \
@@ -1612,34 +1638,36 @@ static NOINLINE void cryptonight_quad_hash_gr_sse41(const uint8_t* __restrict__
#define CN_STEP4(part, a, b0, b1, c, l, mc, ptr, idx) \
uint64_t al##part, ah##part; \
if (props.isBase2()) { \
if (BASE == Algorithm::CN_2) { \
if (props.isR()) { \
al##part = _mm_cvtsi128_si64(a); \
ah##part = _mm_cvtsi128_si64(_mm_srli_si128(a, 8)); \
VARIANT4_RANDOM_MATH(part, al##part, ah##part, cl##part, b0, b1); \
al##part ^= r##part[2] | ((uint64_t)(r##part[3]) << 32); \
ah##part ^= r##part[0] | ((uint64_t)(r##part[1]) << 32); \
if (ALGO == Algorithm::CN_R) { \
al##part ^= r##part[2] | ((uint64_t)(r##part[3]) << 32); \
ah##part ^= r##part[0] | ((uint64_t)(r##part[1]) << 32); \
} \
} else { \
VARIANT2_INTEGER_MATH(part, cl##part, c); \
} \
} \
lo = __umul128(idx, cl##part, &hi); \
if (props.isBase2()) { \
if (props.isR()) { \
if (BASE == Algorithm::CN_2) { \
if (ALGO == Algorithm::CN_R) { \
VARIANT2_SHUFFLE(l, idx & MASK, a, b0, b1, c, 0); \
} else { \
VARIANT2_SHUFFLE2(l, idx & MASK, a, b0, b1, hi, lo, ((props.isRWZ() || props.isUPX2()) ? 1 : 0)); \
VARIANT2_SHUFFLE2(l, idx & MASK, a, b0, b1, hi, lo, (((ALGO == Algorithm::CN_RWZ) || (ALGO == Algorithm::CN_UPX2)) ? 1 : 0)); \
} \
} \
if (props.isR()) { \
if (ALGO == Algorithm::CN_R) { \
a = _mm_set_epi64x(ah##part, al##part); \
} \
a = _mm_add_epi64(a, _mm_set_epi64x(lo, hi)); \
\
if (props.isBase1()) { \
if (BASE == Algorithm::CN_1) { \
_mm_store_si128(ptr, _mm_xor_si128(a, mc)); \
\
if (props.isHeavyTube() || props.isRTO()) { \
if (IS_CN_HEAVY_TUBE || ALGO == Algorithm::CN_RTO) { \
((uint64_t*)ptr)[1] ^= ((uint64_t*)ptr)[0]; \
} \
} else { \
@@ -1653,13 +1681,13 @@ static NOINLINE void cryptonight_quad_hash_gr_sse41(const uint8_t* __restrict__
int32_t d = ((int32_t*)&l[idx & MASK])[2]; \
int64_t q = n / (d | 0x5); \
((int64_t*)&l[idx & MASK])[0] = n ^ q; \
if (props.isHeavyXHV()) { \
if (IS_CN_HEAVY_XHV) { \
d = ~d; \
} \
\
idx = d ^ q; \
} \
if (props.isBase2()) { \
if (BASE == Algorithm::CN_2) { \
b1 = b0; \
} \
b0 = c;
@@ -1669,11 +1697,11 @@ static NOINLINE void cryptonight_quad_hash_gr_sse41(const uint8_t* __restrict__
__m128i mc##n; \
__m128i division_result_xmm_##n; \
__m128i sqrt_result_xmm_##n; \
if (props.isBase1()) { \
if (BASE == Algorithm::CN_1) { \
mc##n = _mm_set_epi64x(*reinterpret_cast<const uint64_t*>(input + n * size + 35) ^ \
*(reinterpret_cast<const uint64_t*>((ctx)->state) + 24), 0); \
} \
if (props.isBase2()) { \
if (BASE == Algorithm::CN_2) { \
division_result_xmm_##n = _mm_cvtsi64_si128(h##n[12]); \
sqrt_result_xmm_##n = _mm_cvtsi64_si128(h##n[13]); \
} \
@@ -1682,7 +1710,7 @@ static NOINLINE void cryptonight_quad_hash_gr_sse41(const uint8_t* __restrict__
__m128i bx##n##1 = _mm_set_epi64x(h##n[9] ^ h##n[11], h##n[8] ^ h##n[10]); \
__m128i cx##n = _mm_setzero_si128(); \
__m128 conc_var##n; \
if (props.isCCX()) { \
if (ALGO == Algorithm::CN_CCX) { \
conc_var##n = _mm_setzero_ps(); \
} \
VARIANT4_RANDOM_MATH_INIT(n);
@@ -1693,8 +1721,17 @@ inline void cryptonight_triple_hash(const uint8_t *__restrict__ input, size_t si
{
constexpr CnAlgo<ALGO> props;
constexpr size_t MASK = props.mask();
constexpr Algorithm::Id BASE = props.base();
if (props.isBase1() && size < 43) {
# ifdef XMRIG_ALGO_CN_HEAVY
constexpr bool IS_CN_HEAVY_TUBE = ALGO == Algorithm::CN_HEAVY_TUBE;
constexpr bool IS_CN_HEAVY_XHV = ALGO == Algorithm::CN_HEAVY_XHV;
# else
constexpr bool IS_CN_HEAVY_TUBE = false;
constexpr bool IS_CN_HEAVY_XHV = false;
# endif
if (BASE == Algorithm::CN_1 && size < 43) {
memset(output, 0, 32 * 3);
return;
}
@@ -1718,7 +1755,7 @@ inline void cryptonight_triple_hash(const uint8_t *__restrict__ input, size_t si
CONST_INIT(ctx[1], 1);
CONST_INIT(ctx[2], 2);
VARIANT2_SET_ROUNDING_MODE();
if (props.isCCX()) {
if (ALGO == Algorithm::CN_CCX) {
RESTORE_ROUNDING_MODE();
}
@@ -1782,8 +1819,17 @@ inline void cryptonight_quad_hash(const uint8_t *__restrict__ input, size_t size
constexpr CnAlgo<ALGO> props;
constexpr size_t MASK = props.mask();
constexpr Algorithm::Id BASE = props.base();
if (props.isBase1() && size < 43) {
# ifdef XMRIG_ALGO_CN_HEAVY
constexpr bool IS_CN_HEAVY_TUBE = ALGO == Algorithm::CN_HEAVY_TUBE;
constexpr bool IS_CN_HEAVY_XHV = ALGO == Algorithm::CN_HEAVY_XHV;
# else
constexpr bool IS_CN_HEAVY_TUBE = false;
constexpr bool IS_CN_HEAVY_XHV = false;
# endif
if (BASE == Algorithm::CN_1 && size < 43) {
memset(output, 0, 32 * 4);
return;
}
@@ -1823,7 +1869,7 @@ inline void cryptonight_quad_hash(const uint8_t *__restrict__ input, size_t size
CONST_INIT(ctx[2], 2);
CONST_INIT(ctx[3], 3);
VARIANT2_SET_ROUNDING_MODE();
if (props.isCCX()) {
if (ALGO == Algorithm::CN_CCX) {
RESTORE_ROUNDING_MODE();
}
@@ -1884,8 +1930,17 @@ inline void cryptonight_penta_hash(const uint8_t *__restrict__ input, size_t siz
{
constexpr CnAlgo<ALGO> props;
constexpr size_t MASK = props.mask();
constexpr Algorithm::Id BASE = props.base();
if (props.isBase1() && size < 43) {
# ifdef XMRIG_ALGO_CN_HEAVY
constexpr bool IS_CN_HEAVY_TUBE = ALGO == Algorithm::CN_HEAVY_TUBE;
constexpr bool IS_CN_HEAVY_XHV = ALGO == Algorithm::CN_HEAVY_XHV;
# else
constexpr bool IS_CN_HEAVY_TUBE = false;
constexpr bool IS_CN_HEAVY_XHV = false;
# endif
if (BASE == Algorithm::CN_1 && size < 43) {
memset(output, 0, 32 * 5);
return;
}
@@ -1915,7 +1970,7 @@ inline void cryptonight_penta_hash(const uint8_t *__restrict__ input, size_t siz
CONST_INIT(ctx[3], 3);
CONST_INIT(ctx[4], 4);
VARIANT2_SET_ROUNDING_MODE();
if (props.isCCX()) {
if (ALGO == Algorithm::CN_CCX) {
RESTORE_ROUNDING_MODE();
}

View File

@@ -8,6 +8,7 @@ PUBLIC cnv2_mainloop_bulldozer_asm
PUBLIC cnv2_double_mainloop_sandybridge_asm
PUBLIC cnv2_rwz_mainloop_asm
PUBLIC cnv2_rwz_double_mainloop_asm
PUBLIC cnv2_upx_double_mainloop_zen3_asm
ALIGN(64)
cnv1_single_mainloop_asm PROC

View File

@@ -8,6 +8,7 @@ PUBLIC cnv2_mainloop_bulldozer_asm
PUBLIC cnv2_double_mainloop_sandybridge_asm
PUBLIC cnv2_rwz_mainloop_asm
PUBLIC cnv2_rwz_double_mainloop_asm
PUBLIC cnv2_upx_double_mainloop_zen3_asm
ALIGN(64)
cnv1_single_mainloop_asm PROC

File diff suppressed because it is too large Load Diff

View File

@@ -1,7 +1,7 @@
/* XMRig
* Copyright (c) 2018-2020 tevador <tevador@gmail.com>
* Copyright (c) 2018-2021 SChernykh <https://github.com/SChernykh>
* Copyright (c) 2016-2021 XMRig <https://github.com/xmrig>, <support@xmrig.com>
* Copyright (c) 2018-2023 SChernykh <https://github.com/SChernykh>
* Copyright (c) 2016-2023 XMRig <https://github.com/xmrig>, <support@xmrig.com>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,7 +17,6 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "crypto/common/VirtualMemory.h"
#include "backend/cpu/Cpu.h"
#include "crypto/common/portable/mm_malloc.h"
@@ -25,6 +24,7 @@
#include <cmath>
#include <cstdlib>
#include <fstream>
#include <sys/mman.h>
@@ -84,7 +84,9 @@ static inline int hugePagesFlag(size_t size)
bool xmrig::VirtualMemory::isHugepagesAvailable()
{
# if defined(XMRIG_OS_MACOS) && defined(XMRIG_ARM)
# ifdef XMRIG_OS_LINUX
return std::ifstream("/proc/sys/vm/nr_hugepages").good() || std::ifstream("/sys/devices/system/node/node0/hugepages/hugepages-2048kB/nr_hugepages").good();
# elif defined(XMRIG_OS_MACOS) && defined(XMRIG_ARM)
return false;
# else
return true;

View File

@@ -131,8 +131,8 @@ void JitCompilerA64::generateProgram(Program& program, ProgramConfiguration& con
// and w16, w10, ScratchpadL3Mask64
emit32(0x121A0000 | 16 | (10 << 5) | ((RandomX_CurrentConfig.Log2_ScratchpadL3 - 7) << 10), code, codePos);
// and w17, w18, ScratchpadL3Mask64
emit32(0x121A0000 | 17 | (18 << 5) | ((RandomX_CurrentConfig.Log2_ScratchpadL3 - 7) << 10), code, codePos);
// and w17, w20, ScratchpadL3Mask64
emit32(0x121A0000 | 17 | (20 << 5) | ((RandomX_CurrentConfig.Log2_ScratchpadL3 - 7) << 10), code, codePos);
codePos = PrologueSize;
literalPos = ImulRcpLiteralsEnd;
@@ -148,16 +148,16 @@ void JitCompilerA64::generateProgram(Program& program, ProgramConfiguration& con
}
// Update spMix2
// eor w18, config.readReg2, config.readReg3
emit32(ARMV8A::EOR32 | 18 | (IntRegMap[config.readReg2] << 5) | (IntRegMap[config.readReg3] << 16), code, codePos);
// eor w20, config.readReg2, config.readReg3
emit32(ARMV8A::EOR32 | 20 | (IntRegMap[config.readReg2] << 5) | (IntRegMap[config.readReg3] << 16), code, codePos);
// Jump back to the main loop
const uint32_t offset = (((uint8_t*)randomx_program_aarch64_vm_instructions_end) - ((uint8_t*)randomx_program_aarch64)) - codePos;
emit32(ARMV8A::B | (offset / 4), code, codePos);
// and w18, w18, CacheLineAlignMask
// and w20, w20, CacheLineAlignMask
codePos = (((uint8_t*)randomx_program_aarch64_cacheline_align_mask1) - ((uint8_t*)randomx_program_aarch64));
emit32(0x121A0000 | 18 | (18 << 5) | ((RandomX_CurrentConfig.Log2_DatasetBaseSize - 7) << 10), code, codePos);
emit32(0x121A0000 | 20 | (20 << 5) | ((RandomX_CurrentConfig.Log2_DatasetBaseSize - 7) << 10), code, codePos);
// and w10, w10, CacheLineAlignMask
codePos = (((uint8_t*)randomx_program_aarch64_cacheline_align_mask2) - ((uint8_t*)randomx_program_aarch64));
@@ -189,8 +189,8 @@ void JitCompilerA64::generateProgramLight(Program& program, ProgramConfiguration
// and w16, w10, ScratchpadL3Mask64
emit32(0x121A0000 | 16 | (10 << 5) | ((RandomX_CurrentConfig.Log2_ScratchpadL3 - 7) << 10), code, codePos);
// and w17, w18, ScratchpadL3Mask64
emit32(0x121A0000 | 17 | (18 << 5) | ((RandomX_CurrentConfig.Log2_ScratchpadL3 - 7) << 10), code, codePos);
// and w17, w20, ScratchpadL3Mask64
emit32(0x121A0000 | 17 | (20 << 5) | ((RandomX_CurrentConfig.Log2_ScratchpadL3 - 7) << 10), code, codePos);
codePos = PrologueSize;
literalPos = ImulRcpLiteralsEnd;
@@ -206,8 +206,8 @@ void JitCompilerA64::generateProgramLight(Program& program, ProgramConfiguration
}
// Update spMix2
// eor w18, config.readReg2, config.readReg3
emit32(ARMV8A::EOR32 | 18 | (IntRegMap[config.readReg2] << 5) | (IntRegMap[config.readReg3] << 16), code, codePos);
// eor w20, config.readReg2, config.readReg3
emit32(ARMV8A::EOR32 | 20 | (IntRegMap[config.readReg2] << 5) | (IntRegMap[config.readReg3] << 16), code, codePos);
// Jump back to the main loop
const uint32_t offset = (((uint8_t*)randomx_program_aarch64_vm_instructions_end_light) - ((uint8_t*)randomx_program_aarch64)) - codePos;
@@ -477,7 +477,7 @@ void JitCompilerA64::emitAddImmediate(uint32_t dst, uint32_t src, uint32_t imm,
}
else
{
constexpr uint32_t tmp_reg = 18;
constexpr uint32_t tmp_reg = 20;
emitMovImmediate(tmp_reg, imm, code, k);
// add dst, src, tmp_reg
@@ -526,7 +526,7 @@ void JitCompilerA64::emitMemLoadFP(uint32_t src, Instruction& instr, uint8_t* co
uint32_t k = codePos;
uint32_t imm = instr.getImm32();
constexpr uint32_t tmp_reg = 18;
constexpr uint32_t tmp_reg = 19;
imm &= instr.getModMem() ? (RandomX_CurrentConfig.ScratchpadL1_Size - 1) : (RandomX_CurrentConfig.ScratchpadL2_Size - 1);
emitAddImmediate(tmp_reg, src, imm, code, k);
@@ -580,7 +580,7 @@ void JitCompilerA64::h_IADD_M(Instruction& instr, uint32_t& codePos)
const uint32_t src = IntRegMap[instr.src];
const uint32_t dst = IntRegMap[instr.dst];
constexpr uint32_t tmp_reg = 18;
constexpr uint32_t tmp_reg = 20;
emitMemLoad<tmp_reg>(dst, src, instr, code, k);
// add dst, dst, tmp_reg
@@ -618,7 +618,7 @@ void JitCompilerA64::h_ISUB_M(Instruction& instr, uint32_t& codePos)
const uint32_t src = IntRegMap[instr.src];
const uint32_t dst = IntRegMap[instr.dst];
constexpr uint32_t tmp_reg = 18;
constexpr uint32_t tmp_reg = 20;
emitMemLoad<tmp_reg>(dst, src, instr, code, k);
// sub dst, dst, tmp_reg
@@ -637,7 +637,7 @@ void JitCompilerA64::h_IMUL_R(Instruction& instr, uint32_t& codePos)
if (src == dst)
{
src = 18;
src = 20;
emitMovImmediate(src, instr.getImm32(), code, k);
}
@@ -655,7 +655,7 @@ void JitCompilerA64::h_IMUL_M(Instruction& instr, uint32_t& codePos)
const uint32_t src = IntRegMap[instr.src];
const uint32_t dst = IntRegMap[instr.dst];
constexpr uint32_t tmp_reg = 18;
constexpr uint32_t tmp_reg = 20;
emitMemLoad<tmp_reg>(dst, src, instr, code, k);
// sub dst, dst, tmp_reg
@@ -686,7 +686,7 @@ void JitCompilerA64::h_IMULH_M(Instruction& instr, uint32_t& codePos)
const uint32_t src = IntRegMap[instr.src];
const uint32_t dst = IntRegMap[instr.dst];
constexpr uint32_t tmp_reg = 18;
constexpr uint32_t tmp_reg = 20;
emitMemLoad<tmp_reg>(dst, src, instr, code, k);
// umulh dst, dst, tmp_reg
@@ -717,7 +717,7 @@ void JitCompilerA64::h_ISMULH_M(Instruction& instr, uint32_t& codePos)
const uint32_t src = IntRegMap[instr.src];
const uint32_t dst = IntRegMap[instr.dst];
constexpr uint32_t tmp_reg = 18;
constexpr uint32_t tmp_reg = 20;
emitMemLoad<tmp_reg>(dst, src, instr, code, k);
// smulh dst, dst, tmp_reg
@@ -735,7 +735,7 @@ void JitCompilerA64::h_IMUL_RCP(Instruction& instr, uint32_t& codePos)
uint32_t k = codePos;
constexpr uint32_t tmp_reg = 18;
constexpr uint32_t tmp_reg = 20;
const uint32_t dst = IntRegMap[instr.dst];
constexpr uint64_t N = 1ULL << 63;
@@ -754,9 +754,9 @@ void JitCompilerA64::h_IMUL_RCP(Instruction& instr, uint32_t& codePos)
literalPos -= sizeof(uint64_t);
*(uint64_t*)(code + literalPos) = (q << shift) + ((r << shift) / divisor);
if (literal_id < 13)
if (literal_id < 12)
{
static constexpr uint32_t literal_regs[13] = { 30 << 16, 29 << 16, 28 << 16, 27 << 16, 26 << 16, 25 << 16, 24 << 16, 23 << 16, 22 << 16, 21 << 16, 20 << 16, 11 << 16, 0 };
static constexpr uint32_t literal_regs[12] = { 30 << 16, 29 << 16, 28 << 16, 27 << 16, 26 << 16, 25 << 16, 24 << 16, 23 << 16, 22 << 16, 21 << 16, 11 << 16, 0 };
// mul dst, dst, literal_reg
emit32(ARMV8A::MUL | dst | (dst << 5) | literal_regs[literal_id], code, k);
@@ -794,7 +794,7 @@ void JitCompilerA64::h_IXOR_R(Instruction& instr, uint32_t& codePos)
if (src == dst)
{
src = 18;
src = 20;
emitMovImmediate(src, instr.getImm32(), code, k);
}
@@ -812,7 +812,7 @@ void JitCompilerA64::h_IXOR_M(Instruction& instr, uint32_t& codePos)
const uint32_t src = IntRegMap[instr.src];
const uint32_t dst = IntRegMap[instr.dst];
constexpr uint32_t tmp_reg = 18;
constexpr uint32_t tmp_reg = 20;
emitMemLoad<tmp_reg>(dst, src, instr, code, k);
// eor dst, dst, tmp_reg
@@ -850,7 +850,7 @@ void JitCompilerA64::h_IROL_R(Instruction& instr, uint32_t& codePos)
if (src != dst)
{
constexpr uint32_t tmp_reg = 18;
constexpr uint32_t tmp_reg = 20;
// sub tmp_reg, xzr, src
emit32(ARMV8A::SUB | tmp_reg | (31 << 5) | (src << 16), code, k);
@@ -878,7 +878,7 @@ void JitCompilerA64::h_ISWAP_R(Instruction& instr, uint32_t& codePos)
uint32_t k = codePos;
constexpr uint32_t tmp_reg = 18;
constexpr uint32_t tmp_reg = 20;
emit32(ARMV8A::MOV_REG | tmp_reg | (dst << 16), code, k);
emit32(ARMV8A::MOV_REG | dst | (src << 16), code, k);
emit32(ARMV8A::MOV_REG | src | (tmp_reg << 16), code, k);
@@ -1026,7 +1026,7 @@ void JitCompilerA64::h_CFROUND(Instruction& instr, uint32_t& codePos)
const uint32_t src = IntRegMap[instr.src];
constexpr uint32_t tmp_reg = 18;
constexpr uint32_t tmp_reg = 20;
constexpr uint32_t fpcr_tmp_reg = 8;
// ror tmp_reg, src, imm
@@ -1050,7 +1050,7 @@ void JitCompilerA64::h_ISTORE(Instruction& instr, uint32_t& codePos)
const uint32_t src = IntRegMap[instr.src];
const uint32_t dst = IntRegMap[instr.dst];
constexpr uint32_t tmp_reg = 18;
constexpr uint32_t tmp_reg = 20;
uint32_t imm = instr.getImm32();

View File

@@ -72,9 +72,9 @@
# x15 -> "r7"
# x16 -> spAddr0
# x17 -> spAddr1
# x18 -> temporary
# x18 -> unused (platform register, don't touch it)
# x19 -> temporary
# x20 -> literal for IMUL_RCP
# x20 -> temporary
# x21 -> literal for IMUL_RCP
# x22 -> literal for IMUL_RCP
# x23 -> literal for IMUL_RCP
@@ -109,7 +109,7 @@ DECL(randomx_program_aarch64):
# Save callee-saved registers
sub sp, sp, 192
stp x16, x17, [sp]
stp x18, x19, [sp, 16]
str x19, [sp, 16]
stp x20, x21, [sp, 32]
stp x22, x23, [sp, 48]
stp x24, x25, [sp, 64]
@@ -164,7 +164,6 @@ DECL(randomx_program_aarch64):
# Read literals
ldr x0, literal_x0
ldr x11, literal_x11
ldr x20, literal_x20
ldr x21, literal_x21
ldr x22, literal_x22
ldr x23, literal_x23
@@ -196,11 +195,11 @@ DECL(randomx_program_aarch64):
DECL(randomx_program_aarch64_main_loop):
# spAddr0 = spMix1 & ScratchpadL3Mask64;
# spAddr1 = (spMix1 >> 32) & ScratchpadL3Mask64;
lsr x18, x10, 32
lsr x20, x10, 32
# Actual mask will be inserted by JIT compiler
and w16, w10, 1
and w17, w18, 1
and w17, w20, 1
# x16 = scratchpad + spAddr0
# x17 = scratchpad + spAddr1
@@ -208,31 +207,31 @@ DECL(randomx_program_aarch64_main_loop):
add x17, x17, x2
# xor integer registers with scratchpad data (spAddr0)
ldp x18, x19, [x16]
eor x4, x4, x18
ldp x20, x19, [x16]
eor x4, x4, x20
eor x5, x5, x19
ldp x18, x19, [x16, 16]
eor x6, x6, x18
ldp x20, x19, [x16, 16]
eor x6, x6, x20
eor x7, x7, x19
ldp x18, x19, [x16, 32]
eor x12, x12, x18
ldp x20, x19, [x16, 32]
eor x12, x12, x20
eor x13, x13, x19
ldp x18, x19, [x16, 48]
eor x14, x14, x18
ldp x20, x19, [x16, 48]
eor x14, x14, x20
eor x15, x15, x19
# Load group F registers (spAddr1)
ldpsw x18, x19, [x17]
ins v16.d[0], x18
ldpsw x20, x19, [x17]
ins v16.d[0], x20
ins v16.d[1], x19
ldpsw x18, x19, [x17, 8]
ins v17.d[0], x18
ldpsw x20, x19, [x17, 8]
ins v17.d[0], x20
ins v17.d[1], x19
ldpsw x18, x19, [x17, 16]
ins v18.d[0], x18
ldpsw x20, x19, [x17, 16]
ins v18.d[0], x20
ins v18.d[1], x19
ldpsw x18, x19, [x17, 24]
ins v19.d[0], x18
ldpsw x20, x19, [x17, 24]
ins v19.d[0], x20
ins v19.d[1], x19
scvtf v16.2d, v16.2d
scvtf v17.2d, v17.2d
@@ -240,17 +239,17 @@ DECL(randomx_program_aarch64_main_loop):
scvtf v19.2d, v19.2d
# Load group E registers (spAddr1)
ldpsw x18, x19, [x17, 32]
ins v20.d[0], x18
ldpsw x20, x19, [x17, 32]
ins v20.d[0], x20
ins v20.d[1], x19
ldpsw x18, x19, [x17, 40]
ins v21.d[0], x18
ldpsw x20, x19, [x17, 40]
ins v21.d[0], x20
ins v21.d[1], x19
ldpsw x18, x19, [x17, 48]
ins v22.d[0], x18
ldpsw x20, x19, [x17, 48]
ins v22.d[0], x20
ins v22.d[1], x19
ldpsw x18, x19, [x17, 56]
ins v23.d[0], x18
ldpsw x20, x19, [x17, 56]
ins v23.d[0], x20
ins v23.d[1], x19
scvtf v20.2d, v20.2d
scvtf v21.2d, v21.2d
@@ -273,7 +272,6 @@ DECL(randomx_program_aarch64_vm_instructions):
literal_x0: .fill 1,8,0
literal_x11: .fill 1,8,0
literal_x20: .fill 1,8,0
literal_x21: .fill 1,8,0
literal_x22: .fill 1,8,0
literal_x23: .fill 1,8,0
@@ -309,17 +307,17 @@ DECL(randomx_program_aarch64_vm_instructions_end):
lsr x10, x9, 32
# mx ^= r[readReg2] ^ r[readReg3];
eor x9, x9, x18
eor x9, x9, x20
# Calculate dataset pointer for dataset prefetch
mov w18, w9
mov w20, w9
DECL(randomx_program_aarch64_cacheline_align_mask1):
# Actual mask will be inserted by JIT compiler
and x18, x18, 1
add x18, x18, x1
and x20, x20, 1
add x20, x20, x1
# Prefetch dataset data
prfm pldl2strm, [x18]
prfm pldl2strm, [x20]
# mx <-> ma
ror x9, x9, 32
@@ -331,17 +329,17 @@ DECL(randomx_program_aarch64_cacheline_align_mask2):
DECL(randomx_program_aarch64_xor_with_dataset_line):
# xor integer registers with dataset data
ldp x18, x19, [x10]
eor x4, x4, x18
ldp x20, x19, [x10]
eor x4, x4, x20
eor x5, x5, x19
ldp x18, x19, [x10, 16]
eor x6, x6, x18
ldp x20, x19, [x10, 16]
eor x6, x6, x20
eor x7, x7, x19
ldp x18, x19, [x10, 32]
eor x12, x12, x18
ldp x20, x19, [x10, 32]
eor x12, x12, x20
eor x13, x13, x19
ldp x18, x19, [x10, 48]
eor x14, x14, x18
ldp x20, x19, [x10, 48]
eor x14, x14, x20
eor x15, x15, x19
DECL(randomx_program_aarch64_update_spMix1):
@@ -384,7 +382,7 @@ DECL(randomx_program_aarch64_update_spMix1):
# Restore callee-saved registers
ldp x16, x17, [sp]
ldp x18, x19, [sp, 16]
ldr x19, [sp, 16]
ldp x20, x21, [sp, 32]
ldp x22, x23, [sp, 48]
ldp x24, x25, [sp, 64]
@@ -405,7 +403,7 @@ DECL(randomx_program_aarch64_vm_instructions_end_light):
stp x2, x30, [sp, 80]
# mx ^= r[readReg2] ^ r[readReg3];
eor x9, x9, x18
eor x9, x9, x20
# mx <-> ma
ror x9, x9, 32
@@ -447,8 +445,8 @@ DECL(randomx_program_aarch64_light_dataset_offset):
# x3 -> end item
DECL(randomx_init_dataset_aarch64):
# Save x30 (return address)
str x30, [sp, -16]!
# Save x20 (used as temporary, but must be saved to not break ABI) and x30 (return address)
stp x20, x30, [sp, -16]!
# Load pointer to cache memory
ldr x0, [x0]
@@ -460,8 +458,8 @@ DECL(randomx_init_dataset_aarch64_main_loop):
cmp x2, x3
bne DECL(randomx_init_dataset_aarch64_main_loop)
# Restore x30 (return address)
ldr x30, [sp], 16
# Restore x20 and x30
ldp x20, x30, [sp], 16
ret

View File

@@ -308,6 +308,10 @@ void xmrig::Network::tick()
if (m_donate) {
m_donate->tick(now);
}
# ifdef XMRIG_FEATURE_API
m_controller->api()->tick();
# endif
}

View File

@@ -22,15 +22,15 @@
#define APP_ID "xmrig"
#define APP_NAME "XMRig"
#define APP_DESC "XMRig miner"
#define APP_VERSION "6.19.4-dev"
#define APP_VERSION "6.21.0"
#define APP_DOMAIN "xmrig.com"
#define APP_SITE "www.xmrig.com"
#define APP_COPYRIGHT "Copyright (C) 2016-2023 xmrig.com"
#define APP_KIND "miner"
#define APP_VER_MAJOR 6
#define APP_VER_MINOR 19
#define APP_VER_PATCH 4
#define APP_VER_MINOR 21
#define APP_VER_PATCH 0
#ifdef _MSC_VER
# if (_MSC_VER >= 1930)
@@ -52,4 +52,39 @@
# endif
#endif
#ifdef XMRIG_OS_WIN
# define APP_OS "Windows"
#elif defined XMRIG_OS_IOS
# define APP_OS "iOS"
#elif defined XMRIG_OS_MACOS
# define APP_OS "macOS"
#elif defined XMRIG_OS_ANDROID
# define APP_OS "Android"
#elif defined XMRIG_OS_LINUX
# define APP_OS "Linux"
#elif defined XMRIG_OS_FREEBSD
# define APP_OS "FreeBSD"
#else
# define APP_OS "Unknown OS"
#endif
#define STR(X) #X
#define STR2(X) STR(X)
#ifdef XMRIG_ARM
# define APP_ARCH "ARMv" STR2(XMRIG_ARM)
#else
# if defined(__x86_64__) || defined(__amd64__) || defined(_M_X64) || defined(_M_AMD64)
# define APP_ARCH "x86-64"
# else
# define APP_ARCH "x86"
# endif
#endif
#ifdef XMRIG_64_BIT
# define APP_BITS "64 bit"
#else
# define APP_BITS "32 bit"
#endif
#endif // XMRIG_VERSION_H