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Author SHA1 Message Date
XMRig
f9e990d0f0 v6.22.2 2024-11-03 14:38:44 +07:00
XMRig
200f23bba7 Merge branch 'dev' 2024-11-03 14:38:00 +07:00
xmrig
4234b20e21 Update CHANGELOG.md 2024-11-03 14:31:17 +07:00
xmrig
c5d8b8265b Merge pull request #3571 from SChernykh/dev
Fix number of threads on the new Intel Core Ultra CPUs
2024-10-25 20:55:35 +07:00
SChernykh
77c14c8362 Fix number of threads on the new Intel Core Ultra CPUs 2024-10-25 13:44:24 +02:00
6 changed files with 10 additions and 9 deletions

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@@ -1,3 +1,7 @@
# v6.22.2
- [#3569](https://github.com/xmrig/xmrig/pull/3569) Fixed corrupted API output in some rare conditions.
- [#3571](https://github.com/xmrig/xmrig/pull/3571) Fixed number of threads on the new Intel Core Ultra CPUs.
# v6.22.1 # v6.22.1
- [#3531](https://github.com/xmrig/xmrig/pull/3531) Always reset nonce on RandomX dataset change. - [#3531](https://github.com/xmrig/xmrig/pull/3531) Always reset nonce on RandomX dataset change.
- [#3534](https://github.com/xmrig/xmrig/pull/3534) Fixed threads auto-config on Zen5. - [#3534](https://github.com/xmrig/xmrig/pull/3534) Fixed threads auto-config on Zen5.

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@@ -20,7 +20,7 @@ set(SOURCES_BACKEND_COMMON
src/backend/common/Workers.cpp src/backend/common/Workers.cpp
) )
if (WITH_BENCHMARK AND (WITH_RANDOMX OR WITH_GHOSTRIDER)) if (WITH_RANDOMX AND WITH_BENCHMARK)
list(APPEND HEADERS_BACKEND_COMMON list(APPEND HEADERS_BACKEND_COMMON
src/backend/common/benchmark/Benchmark.h src/backend/common/benchmark/Benchmark.h
src/backend/common/benchmark/BenchState_test.h src/backend/common/benchmark/BenchState_test.h

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@@ -342,7 +342,7 @@ void xmrig::HwlocCpuInfo::processTopLevelCache(hwloc_obj_t cache, const Algorith
} }
# ifdef XMRIG_ALGO_RANDOMX # ifdef XMRIG_ALGO_RANDOMX
if ((algorithm.family() == Algorithm::RANDOM_X) && L3_exclusive && (PUs > cores.size()) && (PUs < cores.size() * 2)) { if ((vendor() == VENDOR_INTEL) && (algorithm.family() == Algorithm::RANDOM_X) && L3_exclusive && (PUs < cores.size() * 2)) {
// Use all L3+L2 on latest Intel CPUs with P-cores, E-cores and exclusive L3 cache // Use all L3+L2 on latest Intel CPUs with P-cores, E-cores and exclusive L3 cache
cacheHashes = (L3 + L2) / scratchpad; cacheHashes = (L3 + L2) / scratchpad;
} }

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@@ -259,7 +259,7 @@ if (WITH_KAWPOW OR WITH_GHOSTRIDER)
endif() endif()
if (WITH_BENCHMARK AND (WITH_RANDOMX OR WITH_GHOSTRIDER)) if (WITH_RANDOMX AND WITH_BENCHMARK)
add_definitions(/DXMRIG_FEATURE_BENCHMARK) add_definitions(/DXMRIG_FEATURE_BENCHMARK)
list(APPEND HEADERS_BASE list(APPEND HEADERS_BASE

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@@ -333,8 +333,8 @@ void benchmark()
const CnHash::AlgoVariant* av = Cpu::info()->hasAES() ? av_hw_aes : av_soft_aes; const CnHash::AlgoVariant* av = Cpu::info()->hasAES() ? av_hw_aes : av_soft_aes;
uint8_t buf[80] = { 0 }; uint8_t buf[80];
uint8_t hash[32 * 8] = { 0 }; uint8_t hash[32 * 8];
LOG_VERBOSE("%24s | N | Hashrate", "Algorithm"); LOG_VERBOSE("%24s | N | Hashrate", "Algorithm");
LOG_VERBOSE("-------------------------|-----|-------------"); LOG_VERBOSE("-------------------------|-----|-------------");
@@ -540,13 +540,10 @@ HelperThread* create_helper_thread(int64_t cpu_index, int priority, const std::v
}); });
if (hwloc_bitmap_weight(helper_cpu_set) > 0) { if (hwloc_bitmap_weight(helper_cpu_set) > 0) {
hwloc_bitmap_free(main_threads_set);
return new HelperThread(helper_cpu_set, priority, is8MB); return new HelperThread(helper_cpu_set, priority, is8MB);
} }
} }
} }
hwloc_bitmap_free(helper_cpu_set);
hwloc_bitmap_free(main_threads_set);
#endif #endif
return nullptr; return nullptr;

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@@ -22,7 +22,7 @@
#define APP_ID "xmrig" #define APP_ID "xmrig"
#define APP_NAME "XMRig" #define APP_NAME "XMRig"
#define APP_DESC "XMRig miner" #define APP_DESC "XMRig miner"
#define APP_VERSION "6.22.2-dev" #define APP_VERSION "6.22.2"
#define APP_DOMAIN "xmrig.com" #define APP_DOMAIN "xmrig.com"
#define APP_SITE "www.xmrig.com" #define APP_SITE "www.xmrig.com"
#define APP_COPYRIGHT "Copyright (C) 2016-2024 xmrig.com" #define APP_COPYRIGHT "Copyright (C) 2016-2024 xmrig.com"