Merge f0f6d1666c into 7e4caa8929

scripts/randomx_boost.sh

@@ -8,7 +8,7 @@ else
 	modprobe msr allow_writes=on
 fi
 
-if grep -E 'AMD Ryzen|AMD EPYC|AuthenticAMD' /proc/cpuinfo > /dev/null;
+if grep -E 'AMD Ryzen|AMD EPYC' /proc/cpuinfo > /dev/null;
 	then
 	if grep "cpu family[[:space:]]\{1,\}:[[:space:]]25" /proc/cpuinfo > /dev/null;
 		then
@@ -28,14 +28,6 @@ if grep -E 'AMD Ryzen|AMD EPYC|AuthenticAMD' /proc/cpuinfo > /dev/null;
 					wrmsr -a 0xc001102b 0x2000cc10
 					echo "MSR register values for Zen3 applied"
 				fi
-		elif grep "cpu family[[:space:]]\{1,\}:[[:space:]]26" /proc/cpuinfo > /dev/null;
-			then
-				echo "Detected Zen5 CPU"
-				wrmsr -a 0xc0011020 0x4400000000000
-				wrmsr -a 0xc0011021 0x4000000000040
-				wrmsr -a 0xc0011022 0x8680000401570000
-				wrmsr -a 0xc001102b 0x2040cc10
-				echo "MSR register values for Zen5 applied"
 		else
 			echo "Detected Zen1/Zen2 CPU"
 			wrmsr -a 0xc0011020 0

src/backend/cpu/CpuWorker.cpp

@@ -359,9 +359,7 @@ void xmrig::CpuWorker<N>::start()
             }
         }
 
-        if (!Nonce::isPaused()) {
+        consumeJob();
-            consumeJob();
-        }
     }
 }
 

src/backend/cpu/platform/HwlocCpuInfo.cpp

@@ -326,8 +326,7 @@ void xmrig::HwlocCpuInfo::processTopLevelCache(hwloc_obj_t cache, const Algorith
         }
     }
 
-    // This code is supposed to run only on Intel CPUs
+    if (scratchpad == 2 * oneMiB) {
-    if ((vendor() == VENDOR_INTEL) && (scratchpad == 2 * oneMiB)) {
         if (L2 && (cores.size() * oneMiB) == L2 && L2_associativity == 16 && L3 >= L2) {
             L3    = L2;
             extra = L2;

src/backend/cuda/CudaWorker.cpp

@@ -158,7 +158,7 @@ void xmrig::CudaWorker::start()
             std::this_thread::yield();
         }
 
-        if (isReady() && !consumeJob()) {
+        if (!consumeJob()) {
             return;
         }
     }

src/backend/opencl/OclWorker.cpp

@@ -190,7 +190,7 @@ void xmrig::OclWorker::start()
             std::this_thread::yield();
         }
 
-        if (isReady() && !consumeJob()) {
+        if (!consumeJob()) {
             return;
         }
     }

src/core/Miner.cpp

@@ -576,11 +576,6 @@ void xmrig::Miner::setJob(const Job &job, bool donate)
 
 #   ifdef XMRIG_ALGO_RANDOMX
     const bool ready = d_ptr->initRX();
-
-    // Always reset nonce on RandomX dataset change
-    if (!ready) {
-        d_ptr->reset = true;
-    }
 #   else
     constexpr const bool ready = true;
 #   endif

src/crypto/randomx/jit_compiler_x86.cpp

@@ -267,8 +267,8 @@ namespace randomx {
 						initDatasetAVX2 = false;
 						break;
 					case xmrig::ICpuInfo::ARCH_ZEN5:
-						// AVX2 init is 49% faster on Zen5
+						// TODO: test it
-						initDatasetAVX2 = true;
+						initDatasetAVX2 = false;
 						break;
 					}
 				}

src/crypto/rx/RxConfig.cpp

@@ -60,6 +60,8 @@ static const std::array<MsrItems, kMsrArraySize> msrPresets = {
     MsrItems{{ 0xC0011020, 0ULL }, { 0xC0011021, 0x40ULL, ~0x20ULL }, { 0xC0011022, 0x1510000ULL }, { 0xC001102b, 0x2000cc16ULL }},
     MsrItems{{ 0xC0011020, 0x0004480000000000ULL }, { 0xC0011021, 0x001c000200000040ULL, ~0x20ULL }, { 0xC0011022, 0xc000000401570000ULL }, { 0xC001102b, 0x2000cc10ULL }},
     MsrItems{{ 0xC0011020, 0x0004400000000000ULL }, { 0xC0011021, 0x0004000000000040ULL, ~0x20ULL }, { 0xC0011022, 0x8680000401570000ULL }, { 0xC001102b, 0x2040cc10ULL }},
+
+    // TODO: Tune it for Zen5 when it's available
     MsrItems{{ 0xC0011020, 0x0004400000000000ULL }, { 0xC0011021, 0x0004000000000040ULL, ~0x20ULL }, { 0xC0011022, 0x8680000401570000ULL }, { 0xC001102b, 0x2040cc10ULL }},
 
     MsrItems{{ 0x1a4, 0xf }},