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4 Commits
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1e5bc359fb
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1e5bc359fb | ||
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1ed99453dd | ||
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26f4936f6f | ||
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a411ee3565 |
@@ -352,7 +352,7 @@ void xmrig::CpuBackend::setJob(const Job &job)
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const auto &cpu = d_ptr->controller->config()->cpu();
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auto threads = cpu.get(d_ptr->controller->miner(), job.algorithm());
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if (!d_ptr->threads.empty() && d_ptr->threads.size() == threads.size() && std::equal(d_ptr->threads.begin(), d_ptr->threads.end(), threads.begin())) {
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if (!d_ptr->threads.empty() && d_ptr->threads.size() == threads.size() && std::equal(d_ptr->threads.begin(), d_ptr->threads.end(), threads.begin()) && d_ptr->algo == job.algorithm()) {
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return;
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}
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@@ -267,8 +267,8 @@ namespace randomx {
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initDatasetAVX2 = false;
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break;
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case xmrig::ICpuInfo::ARCH_ZEN5:
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// TODO: test it
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initDatasetAVX2 = false;
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// AVX2 init is 49% faster on Zen5
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initDatasetAVX2 = true;
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break;
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}
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}
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@@ -60,8 +60,6 @@ static const std::array<MsrItems, kMsrArraySize> msrPresets = {
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MsrItems{{ 0xC0011020, 0ULL }, { 0xC0011021, 0x40ULL, ~0x20ULL }, { 0xC0011022, 0x1510000ULL }, { 0xC001102b, 0x2000cc16ULL }},
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MsrItems{{ 0xC0011020, 0x0004480000000000ULL }, { 0xC0011021, 0x001c000200000040ULL, ~0x20ULL }, { 0xC0011022, 0xc000000401570000ULL }, { 0xC001102b, 0x2000cc10ULL }},
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MsrItems{{ 0xC0011020, 0x0004400000000000ULL }, { 0xC0011021, 0x0004000000000040ULL, ~0x20ULL }, { 0xC0011022, 0x8680000401570000ULL }, { 0xC001102b, 0x2040cc10ULL }},
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// TODO: Tune it for Zen5 when it's available
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MsrItems{{ 0xC0011020, 0x0004400000000000ULL }, { 0xC0011021, 0x0004000000000040ULL, ~0x20ULL }, { 0xC0011022, 0x8680000401570000ULL }, { 0xC001102b, 0x2040cc10ULL }},
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MsrItems{{ 0x1a4, 0xf }},
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