Merge pull request #3646 from SChernykh/dev

Optimized autoconfig for AMD CPUs with < 2 MB L3 cache per thread
2025-12-06 23:52:38 -05:00 · 2025-03-22 18:36:09 +07:00 · 2025-03-22 11:34:23 +01:00
1 changed files with 7 additions and 2 deletions
--- a/src/backend/cpu/platform/HwlocCpuInfo.cpp
+++ b/src/backend/cpu/platform/HwlocCpuInfo.cpp
@@ -320,8 +320,13 @@ void xmrig::HwlocCpuInfo::processTopLevelCache(hwloc_obj_t cache, const Algorith
            L2 += l2->attr->cache.size;
            L2_associativity = l2->attr->cache.associativity;

-            if (L3_exclusive && l2->attr->cache.size >= scratchpad) {
-                extra += scratchpad;
+            if (L3_exclusive) {
+                if (vendor() == VENDOR_AMD) {
+                    extra += std::min<size_t>(l2->attr->cache.size, scratchpad);
+                }
+                else if (l2->attr->cache.size >= scratchpad) {
+                    extra += scratchpad;
+                }
            }
        }
    }
Author	SHA1	Message	Date
xmrig	36fdfa2694	Merge pull request #3646 from SChernykh/dev Optimized autoconfig for AMD CPUs with < 2 MB L3 cache per thread	2025-03-22 18:36:09 +07:00
SChernykh	6cfc02d24f	Optimized autoconfig for AMD CPUs with < 2 MB L3 cache per thread	2025-03-22 11:34:23 +01:00