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Merge xmrig v6.11.0 into master
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@@ -190,8 +190,8 @@
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r##part[1] = static_cast<uint32_t>(h##part[12] >> 32); \
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r##part[2] = static_cast<uint32_t>(h##part[13]); \
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r##part[3] = static_cast<uint32_t>(h##part[13] >> 32); \
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} \
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v4_random_math_init<ALGO>(code##part, height);
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v4_random_math_init<ALGO>(code##part, height); \
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}
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#define VARIANT4_RANDOM_MATH(part, al, ah, cl, bx0, bx1) \
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if (props.isR()) { \
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@@ -743,8 +743,18 @@ inline void cryptonight_single_hash(const uint8_t *__restrict__ input, size_t si
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# ifdef XMRIG_ALGO_CN_HEAVY
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if (props.isHeavy()) {
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int64_t n = ((int64_t*)&l0[interleaved_index<interleave>(idx0 & MASK)])[0];
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int32_t d = ((int32_t*)&l0[interleaved_index<interleave>(idx0 & MASK)])[2];
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int64_t q = n / (d | 0x5);
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int64_t d = ((int32_t*)&l0[interleaved_index<interleave>(idx0 & MASK)])[2];
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int64_t d5;
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# if defined(_MSC_VER) || (defined(__GNUC__) && (__GNUC__ == 8))
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d5 = d | 5;
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# else
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// Workaround for stupid GCC which converts to 32 bit before doing "| 5" and then converts back to 64 bit
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asm("mov %1, %0\n\tor $5, %0" : "=r"(d5) : "r"(d));
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# endif
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int64_t q = n / d5;
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((int64_t*)&l0[interleaved_index<interleave>(idx0 & MASK)])[0] = n ^ q;
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@@ -343,7 +343,7 @@ typedef union ALIGN_STRUCT(16) SIMDVec {
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// Older gcc does not define vld1q_u8_x4 type
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#if defined(__GNUC__) && !defined(__clang__) && \
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((__GNUC__ == 10 && (__GNUC_MINOR__ <= 1)) || \
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((__GNUC__ == 10 && (__GNUC_MINOR__ <= 2)) || \
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(__GNUC__ == 9 && (__GNUC_MINOR__ <= 3)) || \
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(__GNUC__ == 8 && (__GNUC_MINOR__ <= 4)) || __GNUC__ <= 7)
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FORCE_INLINE uint8x16x4_t _sse2neon_vld1q_u8_x4(const uint8_t *p)
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