1
0
mirror of https://github.com/xmrig/xmrig.git synced 2026-04-18 05:22:28 -04:00

RISC-V: vectorized RandomX main loop

This commit is contained in:
SChernykh
2025-12-26 21:11:11 +01:00
parent 99488751f1
commit f661e1eb30
18 changed files with 1460 additions and 97 deletions

View File

@@ -34,7 +34,7 @@ struct riscv_cpu_desc
bool has_vector = false;
bool has_crypto = false;
inline bool isReady() const { return !model.isNull(); }
inline bool isReady() const { return !isa.isNull(); }
};
static bool lookup_riscv(char *line, const char *pattern, String &value)
@@ -82,7 +82,7 @@ static bool read_riscv_cpuinfo(riscv_cpu_desc *desc)
if (lookup_riscv(buf, "isa", desc->isa)) {
// Check for vector extensions
if (strstr(buf, "zve") || strstr(buf, "v_")) {
if (strstr(buf, "zve64d") || strstr(buf, "v_")) {
desc->has_vector = true;
}
// Check for crypto extensions (AES, SHA, etc.)
@@ -96,7 +96,7 @@ static bool read_riscv_cpuinfo(riscv_cpu_desc *desc)
lookup_riscv(buf, "uarch", desc->uarch);
if (desc->isReady() && !desc->isa.isNull()) {
if (desc->isReady()) {
break;
}
}