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https://github.com/xmrig/xmrig.git
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RISC-V: detect and use hardware AES
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@@ -34,7 +34,7 @@ namespace xmrig {
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extern String cpu_name_riscv();
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extern bool has_riscv_vector();
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extern bool has_riscv_crypto();
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extern bool has_riscv_aes();
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} // namespace xmrig
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@@ -58,8 +58,8 @@ xmrig::BasicCpuInfo::BasicCpuInfo() :
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// Check for vector extensions
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m_flags.set(FLAG_RISCV_VECTOR, has_riscv_vector());
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// Check for crypto extensions (Zknd/Zkne/Zknh - AES and SHA)
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m_flags.set(FLAG_AES, has_riscv_crypto());
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// Check for AES extensions (Zknd/Zkne)
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m_flags.set(FLAG_AES, has_riscv_aes());
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// RISC-V typically supports 1GB huge pages
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m_flags.set(FLAG_PDPE1GB, std::ifstream("/sys/kernel/mm/hugepages/hugepages-1048576kB/nr_hugepages").good());
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@@ -32,7 +32,7 @@ struct riscv_cpu_desc
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String isa;
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String uarch;
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bool has_vector = false;
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bool has_crypto = false;
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bool has_aes = false;
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inline bool isReady() const { return !isa.isNull(); }
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};
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@@ -82,15 +82,13 @@ static bool read_riscv_cpuinfo(riscv_cpu_desc *desc)
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if (lookup_riscv(buf, "isa", desc->isa)) {
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// Check for vector extensions
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if (strstr(buf, "zve64d") || strstr(buf, "v_")) {
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if (strstr(buf, "zve64d") || strstr(buf, "v_") || strstr(buf, "vh_")) {
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desc->has_vector = true;
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}
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// Check for crypto extensions (AES, SHA, etc.)
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// zkn* = NIST crypto suite, zks* = SM crypto suite
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// Note: zba/zbb/zbc/zbs are bit-manipulation, NOT crypto
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if (strstr(buf, "zknd") || strstr(buf, "zkne") || strstr(buf, "zknh") ||
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strstr(buf, "zksed") || strstr(buf, "zksh")) {
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desc->has_crypto = true;
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// AES support requires both zknd and zkne extensions (they can be shown as a part of "zk" or "zkn")
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if (strstr(buf, "zk_") || strstr(buf, "zkn_") || (strstr(buf, "zknd_") && strstr(buf, "zkne_"))) {
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desc->has_aes = true;
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}
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}
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@@ -128,11 +126,11 @@ bool has_riscv_vector()
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return false;
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}
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bool has_riscv_crypto()
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bool has_riscv_aes()
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{
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riscv_cpu_desc desc;
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if (read_riscv_cpuinfo(&desc)) {
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return desc.has_crypto;
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return desc.has_aes;
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}
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return false;
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}
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