RISC-V: use vector hardware AES instead of scalar

src/crypto/randomx/tests/riscv64_zvkb.s

@@ -0,0 +1,13 @@
+/* RISC-V - test if the vector bit manipulation extension is present */
+
+.text
+.option arch, rv64gcv_zvkb
+.global main
+
+main:
+	vsetivli zero, 8, e32, m1, ta, ma
+	vror.vv v0, v0, v0
+	vror.vx v0, v0, x5
+	vror.vi v0, v0, 1
+	li x10, 0
+	ret

src/crypto/randomx/tests/riscv64_zvkned.s

@@ -0,0 +1,12 @@
+/* RISC-V - test if the vector bit manipulation extension is present */
+
+.text
+.option arch, rv64gcv_zvkned
+.global main
+
+main:
+	vsetivli zero, 8, e32, m1, ta, ma
+	vaesem.vv v0, v0
+	vaesdm.vv v0, v0
+	li x10, 0
+	ret