Adjust panthera code for MSVC 2019 compilation (fixes #41)

src/crypto/randomx/panthera/yespower-opt.c

@@ -49,6 +49,7 @@
  * no slowdown from the prefixes is generally observed on AMD CPUs supporting
  * XOP, some slowdown is sometimes observed on Intel CPUs with AVX.
  */
+#if !defined(_MSC_VER)
 #ifdef __XOP__
 #warning "Note: XOP is enabled.  That's great."
 #elif defined(__AVX__)
@@ -60,6 +61,7 @@
 #else
 #warning "Note: building generic code for non-x86.  That's OK."
 #endif
+#endif
 
 /*
  * The SSE4 code version has fewer instructions than the generic SSE2 version,
@@ -102,6 +104,10 @@
 
 #include "yespower-platform.c"
 
+#if defined(_MSC_VER)
+#define __thread
+#endif
+
 #if __STDC_VERSION__ >= 199901L
 /* Have restrict */
 #elif defined(__GNUC__)
@@ -527,7 +533,9 @@ static volatile uint64_t Smask2var = Smask2;
 /* 64-bit without AVX.  This relies on out-of-order execution and register
  * renaming.  It may actually be fastest on CPUs with AVX(2) as well - e.g.,
  * it runs great on Haswell. */
+#if !defined(_MSC_VER)
 #warning "Note: using x86-64 inline assembly for pwxform.  That's great."
+#endif
 #undef MAYBE_MEMORY_BARRIER
 #define MAYBE_MEMORY_BARRIER \
 	__asm__("" : : : "memory");