mirrors/xmrig
1
0
Fork 1
mirror of https://github.com/xmrig/xmrig.git synced 2025-12-06 15:42:38 -05:00
Code Issues Projects Releases Wiki Activity

Merge pull request #3665 from SChernykh/dev

Browse Source 
Tweaked autoconfig for AMD CPUs with < 2 MB L3 cache per thread
This commit is contained in:
xmrig
2025-06-11 23:40:46 +07:00
committed by GitHub
parent d4e57d9427 e4c30eb0dd
commit 2ab7f85ccd
1 changed files with 2 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/backend/cpu/platform/HwlocCpuInfo.cpp
View File

@@ -322,7 +322,8 @@ void xmrig::HwlocCpuInfo::processTopLevelCache(hwloc_obj_t cache, const Algorith
if (L3_exclusive) { if (L3_exclusive) {
if (vendor() == VENDOR_AMD) { if (vendor() == VENDOR_AMD) {
extra += std::min<size_t>(l2->attr->cache.size, scratchpad); // For some reason, AMD CPUs can use only half of the exclusive L2/L3 cache combo efficiently
extra += std::min<size_t>(l2->attr->cache.size / 2, scratchpad);
} }
else if (l2->attr->cache.size >= scratchpad) { else if (l2->attr->cache.size >= scratchpad) {
extra += scratchpad; extra += scratchpad;