Merge xmrig v6.3.4 sources

src/backend/common/WorkerJob.h

@@ -66,14 +66,12 @@ public:
 
     inline bool nextRound(uint32_t rounds, uint32_t roundSize)
     {
-        bool ok = true;
         m_rounds[index()]++;
 
         if ((m_rounds[index()] % rounds) == 0) {
             for (size_t i = 0; i < N; ++i) {
-                *nonce(i) = Nonce::next(index(), *nonce(i), rounds * roundSize, currentJob().isNicehash(), &ok);
-                if (!ok) {
-                    break;
+                if (!Nonce::next(index(), nonce(i), rounds * roundSize, nonceMask())) {
+                    return false;
                 }
             }
         }
@@ -83,13 +81,14 @@ public:
             }
         }
 
-        return ok;
+        return true;
     }
 
 
 private:
     inline int32_t nonceOffset() const  { return currentJob().nonceOffset(); }
     inline size_t nonceSize() const     { return currentJob().nonceSize(); }
+    inline uint64_t nonceMask() const     { return m_nonce_mask[index()]; }
 
     inline void save(const Job &job, uint32_t reserveCount, Nonce::Backend backend)
     {
@@ -97,12 +96,13 @@ private:
         const size_t size = job.size();
         m_jobs[index()]   = job;
         m_rounds[index()] = 0;
+        m_nonce_mask[index()] = job.nonceMask();
 
         m_jobs[index()].setBackend(backend);
 
         for (size_t i = 0; i < N; ++i) {
             memcpy(m_blobs[index()] + (i * size), job.blob(), size);
-            *nonce(i) = Nonce::next(index(), *nonce(i), reserveCount, job.isNicehash());
+            Nonce::next(index(), nonce(i), reserveCount, nonceMask());
         }
     }
 
@@ -110,6 +110,7 @@ private:
     alignas(16) uint8_t m_blobs[2][Job::kMaxBlobSize * N]{};
     Job m_jobs[2];
     uint32_t m_rounds[2] = { 0, 0 };
+    uint64_t m_nonce_mask[2];
     uint64_t m_sequence  = 0;
     uint8_t m_index      = 0;
 };
@@ -125,41 +126,23 @@ inline uint32_t *xmrig::WorkerJob<1>::nonce(size_t)
 template<>
 inline bool xmrig::WorkerJob<1>::nextRound(uint32_t rounds, uint32_t roundSize)
 {
-    bool ok = true;
     m_rounds[index()]++;
 
     uint32_t* n = nonce();
-    const uint32_t prev_nonce = *n;
 
     if ((m_rounds[index()] % rounds) == 0) {
-        *n = Nonce::next(index(), *n, rounds * roundSize, currentJob().isNicehash(), &ok);
+        if (!Nonce::next(index(), n, rounds * roundSize, nonceMask())) {
+            return false;
+        }
+        if (nonceSize() == sizeof(uint64_t)) {
+            m_jobs[index()].nonce()[1] = n[1];
+        }
     }
     else {
         *n += roundSize;
     }
 
-    // Increment higher 32 bits of a 64-bit nonce when lower 32 bits overflow
-    if (!currentJob().isNicehash() && (nonceSize() == sizeof(uint64_t))) {
-        const bool wrapped = (*n < prev_nonce);
-        const bool wraps_this_round = (static_cast<uint64_t>(*n) + roundSize > (1ULL << 32));
-
-        // Account for the case when starting nonce hasn't wrapped yet, but some nonces in the current round will wrap
-        if (wrapped || wraps_this_round) {
-            // Set lower 32 bits to 0 when higher 32 bits change
-            Nonce::reset(index());
-
-            // Sets *n to 0 and Nonce::m_nonce[index] to the correct next value
-            *n = 0;
-            Nonce::next(index(), *n, rounds * roundSize, currentJob().isNicehash(), &ok);
-
-            ++n[1];
-
-            Job& job = m_jobs[index()];
-            memcpy(job.blob(), blob(), job.size());
-        }
-    }
-
-    return ok;
+    return true;
 }
 
 
@@ -169,11 +152,12 @@ inline void xmrig::WorkerJob<1>::save(const Job &job, uint32_t reserveCount, Non
     m_index           = job.index();
     m_jobs[index()]   = job;
     m_rounds[index()] = 0;
+    m_nonce_mask[index()] = job.nonceMask();
 
     m_jobs[index()].setBackend(backend);
 
     memcpy(blob(), job.blob(), job.size());
-    *nonce() = Nonce::next(index(), *nonce(), reserveCount, currentJob().isNicehash());
+    Nonce::next(index(), nonce(), reserveCount, nonceMask());
 }
 
 

src/backend/cpu/interfaces/ICpuInfo.h

@@ -63,6 +63,7 @@ public:
         FLAG_PDPE1GB,
         FLAG_SSE2,
         FLAG_SSSE3,
+        FLAG_SSE41,
         FLAG_XOP,
         FLAG_POPCNT,
         FLAG_CAT_L3,
@@ -97,6 +98,7 @@ public:
     virtual size_t packages() const                                                 = 0;
     virtual size_t threads() const                                                  = 0;
     virtual Vendor vendor() const                                                   = 0;
+    virtual bool jccErratum() const                                                 = 0;
 };
 
 

src/backend/cpu/platform/BasicCpuInfo.cpp

@@ -57,7 +57,7 @@
 namespace xmrig {
 
 
-static const std::array<const char *, ICpuInfo::FLAG_MAX> flagNames     = { "aes", "avx2", "avx512f", "bmi2", "osxsave", "pdpe1gb", "sse2", "ssse3", "xop", "popcnt", "cat_l3" };
+static const std::array<const char *, ICpuInfo::FLAG_MAX> flagNames     = { "aes", "avx2", "avx512f", "bmi2", "osxsave", "pdpe1gb", "sse2", "ssse3", "sse4.1", "xop", "popcnt", "cat_l3" };
 static const std::array<const char *, ICpuInfo::MSR_MOD_MAX> msrNames   = { "none", "ryzen", "intel", "custom" };
 
 
@@ -141,6 +141,7 @@ static inline bool has_bmi2()       { return has_feature(EXTENDED_FEATURES,
 static inline bool has_pdpe1gb()    { return has_feature(PROCESSOR_EXT_INFO,    EDX_Reg, 1 << 26); }
 static inline bool has_sse2()       { return has_feature(PROCESSOR_INFO,        EDX_Reg, 1 << 26); }
 static inline bool has_ssse3()      { return has_feature(PROCESSOR_INFO,        ECX_Reg, 1 << 9); }
+static inline bool has_sse41()      { return has_feature(PROCESSOR_INFO,        ECX_Reg, 1 << 19); }
 static inline bool has_xop()        { return has_feature(0x80000001,            ECX_Reg, 1 << 11); }
 static inline bool has_popcnt()     { return has_feature(PROCESSOR_INFO,        ECX_Reg, 1 << 23); }
 static inline bool has_cat_l3()     { return has_feature(EXTENDED_FEATURES,     EBX_Reg, 1 << 15) && has_feature(0x10, EBX_Reg, 1 << 1); }
@@ -177,6 +178,7 @@ xmrig::BasicCpuInfo::BasicCpuInfo() :
     m_flags.set(FLAG_PDPE1GB, has_pdpe1gb());
     m_flags.set(FLAG_SSE2,    has_sse2());
     m_flags.set(FLAG_SSSE3,   has_ssse3());
+    m_flags.set(FLAG_SSE41,   has_sse41());
     m_flags.set(FLAG_XOP,     has_xop());
     m_flags.set(FLAG_POPCNT,  has_popcnt());
     m_flags.set(FLAG_CAT_L3,  has_cat_l3());
@@ -210,6 +212,37 @@ xmrig::BasicCpuInfo::BasicCpuInfo() :
             m_vendor   = VENDOR_INTEL;
             m_assembly = Assembly::INTEL;
             m_msrMod   = MSR_MOD_INTEL;
+
+            struct
+            {
+                unsigned int stepping : 4;
+                unsigned int model : 4;
+                unsigned int family : 4;
+                unsigned int processor_type : 2;
+                unsigned int reserved1 : 2;
+                unsigned int ext_model : 4;
+                unsigned int ext_family : 8;
+                unsigned int reserved2 : 4;
+            } processor_info;
+
+            cpuid(1, data);
+            memcpy(&processor_info, data, sizeof(processor_info));
+
+            // Intel JCC erratum mitigation
+            if (processor_info.family == 6) {
+                const uint32_t model = processor_info.model | (processor_info.ext_model << 4);
+                const uint32_t stepping = processor_info.stepping;
+
+                // Affected CPU models and stepping numbers are taken from https://www.intel.com/content/dam/support/us/en/documents/processors/mitigations-jump-conditional-code-erratum.pdf
+                m_jccErratum =
+                    ((model == 0x4E) && (stepping == 0x3)) ||
+                    ((model == 0x55) && (stepping == 0x4)) ||
+                    ((model == 0x5E) && (stepping == 0x3)) ||
+                    ((model == 0x8E) && (stepping >= 0x9) && (stepping <= 0xC)) ||
+                    ((model == 0x9E) && (stepping >= 0x9) && (stepping <= 0xD)) ||
+                    ((model == 0xA6) && (stepping == 0x0)) ||
+                    ((model == 0xAE) && (stepping == 0xA));
+            }
         }
     }
 #   endif

src/backend/cpu/platform/BasicCpuInfo.h

@@ -61,11 +61,13 @@ protected:
     inline size_t packages() const override         { return 1; }
     inline size_t threads() const override          { return m_threads; }
     inline Vendor vendor() const override           { return m_vendor; }
+    inline bool jccErratum() const override         { return m_jccErratum; }
 
 protected:
     char m_brand[64 + 6]{};
     size_t m_threads;
     Vendor m_vendor         = VENDOR_UNKNOWN;
+    bool m_jccErratum       = false;
 
 private:
     Assembly m_assembly     = Assembly::NONE;

src/backend/opencl/cl/cn/cryptonight.cl

@@ -899,7 +899,7 @@ __kernel void Blake(__global ulong *states, __global uint *BranchBuf, __global u
 
         ((uint8 *)h)[0] = vload8(0U, c_IV256);
 
-        for (uint i = 0; i < 3; ++i) {
+        for (volatile uint i = 0; i < 3; ++i) {
             ((uint16 *)m)[0] = vload16(i, (__global uint *)states);
             for (uint x = 0; x < 16; ++x) {
                 m[x] = SWAP4(m[x]);

src/backend/opencl/cl/cn/cryptonight_cl.h

@@ -2,7 +2,7 @@
 
 namespace xmrig {
 
-static const char cryptonight_cl[61023] = {
+static const char cryptonight_cl[61032] = {
     0x23,0x69,0x66,0x64,0x65,0x66,0x20,0x63,0x6c,0x5f,0x63,0x6c,0x61,0x6e,0x67,0x5f,0x73,0x74,0x6f,0x72,0x61,0x67,0x65,0x5f,0x63,0x6c,0x61,0x73,0x73,0x5f,0x73,0x70,
     0x65,0x63,0x69,0x66,0x69,0x65,0x72,0x73,0x0a,0x23,0x70,0x72,0x61,0x67,0x6d,0x61,0x20,0x4f,0x50,0x45,0x4e,0x43,0x4c,0x20,0x45,0x58,0x54,0x45,0x4e,0x53,0x49,0x4f,
     0x4e,0x20,0x63,0x6c,0x5f,0x63,0x6c,0x61,0x6e,0x67,0x5f,0x73,0x74,0x6f,0x72,0x61,0x67,0x65,0x5f,0x63,0x6c,0x61,0x73,0x73,0x5f,0x73,0x70,0x65,0x63,0x69,0x66,0x69,
@@ -1826,90 +1826,91 @@ static const char cryptonight_cl[61023] = {
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 };
 
 } // namespace xmrig